CY28339ZC

CY28339 Intel CK408 Mobile Clock Synthesizer Features • Compliant with Intel® CK 408 rev 1.1 Mobile Clock Synthesizer specifications • 3.3V power supply • Two differential CPU clocks • Nine copies of PCI clocks • Three copies configurable PCI free-running clocks • Two 48 MHz clocks (USB, DOT) • Five/six copies of 3V66 clocks Table 1. Frequency S2 1 1 0 0 M S1 0 1 0 1 0 Table[1] 3V66 66M 66M 66M 66M TCLK/4 66BUFF(0:2)/ 3V66(0:4) 66IN 66IN 66M 66M TCLK/4 66IN/3V66–5 66-MHz clock input 66-MHZ clock input 66M 66M TCLK/4 PCIF, PCI 66IN/2 66IN/2 33 M 33 M TCLK/8 REF 14.318M 14.318M 14.318M 14.318M TCLK USB/ DOT 48M 48M 48M 48M TCLK/2 • One VCH clock • One reference clock at 14.318 MHz • SMBus support with read-back capabilities • Ideal Lexmark profile Spread Spectrum electromagnetic interference (EMI) reduction • Dial-a-Frequency™ features • Dial-a-dB™ features • 48-pin TSSOP package CPU (1:2) 100M 133M 100M 133M TCLK/2 Block Diagram X1 X2 Pin Configuration VDD_REF PWR XTAL OSC REF XIN XOUT GND_REF VDD_CPU CPUT1:2 CPUC1:2 VDD_PCI PCIF Stop Clock Control Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 VDD_REF REF S1 CPU_STOP# VDD_CPU CPUT1 CPUC1 GND_CPU VDD_CPU CPUT2 CPUC2 IREF S2 USB_48MHz DOT_48MHz VDD_48 MHz GND_48 MHz 3V66_1/VCH PCI_STOP# 3V66_0 VDD_3V66 GND_3V66 SCLK SDATA PLL Ref Freq PLL 1 S1:2 VTT_PWRGD## CPU_STOP# Gate Divider Network PWR Stop Clock Control PCI7 PCI8 PCIF GND_PCI PCI0 PCI1 PCI2 VDD_PCI PCI4 PCI5 PCI6 VDD_3V66 GND_3V66 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 66IN/3V66_5 PD# VDD_CORE GND_CORE VTT_PWRGD# PWR PCI0:2 PCI4:8 CY28339 37 36 35 34 33 32 31 30 29 28 27 26 25 PCI_STOP# PD# PWR /2 VDD_3V66 3V66_0:1 PWR 3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN PLL 2 VDD_48MHz PWR USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1 SDATA SCLK SMBus Logic Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a 0 state will be latched into the device’s internal state register. Rev 1.0, November 25, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 17 www.SpectraLinear.com CY28339 Pin Definitions Pin Number 47 1 2 43, 42, 39, 38 29 31 20 17, 18, 19 6 REF0 XIN XOUT CPUT1,CPUC1 CPUT2, CPUC2 3V66_0 3V66_1/VCH 66IN/3V66_5 66BUFF [2:0] /3V66 [4:2] PCIF Name I/O 3.3V 14.318 MHz clock output. 14.318 MHz crystal input. 14.318 MHz crystal input. Differential CPU clock outputs. 3.3V 66 MHz clock output. 3.3V selectable through SMBus to be 66 MHz or 48 MHz. 66 MHz input to buffered 66BUFF and PCI or 66 MHz clock from internal VCO. 66 MHz buffered outputs from 66Input or 66 MHz clocks from internal VCO. 33 MHz clocks divided down from 66Input or divided down from 3V66; PCIF default is free-running. PCI clock outputs divided down from 66Input or divided down from 3V66; PCI [7:8] are configurable as free-running PCI through SMBus.[2] Fixed 48 MHz clock output. Fixed 48 MHz clock output. Special 3.3V three-level input for Mode selection. 3.3V LVTTL inputs for CPU frequency selection. A precision resistor is attached to this pin which is connected to the internal current reference. 3.3V LVTTL input for Power_Down# (active LOW). 3.3V LVTTL input for PCI_STOP# (active LOW). 3.3V LVTTL input for CPU_STOP# (active LOW). 3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1] inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. SMBus-compatible SDATA. SMBus-compatible SCLK. 3.3V power supply for outputs. Description 8, 9, 10, 12, 13, 14, PCI [0:2] 4, 5 PCI [4:6] PCI [7:8] 35 34 36 46 37 21 30 45 24 USB_48M DOT_48M S2 S1 IREF PD# PCI_STOP# CPU_STOP# VTT_PWRGD# 25 26 SDATA SCLK 11, 15, 28, 40, 44, VDD_PCI, 48 VDD_3V66, VDD_CPU,VDD_REF 33 22 VDD_48 MHz VDD_CORE 3.3V power supply for 48 MHz. 3.3V power supply for phase-locked loop (PLL). Ground for outputs. 3, 7, 16, 27, 32, 41 GND_REF, GND_PCI, GND_3V66, GND_IREF, GND_CPU 23 GND_CORE Note: 2. PCI3 is internally disabled and is not accessible. Ground for PLL. Rev 1.0, November 25, 2006 Page 2 of 17 CY28339 Two-Wire SMBus Control Interface The two-wire control interface implements a Read/Write slave only interface according to SMBus specification. The device will accept data written to the D2 address and data may read back from address D3. It will not respond to any other addresses, and previously set control registers are retained as long as power in maintained on the device. Serial Control Registers Following the acknowledge of the Address Byte, two additional bytes must be sent: 1. “Command code“ byte 2. “Byte count” byte. Although the data (bits) in the command is considered “don’t care,” it must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged. Byte 0: CPU Clock Register[3,4] Bit 7 6 @Pup 0 0 Name Description Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit. CPU Clock Power-down Mode Select. 0 = Drive CPUT to 2x IREF and drive CPUC LOW 1 = Tri-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to CPU_STOP#. 3V66_1/VCH 3V66_1/VCH Frequency Select 0 = 66M selected, 1 = 48M selected. This is a Read and Write control bit. Reserved HW HW HW 1 PCI_STOP# Reflects the current value of the internal PCI_STOP# function when read. Internally PCI_STOP# is a logical AND function of the internal SMBus register bit and the external PCI_STOP# pin. S2 S1 Frequency Select Bit 2. Reflects the value of S2. This bit is Read-only. Frequency Select Bit 1. Reflects the value of S1. This bit is Read-only. Reserved 5 4 3 2 1 0 0 Byte 1: CPU Clock Register Bit 7 6 @Pup 1 0 Name Reserved CPUT1, CPUC1 CPUT/C Output Functionality Control when CPU_STOP# is asserted. CPUT2, CPUC2 0 = Drive CPUT to 6x IREF and drive CPUC LOW 1 = three-state all CPU outputs. This bit will override Byte0,Bit6 such that even if it is 0, when PD# goes LOW the CPU outputs will be three-stated. CPUT2, CPUC2 CPUT/C2 Functionality Control when CPU_STOP# is asserted. 0 = Stopped LOW,1 = Free Running. This is a Read and Write control bit. CPUT1, CPUC1 CPUT/C1 Functionality Control When CPU_STOP# is asserted. 0 = Stopped LOW, 1 = Free Running. This is a Read and Write control bit. Reserved CPUT2, CPUC2 CPUT/C2 Output Control. 0 = disable, 1 = enabled. This is a Read and Write control bit. CPUT1, CPUC1 CPUT/C1 Output Control. 0 = disable, 1 = enabled. This is a Read and Write control bit. Reserved Description 5 4 3 2 1 0 0 0 0 1 1 1 Notes: 3. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V. 4. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up. Rev 1.0, November 25, 2006 Page 3 of 17 CY28339 Byte 2:PCI Clock Control Register (all bits are Read and Write functional) Bit @Pup Name 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 1 REF Description REF Output Control. 0 = high strength, 1 = low strength. PCI6 PCI6 Output Control. 0 = forced LOW, 1 = enabled PCI5 PCI5 Output Control. 0 = forced LOW, 1 = enabled PCI4 PCI4 Output Control. 0 = forced LOW, 1 = enabled Reserved PCI2 PCI2 Output Control. 0 = forced LOW, 1 = enabled PCI1 PCI1 Output Control. 0 = forced LOW, 1 = enabled PCI0 PCI0 Output Control. 0 = forced LOW, 1 = enabled Byte 3: PCIF Clock and 48M Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 0 1 1 1 1 1 Name Description DOT_48M DOT_48M Output Control. 0 = forced LOW, 1 = enabled USB_48M USB_48M Output Control. 0 = forced LOW,1 = enabled PCIF PCI8 PCI7 PCIF PCI_8 PCI_7 PCI_STOP# Control of PCIF. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. PCI_STOP# Control of PCI8. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. PCI_STOP# Control of PCI7. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. PCIF Output Control. 0 = forced LOW, 1 = running PCI_8 Output Control. 0 = forced LOW, 1 = running PCI_7 Output Control. 0 = forced LOW, 1 = running Byte 4: Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 1 1 1 1 1 3V66_0 3V66_1/VCH 3V66_5 19 18 66BUFF0/3V66_2 Name Reserved. Set = 0. 3V66_0 Output Enable. 0 = disable, 1 = enabled 3V66_1/VCH Output Enable. 0 = disable, 1 = enabled 3V66_5 Output Enable. 0 = disable, 1 = enabled 66BUFF2/3V66_4 Output Enable. 0 = disable, 1 = enabled 66BUFF1/3V66_3 Output Enable. 0 = disable, 1 = enabled 66BUFF0/3V66_2 Output Enable. 0 = disable, 1 = enabled Description SS2 Spread Spectrum Control Bit. 0 = down spread, 1 = center spread). Byte 5:Clock Control Register (all bits are Read and Write functional) Bit 7 6 5 4 3 2 1 0 @Pup 0 1 0 0 0 0 0 0 USB_48M DOT_48M Name Description SS1 Spread Spectrum Control Bit. SS0 Spread Spectrum Control Bit. 66IN to 66M delay Control MSB. 66IN to 66M delay Control LSB. Reserved. Set = 0. DOT_48M Edge Rate Control. When set to 1, the edge is slowed by 15%. Reserved. Set = 0. USB_48M edge rate control. When set to 1, the edge is slowed by 15%. Byte 6: Silicon Signature Register[5] (all bits are Read-only) Bit @Pup Name Description Rev 1.0, November 25, 2006 Page 4 of 17 CY28339 Byte 6: Silicon Signature Register[5] (all bits are Read-only) 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 1 Vendor Code = 0011 Revision = 0001 Byte 7: Reserved Register Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Reserved. Set = 0. Description Byte 8: Dial-a-Frequency Control Register N Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 N6, MSB N5 N4 N3 N2 N3 N0, LSB Name Reserved. Set = 0. These bits are for programming the PLL’s internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description Byte 9: Dial-a-Frequency Control Register R Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 R5, MSB R4 R3 R2 R1 R0 DAF_ENB R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from DAF (SMBus) registers. Name Reserved. Set = 0. These bits are for programming the PLL’s internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Description Note: 5. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored. Rev 1.0, November 25, 2006 Page 5 of 17 CY28339 Dial-a-Frequency Features SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. P is a large-value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 2. Table 2. P Value S(1:0) 00 01 10 11 P 32005333 48008000 96016000 64010667 Special Functions PCIF and IOAPIC Clock Outputs The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. Any two of the PCIF clock outputs can be used as IOAPIC 33-Mhz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event that these clocks are not required, they can be used as general PCI clocks or disabled via the assertion of the PCI_STOP# pin. 3V66_1/VCH Clock Output The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. Configured as DRCG (66M), SMBus Byte0, Bit 5 = “0” The default condition for this pin is to power-up in a 66M operation. In 66M operation this output is SSCG-capable and when spreading is turned on, this clock will be modulated. Configured as VCH (48M), SMBus Byte0, Bit 5 = “1” In this mode, output is configured as a 48-Mhz non-spread spectrum output that is phase-aligned with other 48M outputs (USB and DOT) to within 1-ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power-on. When the SMBus Bit 5 of Byte 0 is programmed from a “0” to a “1,” the 3V66_1/VCH output may glitch while transitioning to 48M output mode. PD# (Power-down) Clarification The PD# (power-down) pin is used to shut off all clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is LOW, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the LOW “stopped” state. PD# Assertion When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66BUFF, the 66BUFF clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 × Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. Dial-a-dB Features SMBus Dial-a-dB feature is available in this device via Byte8 and Byte9. Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. Table 3 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. Table 3. Spread Spectrum SS2 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Center Center Center Center Spread% +0.00, –0.25 +0.00, –0.50 +0.00, –0.75 +0.00, –1.00 +0.13, –0.13 +0.25, –0.25 +0.37, –0.37 +0.50, –1.50 3V66-0 PCI PCI_F Tpci Figure 1. Unbuffered Mode – 3V66_0 to PCI and PCIF Phase Relationship Rev 1.0, November 25, 2006 Page 6 of 17 CY28339 PWRDWN# CPUT 133MHz CPUC 133MHz PCI 33MHz 3V66 USB 48MHz REF 14.318MHz Figure 2. Power-down Assertion Timing Waveforms – Unbuffered Mode 6 6 B u ff P C IF PW RDW N# CPU 133M Hz CPU# 133M Hz 3V66 6 6 In USB 48M Hz R E F 1 4 .3 1 8 M H z Figure 3. Power-down Assertion Timing Waveforms Figure – Buffered Mode Rev 1.0, November 25, 2006 Page 7 of 17 CY28339 PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ms. 0.25mS VDDA = 2.0V Sample Inputs straps Wait for