SL15101ZIT-XXX

SL15101 Programmable Spread Spectrum Clock Generator (SSCG) Key Features Low power dissipation - 7.9mA-typ at 66MHz and VDD=3.3V - 7.0mA-typ at 66MHz and VDD=2.5V Wide 2.5V to 3.3V +/-10% power supply range Programmable 4 outputs from 3 to 200MHz Low Jitter - 110ps at 66MHz Programmable Center or Down Spread Modulation from 0.25 to 5.0% 8 to 48 MHz external crystal range 8 to 166 MHz external clock range Integrated internal voltage regulator Programmable PD#/OE/SSON#/FS functions Programmable CL at XIN and XOUT pins Programmable output rise and fall times Programmable modulation frequency from 30 to 120 kHz Description The SL15101 a programmable low power Spread Spectrum Clock Generator (SSCG) used for reducing Electromagnetic Interference (EMI). The product is designed using SpectraLinear proprietary programmable EProClock™ phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the input clock. The modulated clock can significantly reduce the measured EMI levels, and leading to the compliance with regulatory agency requirements. Up to 4 output clock frequencies, Spread %, output rise and fall times, crystal load, modulation frequency and PD#/OE/SSON#/FS functions can be programmed to meet the needs of wide range of applications. The SL15101 operates from 2.5V to 3.3V power supply voltage range. The product is offered in 8-pin TSSOP package with commercial and industrial grades. Refer to SL15L101 Programmable SSCG product for 1.8V power supply operation. Applications Printers, MFPs Digital Copiers NBPCs and LCD Monitors Routers, Servers and Switchers HDTV and DVD-R/W Benefits Peak EMI reduction of 8 to 16 dB Fast time-to-market Cost Reduction Reduction of PCB layers Eleminates the need for higher order crystals (Xtals) and crystal oscillators (XOs) Block Diagram Rev 1.8, August 10, 2007 Page 1 of 16 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL15101 Pin Configuration 8-Pin TSSOP Pin Description Pin Number 1 2 3 4 Pin Name VDD XOUT XIN/CLKIN SSCLK4 or REFCLK4 or PD# or OE Pin Type Power Output Input Output or Input Positive power supply. Pin Description Crystal or ceramic resonator output pin. Leave this pin unconnected (floating) if external clock is used at Pin-3. Crystal, ceramic resonator or external clock input pin. Multi function Programmable SSCLK4 or REFOUT4 clock pin or PD# or OE control pin. Power Down (PD#-Active Low): If PD#=0(Low) and Output Enable (OE-Active High). If PD# or OE is programmed, the pin is weakly pulled high to VDD. 5 6 7 8 VSS SSCLK1 or REFCLK1 SSCLK2 or REFCLK2 SSCLK3 or REFOUT3 or SSON# or FS Power Output Output Input Power supply ground. This pin can be programmed as SSCLK1 or REFCLK1. This pin can be programmed as SSCLK2 or REFCLK2. Multi function Programmable SSCLK3 or REFOUT3 clock pin or SSON# or FS control pin. Programmable SSON# or Frequency Select (FS) Control pin. If SSCG# function is programmed: Spread-on=0(Low) or Spread-off=1(High). If FS function is programmed: The clock frequencies can be switched between two sets of frequencies as programmed. If SSON# or FS is programmed, the pin weakly pulled low to VSS. Rev 1.8, August 10, 2007 Page 2 of 16 SL15101 General Description The primary source of EMI from digital circuits is the system clock and all the other synchronous clocks and control signals derived from the system clock. The well know techniques of filtering (suppression) and shielding (containment), while effective, can cost money, board space and longer development time. A more effective and efficient technique to reduce EMI is Spread Spectrum Clock Generator (SSCG) technique. Instead of using constant clock frequency, the SSCG technique modulates (spreads) the system clock with a much smaller frequency, to reduce EMI emissions at its source: The System Clock. The SL15101 is designed using SpectraLinear proprietary programmable EProClock™ phase-locked loop (PLL) and Spread Spectrum Technologies (SST) to synthesize and modulate (spread) the system clock such that the energy is spread out over a wider bandwidth. This reduces the peak value of the radiated emissions at the fundamental and the harmonics. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time-to-market without degrading system performance. The SL15101 operates from 3.3V to 2.5V power supply range. Refer to SL15L101 for 1.8V power supply operation. The SL15101 is available in 8-pin TSSOP package with extended Commercial Temperature range of 0 to 85 C and Industrial Temperature range of –40 to 85°C. Input Frequency Range The input frequency range is from 8.0 to 48.0 MHz for crystals and ceramic resonators. If an external clock is used, the input frequency range is from 8 to 166 MHz. Output Frequency Range and Outputs Up to four (4) outputs can be programmed as SSCLK or REFCLK. SSCLK output can be synthesized to any value from 3 to 200 MHz with spread based on valid input frequency. The spread at SSCLK pins can be stopped by SSON# input control pin, If SSON# pin is HIGH (VDD), the frequency at this pin is the synthesized to the nominal value of the input frequency and there is no spread. REFOUT is the buffered output of the oscillator and is the same frequency as the input frequency without spread. However, REFOUT value can also be divided by using the output dividers from 2 to 32. The SSCLK is the programmed and synthesized value of the input clock. The remaining SSCLKs could be the same value providing fanout of up to 4 or the frequency can be divided from also 2 to 32. In this case, the spread % value is the same as the original programmed spread % value. By using only first order crystals, SL15101 can synthesize output frequency up to 200 MHz, eliminating the need for higher order Crystals (Xtals) and Crystal Oscillators (XOs). This reduces the cost while improving the system clock accuracy, performance and reliability. Rev 1.8, August 10, 2007 Programmable CL (Crystal Load) The SL15101 provides programmable on-chip capacitors at XIN/CLKIN (Pin-3) and XOUT (Pin-2). The resolution of this programmable capacitor is 6-bits with LSB value of 0.5pF. When all bits are off the pin capacitance is CXIN=CXOUT =8.5pF (minimum value). When all bits are on the pin capacitance is CXIN=CXOUT=40pF (maximum value). The values of CXIN and CXOUT based on the CL (Crystal Load Capacitor) can be calculated as: CXIN=CXOUT=2CL-CPCB. Refer to the Page-13 for additional information on crystal load (CL). In addition, if an external clock is used, the capacitance at Pin-3 (CLKIN) can programmed to control the edge rate of this input clock, providing additional EMI control. Programmable Modulation Frequency The Spread Spectrum Clock (SSC) modulation default value is 31.5 kHz. The higher values of up to 120 kHz can also be programmed. Less than 30 kHz modulation frequency is not recommended to stay out of the range audio frequency bandwidth since this frequency could be detected as a noise by the audio receivers within the vicinity. Programmable Spread Percent (%) The spread percent (%) value is programmable from +/0.25% to +/-2.5% (center spread) or -0.5% to -5.0% (down spread) for all SSCLK frequencies. It is possible to program smaller or larger non-standard values of spread percent. Contact SLI if these non-standard spread percent values are required in the application. SSON# or Frequency Select (FS) The SL15101 Pin-8 can also be programmed as either SSON# to enable or disable the programmed spread percent value or as Frequency Select (FS). If SSON# is used, when this pin is pulled high (VDD), the spread is stopped and the frequency is the nominal value without spread. If low (GND), the frequency is the nominal value with the spread. If FS function is used, the output pins can be programmed for different set of frequencies as selected by FS. SSCLK value can be any frequency from 3 to 200MHz, but the spread % is the same percent value. REFOUT is the same frequency as the input reference clock or divide by from 2 to 32 without spread. The set of frequencies in Table 1 is given as en example, using 48MHz crystal. The SL15101 also allows a fan-out of up to 4, meaning that Pins 4, 6, 7 and 8 can be programmed to the same frequencies with or without spread. FS (Pin-8) 0 1 SSCLK1/2 (Pins-6/7) 66MHz, +/-2% 33MHz, +/-2% REFCLK4 (Pin-4) 48MHz 24MHz Table 1. Frequency Selection (FS) Power Down (PD#) or Output Enable (OE) The SL15101 Pin-4 can be programmed as either PD# or OE. PD# powers down the entire chip whereas OE only disables the output buffers to Hi-Z. Page 3 of 16 SL15101 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) JEDEC22-A114D In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min -0.5 -0.5 0 -40 -65 -4,000 -1,500 -250 -200 Max 4.6 VDD+0.5 85 85 150 125 260 4,000 1,500 250 200 Unit V V °C °C °C °C °C V V V mA ESD Rating (Charge Device Model) JEDEC22-C101C ESD Rating (Machine Model) Latch-up JEDEC22-A115D 125°C DC Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C Description Operating Voltage Input Low Voltage Symbol VDD VIL Condition VDD+/-10% CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS. IOH=10mA , If Pins 4, 6, 7 and 8 are programmed as SSCLK/REFCLK IOL=10mA, If Pins 4, 6, 7 and 8 are programmed as SSCLK/REFCLK VIN=VDD, Pins 4 and 8. If outputs are programmed as PD#, OE, SSON# or FS and no pull-up/down resister used VIN=GND, Pins 4 and 8. If outputs are programmed as PD#, OE, SSON# or FS and no pull-up/down resister used CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS Min 2.97 0 Typ 3.3 - Max 3.63 0.3VDD Unit V V Input High Voltage VIH 0.7VDD - VDD V Output High Voltage VOH1 VDD-0.5 - - V Output Low Voltage VOL1 - - 0.5 V Input High Current IIH -10 - 10 A Input Low Current IIL -10 - 10 A Pull-up or Down Resistors RPU/D 90 160 230 k Rev 1.8, August 10, 2007 Page 4 of 16 SL15101 Operating Supply Current Standby Current Output Leakage Current Programmable Input Capacitance at Pins 2 and 3 Input Capacitance IDD ISBC IOL FIN=30MHz and all 4 clocks are at 66MHz and +/-2.0% Spread and CL=0 PD#=GND Pins 4, 6, 7 and 8 if programmed as SSCLK or REFOUT Minimum setting value PCin PCout Maximum setting value Resolution (programming steps) CIN2 Pins 4 and 8 if programmed as PD#, OE, SSON or FS Pins 4, 6, 7 and 8 If programmed as SSCLK or REFCLK -10 7.9 70 8 40 0.5 4 9.4 90 10 6 mA A A pF pF pF pF Load Capacitance CL - - 15 pF AC Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C Parameter Input Frequency Range Input Frequency Range Symbol FIN1 FIN2 Condition Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK , Xtal input REFCLK, clock input Clock Input, Pin 3 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Min 8 8 3 0.25 0.25 45 45 40 40 - Typ 50 50 50 50 4.00 2.00 1.40 1.10 0.85 0.70 0.55 Max 48 166 200 48 166 55 55 60 60 4.80 2.40 1.70 1.35 1.00 0.85 0.67 Unit MHz MHz MHz MHz MHz % % % % ns ns ns ns ns ns ns Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time DC1 DC2 DC3 DCIN tr/f1 tr/f2 tr/f3 tr/f4 tr/f5 tr/f6 tr/f7 Rev 1.8, August 10, 2007 Page 5 of 16 SL15101 Cycle-to-Cycle Jitter (SSCLK – Pins 4/6/7/8) Cycle-to-Cycle Jitter (SSCLK – Pins 4/6/7/8) Power-down Time Power-up Time (Crystal or Resonator) Power-up Time (Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Range Spread Percent Variation Modulation Frequency CCJ1 CCJ2 tPD tPU1 FIN=30MHz, all 4 clocks are at 33MHz, +/-2.0% Spread. CL=15pF FIN=30MHz, all 4 clocks are at 33MHz, +/-2.0% Spread. CL=15pF Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Center Spread, SSCLK-1/2/3/4 Down Spread, SSCLK-1/2/3/4 Variation of programmed Spread % Programmable, 31.5 kHz standard 235 185 150 3.5 290 245 350 5.0 ps ps ns ms tPU2 - 2.0 3.0 ms tOE tOD SPR-1 SPR-2 SS% FMOD +/-0.125 -5.0 -15 30 180 180 31.5 350 350 +/-2.5 -0.25 15 120 ns ns % % % kHz DC Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C Description Operating Voltage Input Low Voltage Symbol VDD VIL Condition VDD+/-10% CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS. IOH=10mA , If Pins 4, 6, 7 and 8 are programmed as SSCLK/REFCLK IOL=10mA, If Pins 4, 6, 7 and 8 are programmed as SSCLK/REFCLK VIN=VDD, Pins 4 and 8. If outputs are programmed as PD#, OE, SSON# or FS and no pull-up/down resister used VIN=GND, Pins 4 and 8. If outputs are programmed as PD#, OE, SSON# or FS and no pull-up/down resister used Min 2.25 0 Typ 2.5 - Max 2.75 0.3VDD Unit V V Input High Voltage VIH 0.7VDD - VDD V Output High Voltage VOH1 VDD-0.4 - - V Output Low Voltage VOL1 - - 0.4 V Input High Current IIH -10 - 10 A Input Low Current IIL -10 - 10 A Rev 1.8, August 10, 2007 Page 6 of 16 SL15101 Pull-up or Down Resistors RPU/D CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS FIN=30MHz and all 4 clocks are at 66MHz and +/-2.0% Spread and CL=0 PD#=GND Pins 4, 6, 7 and 8. If programmed as SSCLK or REFCLK Minimum setting value PCin PCout Maximum setting value Resolution (programming steps) CIN2 Pins 4 and 8 If programmed as PD#, OE, SSON or FS Pins 4, 6, 7 and 8. If programmed as SSCLK or REFCLK 90 160 230 k Operating Supply Current Standby Current Output Leakage Current Programmable Input Capacitance at Pins 2 and 3 IDD ISBC IOL -10 - 7.0 70 8 40 0.5 4 8.3 90 10 6 mA A A pF pF pF pF Input Capacitance Load Capacitance CL - - 15 pF AC Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +85 Deg C Parameter Input Frequency Range Input Frequency Range Symbol FIN1 FIN2 Condition Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK, Xtal input REFCLK, clock input Clock Input, Pin 3 Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Min 8 8 3 0.25 0.25 45 45 40 40 - Typ 50 50 50 50 4.80 2.60 1.80 1.40 Max 48 166 200 48 166 55 55 60 60 5.80 3.10 2.20 1.70 Unit MHz MHz MHz MHz MHz % % % % ns ns ns ns Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time DC1 DC2 DC3 DCIN tr/f1 tr/f2 tr/f3 tr/f4 Rev 1.8, August 10, 2007 Page 7 of 16 SL15101 Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Cycle-to-Cycle Jitter (SSCLK – Pins 4/6/7/8 ) Cycle-to-Cycle Jitter (SSCLK – Pins 4/6/7/8) Power-down Time Power-up Time (Crystal or Resonator) Power-up Time (Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Range Spread Percent Variation Modulation Frequency tr/f5 tr/f6 tr/f7 CCJ1 CCJ2 tPD tPU1 Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD FIN=30MHz, all 4 clocks are at 33MHz, +/-2.0% Spread. CL=15pF FIN=30MHz, all 4 clocks are at 33MHz, +/-2.0% Spread. CL=15pF Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Center Spread, SSCLK-1/2/3/4 Down Spread, SSCLK-1/2/3/4 Variation of programmed Spread % Programmable, 31.5 kHz standard 1.10 0.90 0.70 260 210 150 3.5 1.35 1.10 0.85 310 250 350 5.0 ns ns ns ps ps ns ms tPU2 - 2.0 3.0 ms tOE tOD SPR-1 SPR-2 SS% FMOD +/-0.125 -5.0 -15 30 180 180 31.5 350 350 +/-2.5 -0.25 15 120 ns ns % % % kHz DC Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C Description Operating Voltage Input Low Voltage Symbol VDD VIL Condition VDD+/-10% CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS. IOH=10mA , If Pins 4, 6, 7 and 8 are programmed as SSCLK/REFCLK IOL=10mA, If Pins 4, 6, 7 and 8 are programmed as SSCLK/REFCLK Min 2.97 0 Typ 3.3 - Max 3.63 0.3VDD Unit V V Input High Voltage VIH 0.7VDD - VDD V Output High Voltage VOH1 VDD-0.5 - - V Output Low Voltage VOL1 - - 0.5 V Rev 1.8, August 10, 2007 Page 8 of 16 SL15101 VIN=VDD, Pins 4 and 8. If outputs are programmed as PD#, OE, SSON# or FS and no pull-up/down resister used VIN=GND, Pins 4 and 8. If outputs are programmed as PD#, OE, SSON# or FS and no pull-up/down resister used CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS FIN=30MHz and all 4 clocks are at 66MHz and +/-2.0% Spread and CL=0 PD#=GND Pins 4, 6, 7 and 8. If programmed as SSCLK or REFCLK Minimum setting value PCin PCout Maximum setting value Resolution (programming steps) CIN2 Pins 4 and 8 If programmed as PD#, OE, SSON or FS Pins 4, 6, 7 and 8. If programmed as SSCLK or REFCLK Input High Current IIH -15 - 15 A Input Low Current IIL -15 - 15 A Pull-up or Down Resistors RPU/D 100 160 220 k Operating Supply Current Standby Current Output Leakage Current Programmable Input Capacitance at Pins 2 and 3 IDD ISBC IOL -10 - 8.2 80 8 40 0.5 4 9.8 100 10 6 mA A A pF pF pF pF Input Capacitance Load Capacitance CL - - 15 pF AC Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C Parameter Input Frequency Range Input Frequency Range Symbol FIN1 FIN2 Condition Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK, Xtal input REFCLK, clock input Clock Input, Pin 3 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Min 8 8 3 0.25 0.25 45 45 40 40 - Typ 50 50 50 50 4.00 Max 48 166 200 48 166 55 55 60 60 4.80 Unit MHz MHz MHz MHz MHz % % % % ns Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time DC1 DC2 DC3 DCIN tr/f1 Rev 1.8, August 10, 2007 Page 9 of 16 SL15101 Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Cycle-to-Cycle Jitter (SSCLK – Pins 4/6/7/8) Cycle-to-Cycle Jitter (SSCLK – Pins4/6/7/8) Power-down Time Power-up Time (Crystal or Resonator) Power-up Time (Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Range Spread Percent Variation Modulation Frequency tr/f2 tr/f3 tr/f4 tr/f5 tr/f6 tr/f7 CCJ1 CCJ2 tPD tPU1 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD FIN=30MHz, all 4 clocks are at 33MHz, +/-2.0% Spread. CL=15pF FIN=30MHz, all 4 clocks are at 66MHz, +/-2.0% Spread. CL=15pF Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Center Spread, SSCLK-1/2/3/4 Down Spread, SSCLK-1/2/3/4 Variation of programmed Spread % Programmable, 31.5 kHz standard 2.00 1.40 1.10 0.85 0.70 0.55 235 185 150 3.5 2.40 1.70 1.35 1.00 0.85 0.67 290 245 350 5.0 ns ns ns ns ns ns ps ps ns ms tPU2 - 2.0 3.0 ms tOE tOD SPR-1 SPR-2 SS% FMOD +/-0.125 -5.0 -20 30 180 180 31.5 350 350 +/-2.5 -0.25 20 120 ns ns % % % kHz DC Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C Description Operating Voltage Input Low Voltage Symbol VDD VIL Condition VDD+/-10% CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS. Min 2.25 0 Typ 2.5 - Max 2.75 0.3VDD Unit V V Input High Voltage VIH 0.7VDD - VDD V Rev 1.8, August 10, 2007 Page 10 of 16 SL15101 Output High Voltage VOH1 IOH=10mA , If Pins 4, 6, 7 and 8 are programmed as SSCLK/REFCLK IOL=10mA, If Pins 4, 6, 7 and 8 are programmed as SSCLK/REFCLK VIN=VDD, Pins 4 and 8. If outputs are programmed as PD#, OE, SSON# or FS and no pull-up/down resister used VIN=GND, Pins 4 and 8. If outputs are programmed as PD#, OE, SSON# or FS and no pull-up/down resister used CMOS Level, if Pins 4 and 8 programmed as PD#, OE, SSON# or FS FIN=30MHz and all 4 clocks are at 66MHz and +/-2.0% Spread and CL=0 PD#=GND Pins 4, 6, 7 and 8. If programmed as SSCLK or REFCLK Minimum setting value PCin PCout Maximum setting value Resolution (programming steps) CIN2 Pins 4 and 8 If programmed as PD#, OE, SSON or FS Pins 4, 6, 7 and 8. If programmed as SSCLK or REFCLK VDD-0.4 V Output Low Voltage VOL1 - - 0.4 V Input High Current IIH -15 - 15 A Input Low Current IIL -15 - 15 A Pull-up or Down Resistors RPU/D 90 160 230 k Operating Supply Current Standby Current Output Leakage Current Programmable Input Capacitance at Pins 2 and 3 IDD ISBC IOL -10 - 7.2 80 8 40 0.5 4 8.6 100 10 6 mA A A pF pF pF pF Input Capacitance Load Capacitance CL - - 15 pF AC Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85 Deg C Parameter Input Frequency Range Input Frequency Range Symbol FIN1 FIN2 Condition Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK Min 8 8 3 0.25 0.25 45 Typ 50 Max 48 166 200 48 166 55 Unit MHz MHz MHz MHz MHz % Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle DC1 Rev 1.8, August 10, 2007 Page 11 of 16 SL15101 Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Cycle-to-Cycle Jitter (SSCLK – Pins 4/6/7/8) Cycle-to-Cycle Jitter (SSCLK – Pins 4/6/7/8) Power-down Time Power-up Time (Crystal or Resonator) Power-up Time (Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Range Spread Percent Variation Modulation Frequency DC2 DC3 DCIN tr/f1 tr/f2 tr/f3 tr/f4 tr/f5 tr/f6 tr/f7 CCJ1 CCJ2 tPD tPU1 REFCLK, Xtal input REFCLK, clock input Clock Input, Pin 3 Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD Programmable, VDD=2.5 CL=15pF, 20 to 80% of VDD FIN=30MHz, all 4 clocks are at 33MHz, +/-2.0% Spread. CL=15pF FIN=30MHz, all 4 clocks are at 33MHz, +/-2.0% Spread. CL=15pF Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Center Spread, SSCLK-1/2/3/4 Down Spread, SSCLK-1/2/3/4 Variation of programmed Spread % Programmable, 31.5 kHz standard 45 40 40 50 50 50 4.80 2.60 1.80 1.40 1.10 0.90 0.70 260 210 180 3.5 55 60 60 5.80 3.10 2.20 1.70 1.35 1.10 0.85 310 250 350 5.0 % % % ns ns ns ns ns ns ns ps ps ns ms tPU2 - 2.0 3.0 ms tOE tOD SPR-1 SPR-2 SS% FMOD +/-0.125 -5.0 -20 30 180 180 31.5 350 350 +/-2.5 -0.25 20 120 ns ns % % % kHz Rev 1.8, August 10, 2007 Page 12 of 16 SL15101 External Components & Design Considerations Typical Application Schematic VDD 0.1 F XIN(3) 27MHz VDD(1) SSCLK1(6) SSCLK2(7) 66 MHz, +/-1.5% Spread 66 MHz, +/-1.5% Spread 33 MHz, +/-1.5% Spread 27 MHz, No Spread XOUT(2) SSCLK3(4) REFCLK(8) SL15101 VSS(5) Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1 F must be used between VDD and VSS on the pins 1 and 5. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs (SSCLK or REFCLK pins) and the load is over 1 ½ inch. The nominal impedance of the SSCLK output is about 30 . Use 20 resistor in series with the output to terminate 50 trace impedance and place 20 resistor as close to the SSCLK output as possible. Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals. To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and PCout must be programmed to match the crystal load requirement. These values are given by the formula below: PCin(pF) =PCout(pF)= [(CL(pF) – Cp(pF)/2)] x 2 Where CL is crystal load capacitor as given by the crystal datasheet and Cp(pF) is the compensation factor for the total parasitic capacitance at XIN or XOUT pin including PCB related parasitic capacitance. As an example; if a crystal with CL=18pF is used and Cp=4pF, by using the above formula, PCin=PCout=[(18-(4/2)] x 2 = 32pF. Programming PCin and PCout to 32pF assures that this crystal sees an equivalent load of 18pF and no other external crystal load capacitor is needed. Deviating from the crystal load specification could cause an increase in frequency accuracy in ppm. Refer to the Table 5 for the recommended crystal specifications. Rev 1.8, August 10, 2007 Page 13 of 16 SL15101 Recommended External Crystal Specifications Parameter FNOM CL R1,1 R1,2 R1,3 DL1,1 DL1,2 Co1 Co2 Description Nominal Crystal Frequency Range Nominal Crystal Load Equivalent Series Resistance Equivalent Series Resistance Equivalent Series Resistance Crystal Drive Level Crystal Drive Level Shunt Capacitance Shunt Capacitance Min 8 6 20 12.5 10 Typ 12 40 25 20 4 5 Max 48 18 100 60 50 200 150 5.4 7.2 Unit MHz pF Ohm Ohm Ohm µW µW pF pF Comments Fundamental Mode – AT Cut Load for +/-0 ppm Fo resonance value F-Range: 8.0 to 12.999 MHz F-Range: 13.0 to 19.999 MHz F-Range: 20.0 to 48.000 MHz F-Range: 8.0 to 19.999 MHz F-Range: 20.0 to 48.000 MHz SMD Xtals Through Hole (Leaded) Xtals Table 5. Recommended Crystal Specifications Rev 1.8, August 10, 2007 Page 14 of 16 SL15101 Package Outline and Package Dimensions 8-Pin TSSOP Package (173 Mil) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JA JA JC Condition Still air 1m/s air flow 3m/s air flow Independent of air flow Min - Typ 110 100 80 35 Max - Unit °C/W °C/W °C/W °C/W Rev 1.8, August 10, 2007 Page 15 of 16 SL15101 Ordering Information [1] Ordering Number [2] Marking SL15101ZC-XXX SL15101ZC-XXX SL15101ZI-XXX SL15101ZI-XXX Shipping Package Tube Tape and Reel Tube Tape and Reel Package 8-pin TSSOP 8-pin TSSOP 8-pin TSSOP 8-pin TSSOP Temperature 0 to 85°C 0 to 85°C -40 to 85°C -40 to 85°C SL15101ZC-XXX SL15101ZCT-XXX SL15101ZI-XXX SL15101ZIT-XXX Notes: 1. All SLI products are RoHS compliant. 2. “XXX” is “Dash” number and will be assigned by SLI for final programmed samples or production units based on the each customer programming requirements. While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.8, August 10, 2007 Page 16 of 16