SL15316ZC-XXXT

SL15316 Programmable Spread Spectrum Clock Generator (SSCG) Key Features • Low power dissipation - 9.0mA-typ at 66MHz and VDD=3.3V - 8.0mA-typ at 66MHz and VDD=2.5V Wide 3.3V to 2.5V power supply range Programmable 5 outputs from 3 to 200MHz VDDO power suplly for 3 outputs from 3.3 to 2.5V or 1.8V Low Jitter Programmable Center or Down Spread Modulation from 0.25 to 5.0% 8 to 48 MHz external crystal range 3 to 166 MHz external clock range Integrated internal voltage regulator Programmable PD#/OE/SSON#/FS functions Programmable CL at XIN and XOUT pins Programmable output rise and fall times Programmable modulation frequency from 25 to 120 kHz Printers, MFPs Digital Copiers NBPCs and LCD Monitors Routers, Servers and Switches HDTV and DVD-R/W Description The SL15316 a programmable Ultra low Power Spread Spectrum Clock Generator (SSCG) used for reducing Electromagnetic Interference (EMI). The product is designed using SpectraLinear proprietary programmable phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the input clock. The modulated clock can significantly reduce the measured EMI levels, and leading to the compliance with regulatory agency requirements. Up to 5 output clock frequencies, Spread %, output rise and fall times, crystal load, modulation frequency and PD#/OE/SSON#/FS functions can be programmed to meet the needs of wide range of applications. The SL15316 operates from 2.5V to 3.3V power supply voltage range. Separate VDDO power supply is provided for three (3) clock outputs which can be any value from 3.3V to 2.5V or 1.8V where VDDO≤VDD. The product is offered in 16-pin TSSOP package with commercial and industrial grades. • • • • • • • • • • • • Applications • • • • • Benefits • • • • • Peak EMI reduction of 6 to 16 dB Fast time-to-market Cost Reduction Reduction of PCB layers Eleminates the need for higher order crystals (Xtals) and crystal oscillators (XOs) Block Diagram Rev 1.0, August 7, 2008 Page 1 of 12 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL15316 Pin Configuration 16-Pin TSSOP Pin Description Pin Number 1 2 3 Pin Name VDD VDD XOUT Pin Type Power Power Output Pin Description Positive power supply. From 3.3V to 2.5V, +/-10%. Positive power supply. From 3.3V to 2.5V, +/-10%. Crystal or ceramic resonator output pin. Leave this pin unconnected (floating) if external clock is used at Pin-4. Programmable pin capacitance from 8 to 40pF. 4 XIN/CLKIN Input Crystal, ceramic resonator or external clock input pin. Programmable pin capacitance from 8 to 40pF. 5 6 7 8 9 10 VSS N/C SSCLK1 or REFCLK1 or PD#/OE/SSON#/FS VSS VSS VSSO Power N/C Output Power Power Power Power supply ground. No Connect. Leave this pin unconnected (floating). This pin can be programmed as SSCLK1 or REFCLK1 or one of PD#/OE/SSON#/FS functions. Power supply ground. Power supply ground. Power supply ground for VDDO. This pin is internally connected to VSS. Page 2 of 12 Rev 1.0, August 7, 2008 SL15316 11 12 13 14 15 16 SSCLK2 or REFCLK2 or PD#/OE/SSON#/FS SSCLK3 or REFCLK3 SSCLK4 or REFCLK4 VSS SSCLK5 or REFCLK5 or PD#/OE/SSON#/FS VDDO I/O Output Output Power I/O Power This pin can be programmed as SSCLK2 or REFCLK2. This pin can be programmed as SSCLK3 or REFCLK3. This pin can be programmed as SSCLK4 or REFCLK4. Power supply ground. This pin can be programmed as SSCLK5 or REFCLK5 or one of PD#/OE/SSON#/FS functions. Positive power supply for pins 12, 13 and 15. can be 3.3V to 2.5V or 1.8V +/-10% where VDDO≤VDD. Available REFCLK Frequencies and Dividers All REFCLK outputs are programmed by using buffered crystal or clock input and output dividers. These outputs can not be programmed for spread spectrum clock function. The table below gives the available output dividers for REFCLK outputs: Pin Number 7 11 12 13 15 Pin Name REFCLK1 REFCLK2 REFCLK3 REFCLK4 REFCLK5 Description Crystal or clock input reference frequency divide by 1 to 32 Crystal or clock input reference frequency divide by 1 to 32 Crystal or clock input reference frequency (no divider) Crystal or clock input reference frequency divide by 2 to 32 Crystal or clock input reference frequency divide by 2N where N = 2 to 16. Rev 1.0, August 7, 2008 Page 3 of 12 SL15316 General Description The primary source of EMI from digital circuits is the system clock and all the other synchronous clocks and control signals derived from the system clock. The well know techniques of filtering (suppression) and shielding (containment), while effective, can cost money, board space and longer development time. A more effective and efficient technique to reduce EMI is Spread Spectrum Clock Generator (SSCG) technique. Instead of using constant clock frequency, the SSCG technique modulates (spreads) the system clock with a much smaller frequency, to reduce EMI emissions at its source: The System Clock. The SL15316 is designed using SpectraLinear proprietary phase-locked loop (PLL) and Spread Spectrum Technologies (SST) to synthesize and modulate (spread) the system clock such that the energy is spread out over a wider bandwidth. This reduces the peak value of the radiated emissions at the fundamental and the harmonics. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time-tomarket without degrading system performance. The SL15316 operates from 3.3V to 2.5V power supply range. Separate VDDO power supply is provided for thre (3) output clock drivers. The supply voltage on these pins could be 3.3V to 25V or 1.8V as long as VDDO≤VDD condition is met. The SL15316 is available in 16-pin TSSOP package with Commercial Temperature range of 0 to 70°C and Industrial Temperature range of –40 to 85°C. Input Frequency Range The input frequency range is from 8.0 to 48.0 MHz for crystals and ceramic resonators. If an external clock is used, the input frequency range is from 3 to 166 MHz. Output Frequency Range and Outputs Up to five (5) outputs can be programmed as SSCLK or REFCLK. SSCLK output can be synthesized to any value from 3 to 200 MHz with spread using input frequency. The spread at SSCLK pins can be stopped by SSON# input control pin, If SSON# pin is HIGH (VDD), the frequency at this pin is the synthesized to the nominal value of the input frequency and there is no spread. REFOUT is the buffered output of the oscillator and is the same frequency as the input frequency without spread. However, REFOUT value can also be divided by using the output divider. The SSCLK is the programmed and synthesized value of the input clock. The remaining SSCLKs could be the same value providing fanout of up to 5 or the frequency can be divided from also 2 to 32. In this case, the spread % value is the same as the original programmed spread % value. By using only first order crystals, SL15316 can synthesize output frequency up to 200 MHz, eliminating the need for higher order Crystals (Xtals) and Crystal Oscillators (XOs). This reduces the cost while improving the system clock accuracy, performance and reliability. Rev 1.0, August 7, 2008 Programmable CL (Crystal Load) The SL15316 provides programmable on-chip capacitors at XIN/CLKIN (Pin-3) and XOUT (Pin-2). The resolution of this programmable capacitor is 6-bits with LSB value of 0.5pF. When all bits are off the pin capacitance is CXIN=CXOUT =7.0pF (minimum value). When all bits are on the pin capacitance is CXIN=CXOUT=38pF (maximum value). The values of CXIN and CXOUT based on the CL (Crystal Load Capacitor) can be calculated as: CXIN=CXOUT=2CL-CPCB. Refer to the Page-10 for additional information on crystal load (CL). In addition, if an external clock is used, the capacitance at Pin-4 (XIN/CLKIN) can programmed to control the edge rate of this input clock, providing additional EMI control. Programmable Modulation Frequency The Spread Spectrum Clock (SSC) modulation default value is 31.5 kHz. The higher values of 60, 90 and 120 kHz can also be programmed. Less than 25 kHz modulation frequency is not recommended to stay out of the range audio frequency bandwidth since this frequency could be detected as a noise by the audio receivers within the vicinity. Programmable Spread Percent (%) The spread percent (%) value is programmable from +/0.125% to +/-2.5% (center spread) or -0.25% to -5.0% (down spread) for all SSCLK frequencies. It is possible to program smaller or larger non-standard values of spread percent. Contact SLI if these non-standard spread percent values are required in the application. SSON# or Function Select (FS) The SL15316 Pins 7, 12 and 15 could be programmed as either SSON# to enable or disable the programmed spread percent value or as Frequency Select (FS). If SSON# is used, when this pin is pulled high (VDD), the spread is stopped and the frequency is the nominal value without spread. If low (GND), the frequency is the nominal value with the spread. If FS function is used, the output pins could be programmed for different set of frequencies or spread % as selected by FS. SSCLK value can be any frequency from 3 to 200MHz, but the spread % is the same percent value. REFOUT is the same frequency as the input reference clock or divide by from 2 to 32 without spread. The SL15316 allows a fan-out of up to 5 clocks, meaning that Pins 7, 11, 12, 13 and 15 can be programmed to the same frequencies with or without spread. Power Down (PD#) or Output Enable (OE) The SL15316 Pins 7, 11, 12, 13 and 15 could also be programmed as either PD# or OE. PD# powers down the entire chip whereas OE only disables the output buffers to Hi-Z. Spread Spectrum Clock Modulation Frequency The modulation frequency of spread spectrum clock can be programmed from 25 to 120kHz. Page 4 of 12 SL15316 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) ESD Rating (Charge Device Model) ESD Rating (Machine Model) JEDEC C22-A114D JEDEC C22-C101C JEDEC C22-A115D In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min -0.5 -0.5 0 -40 -65 -4,000 -1,500 -200 Max 4.2 VDD+0.5 70 85 150 125 260 4,000 1,500 200 Unit V V °C °C °C °C °C V V V DC Electrical Characteristics (C and I-Grades) Unless otherwise stated VDD= 3.3V+/- 10% and CL=15pF Description Operating Voltage Operating Voltage Operating Voltage Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Symbol VDD VDDO-1 VDDO-2 VIL VIH VOH1 VOL1 IIH Condition VDD+/-10% VDDO≤VDD VDDO≤VDD CMOS Level, Pins programmed as PD#, OE, SSON# or FS CMOS Level, Pins programmed as PD#, OE, SSON# or FS IOH=8mA , Pins programmed as SSCLK or REFCLK IOL=8mA, Pins programmed as SSCLK or REFCLK VIN=VDD, Pins programmed as PD#, OE, SSON# or FS and no pull-up/down resister used VIN=GND, Pins programmed as PD#, OE, SSON# or FS and no pull-up/down resister used Pins programmed as PD#, OE, SSON# or FS Min 2.25 2.25 1.62 0 0.7VDD VDD-0.5 -10 Typ Max 3.63 Unit V V V V V V V μA 1.8 - VDD 1.96 0.3VDD VDD 0.5 10 Input High Current Input Low Current IIL RPU/D -10 100 150 10 250 μA kΩ Pull-up or Down Resistors Rev 1.0, August 7, 2008 Page 5 of 12 SL15316 Operating Supply Current Standby Current IDD ISBC FIN=25MHz Clock, all 5 clocks are at 66MHz, +/-1.0% Spread. CL=0, VDD=VDDO=3.3V If programmed PD#=GND For Pins programmed as SSCLK or REFOUT and if PD# or OE is programmed. PD#=0 or OE=1 Minimum programming value Maximum programming value Pins programmed as PD#, OE, SSON or FS For all pins programmed as SSCLK or REFCLK 9.0 70 TBD 100 mA μA Output Leakage Current IOL -10 - 10 μA Programmable Input Capacitance at Pins 3 and 4 Input Capacitance Load Capacitance PCin PCout CIN2 CL - 7 38 4 - 6 15 pF pF pF pF AC Electrical Characteristics (C and I-Grades) Unless otherwise stated VDD= 3.3V+/- 10% and CL=15pF Parameter Input Frequency Range Input Frequency Range Symbol FIN1 FIN2 Condition Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK Clock Input, Pin 3 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Min 8 3 3 0.25 0.25 45 45 40 - Typ 50 50 50 3.8 1.9 1.4 1.0 0.85 0.65 Max 48 166 200 48 166 55 55 60 - Unit MHz MHz MHz MHz MHz % % % ns ns ns ns ns ns Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time DC1 DC2 DCIN tr/f1 tr/f2 tr/f3 tr/f4 tr/f5 tr/f6 Rev 1.0, August 7, 2008 Page 6 of 12 SL15316 Output Rise/Fall Time Cycle-to-Cycle Jitter tr/f7 CCJ1 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD FIN=25MHz Clock, all 5 clocks are at 66MHz, +/-1.0% Spread. CL=10pF, VDD=VDDO1/2=3.3V FIN=25MHz Clock, all 5 clocks are at 166MHz, +/-1.0% Spread. CL=10pF, VDD=VDDO1/2=3.3V Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Center Spread, all programmed SSCLKs Down Spread, all programmed SSCLKs Variation of programmed Spread % Programmable, 31.5 kHz standard Time for VDD reaching minimum specified value and monolithic power supply ramp 0.50 TBD TBD ns ps Cycle-to-Cycle Jitter CCJ2 - TBD TBD ps Power-down Time Power-up Time (Crystal or Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Range Spread Percent Variation Modulation Frequency Power Supply Ramp Time tPD tPU - 150 3.5 350 5.0 ns ms tOE tOD SPR-1 SPR-2 ΔSS% FMOD tPSR +/-0.125 -5.0 -15 25 - 180 180 31.5 - 350 350 +/-2.5 -0.25 15 120 12 ns ns % % % kHz ms DC Electrical Characteristics (C and I-Grades) Unless otherwise stated VDD= 2.5V+/- 10% and CL=15pF Description Operating Voltage Operating Voltage Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Symbol VDD VDDO VIL VIH VOH1 VOL1 IIH Condition VDD+/-10% VDD0≤VDD CMOS Level, Pins programmed as PD#, OE, SSON# or FS CMOS Level, Pins programmed as PD#, OE, SSON# or FS IOH=8mA , Pins programmed as SSCLK or REFCLK IOL=8mA, Pins programmed as SSCLK or REFCLK VIN=VDD, Pins programmed as PD#, OE, SSON# or FS and no pull-up/down resister used Min 2.25 1.62 0 0.7VDD VDD-0.5 -15 Typ 2.5 - Max 2.75 VDD 0.3VDD VDD 0.5 15 Unit V V V V V V μA Input High Current Rev 1.0, August 7, 2008 Page 7 of 12 SL15316 Input Low Current IIL RPU/D IDD ISBC VIN=GND, Pins programmed as PD#, OE, SSON# or FS and no pull-up/down resister used Pins programmed as PD#, OE, SSON# or FS FIN=25MHz Clock, all 5 clocks are at 66MHz, +/-1.0% Spread, CL=0, VDD=VDDO1/2=3.3V If programmed PD#=GND For Pins programmed as SSCLK or REFOUT and if PD# or OE is programmed. PD#=0 or OE=1 Minimum programming value Maximum programming value Pins programmed as PD#, OE, SSON or FS For all pins programmed as SSCLK or REFCLK -15 90 150 8.0 70 15 275 TBD 120 μA kΩ mA μA Pull-up or Down Resistors Operating Supply Current Standby Current Output Leakage Current IOL -15 - 15 μA Programmable Input Capacitance at Pins 3 and 4 Input Capacitance Load Capacitance PCin PCout CIN2 CL - 7 38 4 - 6 15 pF pF pF pF AC Electrical Characteristics (C and I-Grades) Unless otherwise stated VDD= 2.5V+/- 10% and CL=15pF Parameter Input Frequency Range Input Frequency Range Symbol FIN1 FIN2 Condition Crystal or Ceramic Resonator External Clock SSCLK REFCLK, crystal or resonator input REFCLK, clock input SSCLK REFCLK Clock Input, Pin 3 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, Min 8 3 3 0.25 0.25 45 45 40 - Typ 50 50 50 3.8 1.9 1.4 1.0 0.85 Max 48 166 200 48 166 55 55 60 - Unit MHz MHz MHz MHz MHz % % % ns ns ns ns ns Output Frequency Range FOUT1 Output Frequency Range FOUT2 Output Frequency Range FOUT3 Output Duty Cycle Output Duty Cycle Input Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time DC1 DC2 DCIN tr/f1 tr/f2 tr/f3 tr/f4 tr/f5 Rev 1.0, August 7, 2008 Page 8 of 12 SL15316 CL=15pF, 20 to 80% of VDD Output Rise/Fall Time Output Rise/Fall Time Cycle-to-Cycle Jitter tr/f6 tr/f7 CCJ1 Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD Programmable, VDD=3.3V, CL=15pF, 20 to 80% of VDD FIN=25MHz Clock, all 5 clocks are at 66MHz, +/-1.0% Spread. CL=10pF, VDD=VDDO1/2=3.3V FIN=25MHz Clock, all 5 clocks are at 166MHz, +/-1.0% Spread. CL=10pF, VDD=VDDO1/2=3.3V Time from PD# falling edge to Hi-Z at outputs (Asynchronous) Time from PD# rising edge to valid frequency at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Time from OE falling edge to Hi-Z at outputs (Asynchronous) Center Spread, all programmed SSCLKs Down Spread, all programmed SSCLKs Variation of programmed Spread % Programmable, 31.5 kHz standard Time for VDD reaching minimum specified value and monolithic power supply ramp 0.65 0.50 TBD TBD ns ns ps Cycle-to-Cycle Jitter CCJ2 - TBD TBD ps Power-down Time Power-up Time (Crystal or Clock) Output Enable Time Output Disable Time Spread Percent Range Spread Percent Range Spread Percent Variation Modulation Frequency Power Supply Ramp Time tPD tPU - 150 3.5 350 5.0 ns ms tOE tOD SPR-1 SPR-2 ΔSS% FMOD tPSR +/-0.125 -5.0 -20 25 - 180 180 31.5 - 450 450 +/-2.5 -0.25 20 120 12 ns ns % % % kHz ms Rev 1.0, August 7, 2008 Page 9 of 12 SL15316 External Components & Design Considerations Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1μF and 0.01μF must be used between VDD, VDDO1/2 and VSS pins. Place the capacitor on the component side of the PCB as close to the VDD and VDDO1/2 pins as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor and the power supply pins. Series Termination Resistor: A series termination resistor is recommended if the distance between the outputs (SSCLK or REFCLK pins) and the load is over 1 ½ inch. The nominal impedance of the SSCLK output is about 30 Ω. Use 20 Ω resistor in series with the output to terminate 50Ω trace impedance and place 20 Ω resistor as close to the SSCLK or REFCLK outputs as possible. Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals. To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and PCout must be programmed to match the crystal load requirement. These values are given by the formula below: PCin(pF) =PCout(pF)= [(CL(pF) – Cp(pF)/2)] x 2 Where CL is crystal load capacitor as given by the crystal datasheet and Cp(pF) is the compensation factor for the total parasitic capacitance at XIN or XOUT pin including PCB related parasitic capacitance. As an example; if a crystal with CL=18pF is used and Cp=4pF, by using the above formula, PCin=PCout=[(18-(4/2)] x 2 = 32pF. Programming PCin and PCout to 32pF assures that this crystal sees an equivalent load of 18pF and no other external crystal load capacitor is needed. Deviating from the crystal load specification could cause an increase in frequency accuracy in ppm. Refer to the Table 5 for the recommended crystal specifications. Parameter FNOM CL R1,1 R1,2 R1,3 DL1,1 DL1,2 Co1 Co2 Description Nominal Crystal Frequency Range Nominal Crystal Load Equivalent Series Resistance Equivalent Series Resistance Equivalent Series Resistance Crystal Drive Level Crystal Drive Level Shunt Capacitance Shunt Capacitance Min 8 6 20 12.5 10 - Typ 12 40 25 20 4 5 Max 48 18 100 60 50 200 150 5.4 7.2 Unit MHz pF Ohm Ohm Ohm µW µW pF pF Comments Fundamental Mode – AT Cut Load for +/-0 ppm Fo resonance value F-Range: 8.0 to 12.999 MHz F-Range: 13.0 to 19.999 MHz F-Range: 20.0 to 48.000 MHz F-Range: 8.0 to 19.999 MHz F-Range: 20.0 to 48.000 MHz SMD Xtals Through Hole (Leaded) Xtals Table 5. Recommended Crystal Specifications Rev 1.0, August 7, 2008 Page 10 of 12 SL15316 Package Outline and Package Dimensions 16-Pin TSSOP Package (173 Mil) 16 9 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) Dimensions are in milimeters (inches) Top line: (MIN) and Bottom line: (Max) Pin-1 ID 1 8 4.900(0.193) 5.100(0.200) 1.200(0.047) MAX 0.250(0.010) BSC Gauge Plane 0.800(0.031) 1.050(0.041) 0.190(0.007) 0.300(0.012) 0.050(0.002) 0.150(0.006) 0.090(0.003) 0.200(0.008) 0.076(0.003) 0.650(0.025) BSC Seating Plane 0 to 8° 0.500(0.020) 0.750(0.030) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol θ JA θ JA θ JA θ JC Still air 1m/s air flow 3m/s air flow Independent of air flow Condition Min Typ 110 100 80 35 Max Unit °C/W °C/W °C/W °C/W Rev 1.0, August 7, 2008 Page 11 of 12 SL15316 Ordering Information [1] Ordering Number [2] Marking SL15316ZC-XXX SL15316ZC-XXX SL15316ZI-XXX SL15316ZI-XXX Shipping Package Tube Tape and Reel Tube Tape and Reel Package 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP Temperature 0 to 70°C 0 to 70°C -40 to 85°C -40 to 85°C SL15316ZC-XXX SL15316ZC-XXXT SL15316ZI-XXX SL15316ZI-XXXT Notes: 1. All SLI products are RoHS compliant. 2. “XXX” is “Dash” number and will be assigned by SLI for final programmed samples or production units based on the each customer programming requirements. While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.0, August 7, 2008 Page 12 of 12