SL23EP08SC-5HT

Preliminary SL23EP08 Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features 10 to 220 MHz operating frequency range Low output clock skew: 70ps-typ Low output clock Jitter: 50 ps-typ - 50 ps-typ at 166MHz, CL=15pF and VDD=3.3V - 75 ps-typ at 166MHz, CL=15pF and VDD=2.5V Low part-to-part output skew: 150 ps-typ 3.3V to 2.5V power supply range Low power dissipation: - 22 mA-typ at 66MHz and VDD=3.3V - 20 mA-typ at 66MHz and VDD=2.5V One input drives 8 outputs Multiple configurations and drive options Select mode to bypass PLL or tri-state outputs SpreadThru™ PLL that allows use of SSCG Available in 16-pin SOIC and TSSOP packages Available in Commercial and Industrial grades Description The SL23EP08 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to eight (8) clock outputs from one (1) reference input clock, for high speed clock distribution applications. The product has an on-chip PLL and a feedback pin (FBK) which can be used to obtain feedback from any one of the output clocks. The SL23EP08 has two (2) clock driver banks each with four (4) clock outputs. These outputs are controlled by two (2) select input pins S1 and S2. When only four (4) outputs are needed, bank-B output clock buffers can be tri-stated to reduce power dissipation and jitter. The select inputs can also be used to tri-state both banks A and B or drive them directly from the input bypassing the PLL and making the product behave like a Non-Zero Delay Buffer (NZDB). The SL23EP08 offers various X/2,1X, 2X and 4x frequency options at the output clocks. Refer to the “Product Configuration Table” for the details. The SL23EP08-1H, -2H and 5H versions operates up to 220 MHz and SL23EP08-1, -2, -3 and -4 versions operate up to 133 MHz with CL=15pF output load. Applications Printers, MFPs and Digital Copiers PCs and Work Stations Routers, Switchers and Servers Datacom and Telecom High-Speed Digital Embeded Systems Benefits Up to eight (8) distribution of input clock Standard and High-Dirive levels to control impedance level, frequency range and EMI Low skew, jitter and power dissipation Block Diagram /2 (Divider for -3 and -4) Low Power and Low Jitter CLKIN /2 (Divider for -5H only) PLL MUX FBK CLKA1 CLKA2 CLKA3 S2 Input Selection Decoding Logic S1 /2 (Divider for -2, -2H and -3) CLKA4 CLKB1 CLKB2 CLKB3 2 2 CLKB4 VDD GND Rev 1.4, May 28, 2007 Page 1 of 18 2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com SL23EP08 Pin Configuration 16-Pin SOIC/TSSOP Pin Description Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name CLKIN CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 S1 CLKB3 CLKB4 GND VDD CLKA3 CLKA4 FBK Pin Type Input Output Output Power Power Output Output Input Input Output Output Power Power Output Output Output Pin Description Reference Frequency Clock Input. 5V tolerant input. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). 3.3V to 2.5V Power Supply. Power Ground. Buffered Clock Output, Bank B. Weak pull-down (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Select Input, select pin S2. Weak pull-up (250k ). Select Input, select pin S1. Weak pull-up (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Buffered Clock Output, Bank B. Weak pull-down (250k ). Power Ground. 3.3V to 2.5V Power Supply. Buffered Clock Output, Bank A. Weak pull-down (250k ). Buffered Clock Output, Bank A. Weak pull-down (250k ). PLL Feedback input. Rev 1.4, May 28, 2007 Page 2 of 18 SL23EP08 General Description The SL23EP08 is a low skew, low jitter Zero Delay Buffer with very low operating current. The product includes an on-chip high performance PLL that locks into the input reference clock and produces eight (8) output clock drivers tracking the input reference clock for systems requiring clock distribution. in addition to FBK pin used for internal PLL feedback, there are two (2) banks with four (4) outputs in each bank, bringing the number of total available output clocks to eight (8). PLL Bypass Mode If the S2=1 and S2=0 pins, the on-chip PLL is shutdown and bypassed, and all the eight (8) output clocks of bank A and bank B are driven directly from the reference input clock. In this operation mode SL23EP08 works like a non-ZDB product. High and Low-Drive Product Options The SL23EP08 is offered with high drive “-1H, -2H and 5H” and standard drive “-1, -2, -3 and -4” options. These drive options enable the users to control load levels, frequency range and EMI control. Refer to the AC electrical tables for the details. SL23EP08-5H is offered only with high drive option. SL23EP08-3 and -4 are offered only with standard drive option. Input and output Frequency Range The input and output frequency range is the same for SL23EP08-1 and -1H versions. For SL23EP08-2, -2H 3, -4 and -5H versions, the output frequency is 1/2x, 1x, 2x, or 4x of the CLKIN as given in the “Available SL23EP08 Configurations” Table 3. But, the frequency range depends on VDD and drive levels as given in the “Electrical Specifications” Tables. If the input clock frequency is DC (from GND to VDD), this is detected by an input frequency detection circuitry and all eight (8) clock outputs are forced to HiZ. The PLL is shutdown to save power. In this shutdown state, the product draws less than 10 A supply current. Skew and Zero Delay All outputs should drive the similar load to achieve output-to-output skew and input-to-output delay specifications given in the AC electrical tables. However, Zero delay between input and outputs can be adjusted by changing the loading of FBK pin relative to the banks A and B clocks since FBK is the feedback to the PLL. Power Supply Range (VDD) SpreadThru™ Feature If a Spread Spectrum Clock (SSC) were to be used as an input clock, the SL23EP08 is designed to pass the modulated Spread Spectrum Clock (SSC) signal from its reference input to the output clocks. The same spread characteristics at the input are passed through the PLL and drivers without any degradation in spread percent (%), spread profile and modulation frequency. The SL23EP08 is designed to operate with from 3.3V to 2.5V VDD power supply range. An internal on-chip voltage regulator is used to provide PLL constant power supply of 1.8V, leading to a consistent and stable PLL electrical performance in terms of skew, jitter and power dissipation. The SL2308 I/O is powered by using VDD. Contact SLI for 1.8V power supply version ZDB called SL23EPL08. Select Input Control The SL23EP08 provides two (2) input select control pins called S1 and S2. This feature enables users to selects various states of output clock banks-A and bank-B, output source and PLL shutdown features as shown in the Table 2. The S1 (Pin-9) and S2 (Pin-8) inputs include 250 k weak pull-down resistors to GND. Rev 1.4, May 28, 2007 Page 3 of 18 SL23EP08 Figure 1. CLKIN Input to CLKA and CLKB Delay S2 0 0 1 1 S1 0 1 0 1 Clock A1-A4 Tri-state Driven Driven Driven Clock B1-B4 Tri-state Tri-state Driven Driven Output Source PLL PLL Reference(CLKIN) PLL PLL Shutdown and Bypass Yes No Yes No Table 2. Select Input Decoding Device SL23EP08-1 and 1H SL23EP08-2 and -2H SL23EP08-2 and -2H SL23EP08-3 SL23EP08-3 [1] [1] [1] [1] Feedback From Bank-A or Bank-B Bank-A Bank-B Bank-A Bank-B Bank-A or Bank-B Bank-A or Bank-B Bank-A Frequency Reference Reference 2x Reference 2xReference 4xReference 2x Reference Reference/2 Bank-B Frequency Reference Reference/2 Reference Reference [2] 2xReference 2x Reference Reference/2 SL23EP08-4 SL23EP08-5H Table 3. Available SL23EP08 Configurations Notes: 1. Outputs are inverted on SL23EP08-2, -2H and -3 in PLL bypass mode when S2=1 and S1=0. Use SL23EP08-1 if non-inverting outputs are required. 2. Output phase is random (0° or 180° with respect to input clock). Use SL23EP08-2 if phase integrity is required. Rev 1.4, May 28, 2007 Page 4 of 18 SL23EP08 Absolute Maximum Ratings Description Supply voltage, VDD All Inputs and Outputs Ambient Operating Temperature Ambient Operating Temperature Storage Temperature Junction Temperature Soldering Temperature ESD Rating (Human Body Model) MIL-STD-883, Method 3015 In operation, C-Grade In operation, I-Grade No power is applied In operation, power is applied Condition Min -0.5 -0.5 0 -40 -65 2000 Max 4.6 VDD+0.5 70 85 150 125 260 - Unit V V °C °C °C °C °C V Operating Conditions (C-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Operating Voltage Operating Temperature Input Capacitance Symbol VDD TA VIH Condition VDD+/-10% Ambient Temperature Pins 1, 8, 9 and 16 Min 2.97 0 - Typ 3.3 5 Max 3.63 70 7 Unit V °C pF Rev 1.4, May 28, 2007 Page 5 of 18 SL23EP08 DC Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Symbol VINL VINH IINL IINH Condition CLKIN, S2 and S1 pins CLKIN, S2 and S1 pins 0 < VIN < 0.8V CLKIN, S2 and S1 inputs VIN = 2.4 to VDD CLKIN, S2 and S1 inputs IOL = 8 mA (standard drive) Min – 2.0 – – – – 2.4 2.4 – – – – – 175 Typ – – 25 – – – – – 8 16 22 28 34 250 Max 0.8 VDD+0.3 50 50 0.4 0.4 – – 12 20 28 36 44 325 Unit V V µA µA V V V V µA mA Output LOW Voltage VOL IOL = 12 mA (high drive) IOH = –8 mA (standard drive) Output HIGH Voltage Power Down Supply Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Pull-up and Pull-down Resistors VOH IOH = –12 mA (high drive) IIDDPD IDD1 IDD2 IDD3 IDD4 RPUD Measured at CLKIN= GND to VDD or input is floating All Outputs CL=0, 33.3 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 66.6 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 100 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 133.3 MHz CLKIN S2=S1=1 (high), all versions Pins-1/2/3/7/8/9/10/11/14/15 250k -typ mA mA mA k Switching Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Symbol FOUT1 FOUT2 Condition CL=15pf, -1H and -2H CL=22pf, -1H and -2H CL=30pf, -1H and -2H CL=15pf, -1, -2 and -4 CL=22pf, -1, -2 and -4 CL=30pf, -1, -2 and -4 Measured at VDD/2, all versions CL=30pF, Fout=66 MHz, all versions Measured at VDD/2 Min 10 10 10 10 10 10 30 40 Typ 50 50 Max 220 200 135 200 135 100 70 60 Unit MHz MHz MHz MHz MHz MHz % % Output Frequency Range FOUT3 FOUT4 FOUT5 FOUT6 Input Duty Cycle Output Duty Cycle DC1 DC2 Rev 1.4, May 28, 2007 Page 6 of 18 SL23EP08 Switching Electrical Characteristics (C-Grade-Cont.) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Output Duty Cycle Output Duty Cycle Output Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output-to-Output Skew on Same Bank Output-to-Output Skew on Same Bank Output-to-Output Skew Between Bank A and B Output-to-Output Skew Between Bank A and B Device-to-Device Skew DC3 DC4 DC5 tr/f1 tr/f2 tr/f3 tr/f4 SKW2 SKW2 SKW3 SKW4 SKW5 CL=15pF, Fout=66 MHz, all versions Measured at VDD/2 CL=15pF, Fout=133 MHz, all versions Measured at VDD/2 CL=15pF, Fout=166 MHz, all versions Measured at VDD/2 CL=30pF, -1, -2 and -4 versions CL=15pF, -1, -2 and -4 versions CL=30pF, -1H and -2H and versions CL=15pF, -1H and -2H and versions -1 and -2, measured from 0.8V to 2.0V, and outputs are equally loaded -1H and -2H and -4, measured at VDD/2 and outputs are equally loaded -1, -1H, 2H and -4, measured at VDD/2 and outputs are equally loaded -2, measured at VDD/2 and outputs are equally loaded All versions, measured at VDD/2 and outputs are equally loaded All versions, CLKIN to FBK rising edge, measured at VDD/2 and outputs are equally loaded and S2=S1=1 Fout=66 MHz and CL=15pF Cycle-to-Cycle Jitter (-1 and -2 Versions) CCJ1 Fout=66MHz and CL=30PF Fout=166MHz and CL=15pF Cycle-to-Cycle Jitter (-1H, -2H and -4 Versions) PLL Lock Time Fout=66 MHz and CL=15pF CCJ2 Fout=133MHz and CL=30PF Fout=166MHz and CL=15pF tLOCK From 0.95VDD and valid clock presented at CLKIN 45 40 45 50 50 50 80 70 80 130 150 55 60 55 2.2 1.5 1.5 1.2 150 150 150 300 400 % % % ns ns ns ns ps ps ps ps ps Input-to-Output Delay Dt -200 - 75 100 50 100 150 75 - 200 150 200 100 200 300 150 1.0 ps ps ps ps ps ps ps ms Rev 1.4, May 28, 2007 Page 7 of 18 SL23EP08 Operating Conditions (I-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C Description Operating Voltage Operating Temperature Input Capacitance Symbol VDD TA VIH Condition VDD+/-10% Ambient Temperature Pins 1, 8, 9 and 16 Min 2.97 -40 - Typ 3.3 5 Max 3.63 85 8 Unit V °C pF DC Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85° Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Symbol VINL VINH IINL IINH Condition CLKIN, S2 and S1 pins CLKIN, S2 and S1 pins 0 < VIN < 0.8V CLKIN, S2 and S1 inputs VIN = 2.4 to VDD CLKIN, S2 and S1 inputs IOL = 8 mA (standard drive) Min – 2.0 – – – – 2.4 2.4 – – – – – 125 Typ – – 25 – – – – – 12 17 24 30 38 250 Max 0.8 VDD+0.3 50 50 0.4 0.4 – – 18 22 32 40 50 375 Unit V V µA µA V V V V µA mA mA mA mA k Output LOW Voltage VOL IOL = 12 mA (high drive) IOH = –8 mA (standard drive) Output HIGH Voltage Power Down Supply Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Pull-up and Pull-down Resistors VOH IOH = –12 mA (high drive) IIDDPD IDD1 IDD2 IDD3 IDD4 RPUD Measured at CLKIN= GND to VDD or input is floating All Outputs CL=0, 33.3 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 66.6 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 100 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 133.3 MHz CLKIN S2=S1=1 (high), all versions Pins-1/2/3/7/8/9/10/11/14/15 250k -typ Rev 1.4, May 28, 2007 Page 8 of 18 SL23EP08 Switching Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 2.5+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Symbol FOUT1 FOUT2 Condition CL=15pf, -1H and -2H versions CL=22pf, -1H and -2H versions CL=30pf, -1H and -2H versions CL=15pf, -1, -2 and -4 versions CL=22pf, -1, -2 and -4 versions CL=30pf, -1, -2 and -4 versions Measured at VDD/2, all versions CL=30pF, Fout=66 MHz, all versions CL=15pF, Fout=66 MHz, all versions Measured at VDD/2 CL=15pF, Fout=133 MHz, all versions Measured at VDD/2 CL=15pF, Fout=166 MHz, all versions Measured at VDD/2 CL=30pF, -1, -2 and -4 versions CL=15pF, -1, -2 and -4 versions CL=30pF, -1H and -2H and versions CL=15pF, -1H and -2H and versions -1 and -2, measured from 0.8V to 2.0V, and outputs are equally loaded -1H and -2H and -4, measured at VDD/2 and outputs are equally loaded -1, -1H, 2H and -4, measured at VDD/2 and outputs are equally loaded -2, measured at VDD/2 and outputs are equally loaded All versions, measured at VDD/2 and outputs are equally loaded All versions, CLKIN to FBK rising edge, measured at VDD/2 and outputs are equally loaded and S2=S1=1 Fout=66 MHz and CL=15pF Min 10 10 10 10 10 10 30 40 45 40 45 - Typ 50 50 50 50 50 80 70 80 130 250 Max 220 200 135 200 135 100 70 60 55 60 55 2.2 1.5 1.5 1.2 150 150 150 300 500 Unit MHz MHz MHz MHz MHz MHz % % % % % ns ns ns ns ps ps ps ps ps Output Frequency Range FOUT3 FOUT4 FOUT5 FOUT6 Input Duty Cycle Output Duty Cycle Output Duty Cycle Output Duty Cycle Output Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output-to-Output Skew on Same Bank Output-to-Output Skew on Same Bank Output-to-Output Skew Between Bank A and B Output-to-Output Skew Between Bank A and B Device-to-Device Skew DC1 DC2 DC3 DC4 DC5 tr/f1 tr/f2 tr/f3 tr/f4 SKW2 SKW2 SKW3 SKW4 SKW5 Input-to-Output Delay Dt -200 - 85 110 65 110 200 150 225 115 225 Page 9 of 18 ps ps ps ps ps Cycle-to-Cycle Jitter (-1 and -2 Versions) Cycle-to-Cycle Jitter Rev 1.4, May 28, 2007 CCJ1 Fout=66MHz and CL=30PF Fout=166MHz and CL=15pF CCJ2 Fout=66 MHz and CL=15pF SL23EP08 (-1H, -2H and -4 Versions) PLL Lock Time tLOCK Fout=133MHz and CL=30PF Fout=166MHz and CL=15pF From 0.95VDD and valid CLKIN 175 100 350 175 1.0 ps ps ms Operating Conditions (C-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Operating Voltage Operating Temperature Input Capacitance Symbol VDD TA VIH Condition VDD+/-10% Ambient Temperature Pins 1, 8, 9 and 16 Min 2.25 0 - Typ 2.5 5 Max 2.75 70 7 Unit V °C pF DC Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Symbol VINL VINH IINL IINH Condition CLKIN, S2 and S1 pins CLKIN, S2 and S1 pins 0 < VIN < 0.7V CLKIN, S2 and S1 inputs VIN = 1.7 to VDD CLKIN, S2 and S1 inputs IOL = 6 mA (standard drive) Min – 1.7 – – – – 2.0 2.0 – – – – – 125 Typ – – 25 – – – – – 8 15 20 26 32 250 Max 0.7 VDD+0.3 50 50 0.3 0.3 – – 12 18 25 33 40 375 Unit V V µA µA V V V V µA mA Output LOW Voltage VOL IOL = 8 mA (high drive) IOH = – 6 mA (standard drive) Output HIGH Voltage Power Down Supply Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Pull-up and Pull-down Resistors VOH IOH = – 8 mA (high drive) IIDDPD IDD1 IDD2 IDD3 IDD4 RPUD Measured at CLKIN= GND to VDD or input is floating All Outputs CL=0, 33.3 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 66.6 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 100 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 133.3 MHz CLKIN S2=S1=1 (high), all versions Pins-1/2/3/7/8/9/10/11/14/15 250k -typ mA mA mA k Rev 1.4, May 28, 2007 Page 10 of 18 SL23EP08 Switching Electrical Characteristics (C-Grade) Unless otherwise stated VDD= 2.5+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Description Symbol FOUT1 FOUT2 Condition CL=15pf, -1H and -2H CL=22pf, -1H and -2H CL=30pf, -1H and -2H CL=15pf, -1, -2 and -4 CL=22pf, -1, -2 and -4 CL=30pf, -1, -2 and -4 Measured at VDD/2, all versions Min 10 10 10 10 10 10 30 Typ 50 Max 170 135 100 135 100 75 70 Unit MHz MHz MHz MHz MHz MHz % Output Frequency Range FOUT1 FOUT4 FOUT5 FOUT1 Input Duty Cycle DC1 Switching Electrical Characteristics (C-Grade-Cont.) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Output Duty Cycle Output Duty Cycle Output Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output-to-Output Skew on Same Bank Output-to-Output Skew on Same Bank Output-to-Output Skew Between Bank A and B Output-to-Output Skew Between Bank A and B Device-to-Device Skew DC2 DC3 DC4 tr/f1 tr/f2 tr/f3 tr/f4 SKW2 SKW2 SKW3 SKW4 SKW5 CL=15pF, Fout=66 MHz, all versions Measured at VDD/2 CL=15pF, Fout=133 MHz, all versions Measured at VDD/2 CL=15pF, Fout=166 MHz, all versions Measured at VDD/2 CL=30pF, -1, -2 and -4 versions Measured at 0.6 to 1.8V CL=15pF, -1, -2 and -4 versions Measured at 0.6 to 1.8V CL=30pF, -1H and -2H and versions Measured at 0.6 to 1.8V CL=15pF, -1H and -2H and versions Measured at 0.6 to 1.8V -1 and -2, measured from 0.8V to 2.0V, and outputs are equally loaded -1H and -2H and -4, measured at VDD/2 and outputs are equally loaded -1, -1H, 2H and -4, measured at VDD/2 and outputs are equally loaded -2, measured at VDD/2 and outputs are equally loaded All versions, measured at VDD/2 and outputs are equally loaded All versions, CLKIN to FBK rising edge, measured at VDD/2 and outputs are equally loaded and S2=S1=1 45 45 40 50 50 50 80 70 80 130 150 55 55 60 2.0 1.6 1.4 1.1 200 200 200 350 500 % % % ns ns ns ns ps ps ps ps ps Input-to-Output Delay Dt -250 - 250 ps Rev 1.4, May 28, 2007 Page 11 of 18 SL23EP08 Cycle-to-Cycle Jitter (-1, -2 and -4 Versions) Cycle-to-Cycle Jitter (-1H and -2H Versions) PLL Lock Time CCJ1 Fout=66 MHz and CL=15pF Fout=133MHz and CL=15pF CCJ2 tLOCK Fout=66MHz and CL=15pF Fout=166MHz and CL=15pF From 0.95VDD and valid clock presented at CLKIN 75 50 100 75 150 100 200 150 1.0 ps ps ps ps ms Operating Conditions (I-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C Description Operating Voltage Operating Temperature Input Capacitance Symbol VDD TA VIH Condition VDD+/-10% Ambient Temperature Pins 1, 8, 9 and 16 Min 2.25 -40 - Typ 2.5 5 Max 2.75 85 8 Unit V °C pF Rev 1.4, May 28, 2007 Page 12 of 18 SL23EP08 DC Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85° Description Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current Symbol VINL VINH IINL IINH Condition CLKIN, S2 and S1 pins CLKIN, S2 and S1 pins 0 < VIN < 0.7V CLKIN, S2 and S1 inputs VIN = 1.7V to VDD CLKIN, S2 and S1 inputs IOL = 6 mA (standard drive) Min – 1.7 – – – – 2.0 2.0 – – – – – 125 Typ – – 25 – – – – – 8 16 21 27 34 250 Max 0.7 VDD+0.3 50 50 0.3 0.3 – – 12 20 28 36 44 375 Unit V V µA µA V V V V µA mA mA mA mA k Output LOW Voltage VOL IOL = 8 mA (high drive) IOH = –6 mA (standard drive) Output HIGH Voltage Power Down Supply Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Pull-up and Pull-down Resistors VOH IOH = –8 mA (high drive) IIDDPD IDD1 IDD2 IDD3 IDD4 RPUD Measured at CLKIN= GND to VDD or input is floating All Outputs CL=0, 33.3 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 66.6 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 100 MHz CLKIN S2=S1=1 (high), all versions All Outputs CL=0, 133.3 MHz CLKIN S2=S1=1 (high), all versions Pins-1/2/3/7/8/9/10/11/14/15 250k -typ Switching Electrical Characteristics (I-Grade) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C Description Symbol FOUT1 FOUT2 Output Frequency Range FOU3 FOUT4 FOUT5 FOUT6 Input Duty Cycle Output Duty Cycle DC1 DC2 Condition CL=15pf, -1H and -2H versions CL=22pf, -1H and -2H versions CL=30pF, -1H and -2H versions CL=15pf, -1, -2 and -4 versions CL=22pf, -1, -2 and -4 versions CL=30pf, -1, -2 and -4 versions Measured at VDD/2, all versions CL=30pF, Fout=66 MHz, all versions Measured at VDD/2 Min 10 10 10 10 10 10 30 40 Typ 50 50 Max 175 135 100 135 100 75 70 60 Unit MHz MHz MHz MHz MHz MHz % % Rev 1.4, May 28, 2007 Page 13 of 18 SL23EP08 Switching Electrical Characteristics (I-Grade-Cont.) Unless otherwise stated VDD= 2.5V+/- 10%, CL=15pF and Ambient Temperature range -40 to +85°C Output Duty Cycle Output Duty Cycle Output Duty Cycle Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output-to-Output Skew on Same Bank Output-to-Output Skew on Same Bank Output-to-Output Skew Between Bank A and B Output-to-Output Skew Between Bank A and B Device-to-Device Skew DC3 DC4 DC5 tr/f1 tr/f2 tr/f3 tr/f4 SKW2 SKW2 SKW3 SKW4 SKW5 CL=15pF, Fout=66 MHz, all versions Measured at VDD/2 CL=15pF, Fout=133 MHz, all versions Measured at VDD/2 CL=15pF, Fout=166 MHz, all versions Measured at VDD/2 CL=30pF, -1, -2 and -4 versions Measured at 0.6 to 1.8V CL=15pF, -1, -2 and -4 versions Measured at 0.6 to 1.8V CL=30pF, -1H and -2H and versions Measured at 0.6 to 1.8V CL=15pF, -1H and -2H and versions Measured at 0.6 to 1.8V -1 and -2, measured from 0.8V to 2.0V, and outputs are equally loaded -1H and -2H and -4, measured at VDD/2 and outputs are equally loaded -1, -1H, 2H and -4, measured at VDD/2 and outputs are equally loaded -2, measured at VDD/2 and outputs are equally loaded All versions, measured at VDD/2 and outputs are equally loaded All versions, CLKIN to FBK rising edge, measured at VDD/2 and outputs are equally loaded and S2=S1=1 Fout=66 MHz and CL=15pF Fout=133MHz and CL=15pF CCJ2 tLOCK Fout=66 MHz and CL=15pF Fout=166MHz and CL=15pF From 0.95VDD and valid CLKIN 45 45 40 50 50 50 100 100 100 180 275 55 55 60 2.2 1.8 1.5 1.2 220 220 220 375 550 % % % ns ns ns ns ps ps ps ps ps Input-to-Output Delay Cycle-to-Cycle Jitter (-1, -2 and -4 Versions) Cycle-to-Cycle Jitter (-1H and -2H Versions) PLL Lock Time Dt -200 - 80 70 70 60 - 200 175 150 150 125 1.0 ps ps ps ps ps ms CCJ1 Rev 1.4, May 28, 2007 Page 14 of 18 SL23EP08 External Components & Design Considerations Typical Application Schematic Comments and Recommendations Decoupling Capacitor: A decoupling capacitor of 0.1 F must be used between VDD and VSS pins. Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the VDD pin and to the GND via should be kept as short as possible. Do not use vias between the decoupling capacitor and the VDD pin. Series Termination Resistor: A series termination resistor is recommended if the distance between the output clocks and the load is over 1 ½ inch. The nominal impedance of the clock outputs is given on the page 5. Place the series termination resistors as close to the clock outputs as possible. Zero Delay and Skew Control: All outputs and CLKIN pins should be loaded with the same load to achieve “Zero Delay” between the CLKIN and the outputs. The CLKOUT pin is connected to CLKIN internally on-chip for feedback to PLL. For applications requiring zero input/output delay, the load at the all output pins including the CLKOUT pin must be the same. If any delay adjustment is required, the capacitance at the CLKOUT pin could be increased or decreased to increase or decrease the delay between Bank A and B clocks and CLKIN. For minimum pin-to-pin skew, the external load at all the Bank A and B clocks must be the same. Rev 1.4, May 28, 2007 Page 15 of 18 SL23EP08 Package Outline and Package Dimensions 16-Lead TSSOP (4.4mm) 16 9 6.250(0.246) 6.500(0.256) 4.300(0.169) 4.500(0.177) Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) Pin-1 ID 1 8 2.900(0.114) 3.100(0.122) 1.100(0.043) MAX 0.650(0.025) BSC Gauge Plane 0.850(0.033) 0.950(0.037) 0.050(0.002) 0.150(0.006) 0.090(0.003) 0.200(0.008) 0.190(0.007) 0.300(0.012) 0.076(0.003) 0.650(0.025) BSC Seating Plane 0 to 8 ° 0.500(0.020) 0.700(0.027) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JA JA JC Condition Still air 1m/s air flow 3m/s air flow Independent of air flow Min - Typ 80 70 68 36 Max - Unit °C/W °C/W °C/W °C/W Rev 1.4, May 28, 2007 Page 16 of 18 SL23EP08 Package Drawing and Dimensions (Cont.) 16-Lead SOIC (150 Mil) 16 9 0.150(3.810) 0.157(3.987 Dimensions are in milimeters(inches). Top line: (MIN) and Bottom line: (Max) Pin-1 ID 0.230(5.842) 0.244(6.197) 1 8 0.189(4.800) 0.196(4.978) 0.010(0.2540) X 45° 0.016(0.406) 0.0075(0.190) 0.0098(0.249) 0.061(1.549) 0.068(1.727) 0.004(0.102) 0.050(1.270) BSC 0.0138(0.350) 0.0192(0.487) 0.004(0.102) 0.0098(0.249) Seating plane 0° to 8° 0.016(0.406) 0.035(0.889) Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol JA JA JA JC Condition Still air 1m/s air flow 3m/s air flow Independent of air flow Min - Typ 120 115 105 60 Max - Unit °C/W °C/W °C/W °C/W Rev 1.4, May 28, 2007 Page 17 of 18 SL23EP08 Ordering Information [3] Ordering Number SL23EP08SC-1 SL23EP08SC-1T SL23EP08SI-1 SL23EP08SI-1T SL23EP08SC-1H SL23EP08SC-1HT SL23EP08SI-1H SL23EP08SI-1HT SL23EP08ZC-1H SL23EP08ZC-1HT SL23EP08ZI-1H SL23EP08ZI-1HT SL23EP08SC-2 SL23EP08SC-2T SL23EP08SI-2 SL23EP08SI-2T SL23EP08SC-2H SL23EP08SC-2HT SL23EP08SC-4 SL23EP08SC-4T SL23EP08SI-4 SL23EP08SI-4T SL23EP08SC-5H SL23EP08SC-5HT Notes: 3. The SL23EP08 products are RoHS compliant. Marking SL23EP08SC-1 SL23EP08SC-1 SL23EP08SI-1 SL23EP08SI-1 SL23EP08SC-1H SL23EP08SC-1H SL23EP08SI-1H SL23EP08SI-1H SL23EP08ZC-1H SL23EP08ZC-1H SL23EP08ZI-1H SL23EP08ZI-1H SL23EP08SC-2 SL23EP08SC-2 SL23EP08SI-2 SL23EP08SI-2 SL23EP08SC-2H SL23EP08SC-2H SL23EP08SC-4 SL23EP08SC-4 SL23EP08SI-4 SL23EP08SI-4 SL23EP08SC-5H SL23EP08SC-5H Shipping Package Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tape and Reel Tube Tube Package 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin TSSOP 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC 16-pin SOIC Temperature 0 to 70°C 0 to 70°C -40 to 85°C -40 to 85°C 0 to 70°C 0 to 70°C -40 to 85°C -40 to 85°C 0 to 70°C 0 to 70°C -40 to 85°C -40 to 85°C 0 to 70°C 0 to 70°C -40 to 85°C -40 to 85°C 0 to 70°C 0 to 70°C 0 to 70°C 0 to 70°C -40 to 85°C -40 to 85°C 0 to 70°C 0 to 70°C While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and an expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice. Rev 1.4, May 28, 2007 Page 18 of 18