W209C

W209C Frequency Generator for Integrated Core Logic with 133MHz FSB Features • Maximized EMI suppression using Cypress’s Spread Spectrum technology • Low jitter and tightly controlled clock skew • Highly integrated device providing clocks required for CPU, core logic, and SDRAM • Two copies of CPU clock • Nine copies of SDRAM clock • Eight copies of PCI clock • One copy of synchronous APIC clock • Two copies of 66 MHz outputs • Two copies of 48 MHz outputs • One copy of selectable 24 or 48 MHz clock • One copy of double strength 14.31818 MHz reference clock • Power-down control • SMBus interface for turning off unused clocks Table 1. Frequency Selections FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 75.3 95.0 129.0 150.0 150.0 110.0 140.0 144.0 68.3 105.0 138.0 140.0 66.8 100.2 133.6 133.6 157.3 160.0 146.6 122.0 127.0 122.0 117.0 114.0 80.0 78.0 166.0 160.0 66.6 100.0 133.3 133.3 SDRAM 3V66 113.0 95.0 129.0 113.0 150.0 110.0 140.0 108.0 102.5 105.0 138.0 105.0 100.2 100.2 133.6 100.2 118.0 120.0 110.0 91.5 127.0 122.0 117.0 114.0 120.0 117.0 166.0 160.0 100.0 100.0 133.3 100.0 75.3 63.3 86.0 75.3 73.0 93.3 72.0 68.3 70.0 92.0 70.0 66.8 66.8 89.1 66.8 78.6 80.0 73.3 61.0 84.6 81.3 78.0 76.0 80.0 78.0 55.3 53.3 66.6 66.6 88.9 66.6 PCI 37.6 31.6 43.0 37.6 36.6 46.7 36.0 34.1 35.0 46.0 35.0 33.4 33.4 44.4 33.4 39.3 40.0 36.6 30.5 42.3 40.6 39.0 38.0 40.0 39.0 27.6 26.7 33.3 33.3 44.4 33.3 APIC 18.8 15.8 21.5 18.8 25.0 18.3 23.3 18.0 17.0 17.5 23.0 17.5 16.7 16.7 22.2 16.7 19.6 20.0 18.3 15.2 21.1 20.3 19.5 19.0 20.0 19.5 13.8 13.3 16.6 16.6 22.2 16.6 SS OFF –0.6% OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ±0.45% ±0.45% ±0.45% ±0.45% OFF OFF OFF –0.6% OFF –0.6% OFF OFF OFF OFF OFF OFF –0.6% –0.6% –0.6% –0.6% 100.0 50.0 Key Specifications CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps APIC, 48-MHz, 3V66, PCI Outputs Cycle-to-Cycle Jitter: ................................................... 500 ps CPU, 3V66 Output Skew:............................................ 175 ps SDRAM, APIC, 48-MHz Output Skew:........................ 250 ps PCI Output Skew:........................................................ 500 ps CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns CPU to 3V66 Skew (@ 66 MHz) ........................ 7.0 to 8.0 ns 3V66 to PCI Skew (3V66 lead)........................... 1.5 to 3.5 ns PCI to APIC Skew ..................................................... ± 0.5 ns Block Diagram VDDQ3 X1 X2 XTAL OSC PLL REF FREQ REF2X/FS3* Pin Configuration REF2x/FS3* VDDQ3 X1 X2 GND VDDQ3 3V66_0 3V66_1 GND FS0*/PCI0 FS1*/PCI1 FS2*/PCI2 GND PCI3 PCI4 VDDQ3 PCI5 PCI6 PCI7 GND 48MHz_0 FS4*/48MHz_1 SI0/24_48#MHz* VDDQ3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 [1] 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDQ2 APIC VDDQ2 CPU0 CPU1 GND VDDQ3 SDRAM0 SDRAM1 SDRAM2 GND SDRAM3 SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 DCLK GND PWRDWN#^ SCLK VDDQ3 GND SDATA VDDQ2 SDATA SCLK SMBus Logic (FS0:4*) Divider, Delay, and Phase Control Logic CPU0:1 2 APIC VDDQ3 2 W209C 3V66_0:1 FS0*/PCI0 FS1*/PCI1 FS2*/PCI2 PLL 1 5 PCI3:7 SDRAM0:7 DCLK VDDQ3 48MHz_0 PWRDWN# 8 PLL2 /2 FS4*/48MHz_1 SI0/24_48#MHz* Note: 1. Internal pull-down or pull-up resistors present on inputs marked with * or ^ respectively. Design should not rely solely on internal pull-up or pull-down resistor to set I/O pins HIGH or LOW respectively. Rev 1.0, November 20, 2006 2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550 Page 1 of 15 www.SpectraLinear.com W209C I Pin Definitions Pin Name REF2x/FS3 Pin No. 1 Pin Type I/O Pin Description Reference Clock with 2x Drive/Frequency Select 3: 3.3V 14.318-MHz clock output. This pin also serves as the select strap to determine device operating frequency as described in Table 1. Crystal Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Output: An input connection for an external 14.318-MHz crystal connection. If using an external reference, this pin must be left unconnected. PCI Clock 0/Frequency Selection 0: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 1/Frequency Selection 1: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 2/Frequency Selection 2: 3.3V 33-MHz PCI clock outputs. This pin also serves as the select strap to determine device operating frequency as described in Table 1. PCI Clock 3 through 7: 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individually turned off via SMBus interface. 66-MHz Clock Output: 3.3V output clocks. The operating frequency is controlled by FS0:4 (see Table 1). 48-MHz Clock Output: 3.3V fixed 48-MHz, non-spread spectrum clock output. 48-MHz Clock Output/Frequency Selection 4: 3.3V fixed 48-MHz, non-spread spectrum clock output. This pin also serves as the select strap to determine device operating frequency as described in Table 1. Clock Output for Super I/O: This is the input clock for a Super I/O (SIO) device. During power up, it also serves as a selection strap. If it is sampled HIGH, the output frequency for SIO is 24 MHz. If the input is sampled LOW, the output is 48 MHz. Power Down Control: LVTTL-compatible input that places the device in power-down mode when held LOW. CPU Clock Outputs: Clock outputs for the host bus interface. Output frequencies depending on the configuration of FS0:4. Voltage swing is set by VDDQ2. SDRAM Clock Outputs: 3.3V outputs for SDRAM and chipset. The operating frequency is controlled by FS0:4 (see Table 1). Synchronous APIC Clock Outputs: Clock outputs running synchronous with the PCI clock outputs. Voltage swing set by VDDQ2. Data pin for SMBus circuitry. Clock pin for SMBus circuitry. 3.3V Power Connection: Power supply for SDRAM output buffers, PCI output buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V. 2.5V Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to 2.5V or 3.3V. Ground Connections: Connect all ground pins to the common system ground plane. X1 X2 FS0*/PCI0 3 4 10 I I I/O FS1*/PCI1 11 I/O FS2*/PCI2 12 I/O PCI3:7 3V66_0:1 48MHz_0 FS4*/ 48MHz_1 SIO/ 24_48#MHz* PWRDWN# CPU0:1 SDRAM0:7, DCLK APIC SDATA SCLK VDDQ3 VDDQ2 GND 14, 15, 17, 18, 19 7,8 21 22 O O O I/O 23 I/O 29 45, 44 41, 40, 39, 37, 36, 35, 33, 32, 31 47 25 28 2, 6, 16, 24, 27, 34, 42 46, 48 5, 9, 13, 20, 26, 30, 38, 43, I O O O I/O I P P G Rev 1.0, November 20, 2006 Page 2 of 15 W209C Output Strapping Resistor Series Termination Resistor W209C Power-on Reset Timer Clock Load Output Buffer Output Three-state Q Hold Output Low D 10k Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Overview The W209C is a highly integrated frequency timing generator, supplying all the required clock sources for an Intel® architecture platform using graphics integrated core logic. Functional Description I/O Pin Operation Pin # 1, 10, 11, 12, 22, and 23 are dual-purpose l/O pins. Upon power-up the pin acts as a logic input. An external 10-k strapping resistor should be used. Figure 1 shows a suggested method for strapping resistor connections. After 2 ms, the pin becomes an output. Assuming the power supply has stabilized by then, the specified output frequency 10 ns 20 ns is delivered on the pins. If the power supply has not yet reached full value, output frequency initially may be below target, but will increase to target once supply voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. Offsets Among Clock Signal Groups Figure 2 and Figure 3 represent the phase relationship among the different groups of clock outputs from W209C when it is providing a 66-MHz CPU clock and a 100-MHz CPU clock, respectively. It should be noted that when CPU clock is operating at 100 MHz, CPU clock output is 180 degrees out of phase with SDRAM clock outputs. 0 ns 30 ns 40 ns CPU 100 Period CPU 66-MHz SDRAM 100 Period SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC Hub-PC Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock) Rev 1.0, November 20, 2006 Page 3 of 15 W209C 0 ns 10 ns 20 ns 30 ns 40 ns CPU 100 Period CPU 100-MHz SDRAM 100 Period SDRAM 100-MHz 3V66 66-MHz PCI 33-MHz REF 14.318-MHz USB 48-MHz APIC Hub-PC Figure 3. Group Offset Waveforms (100-MHz CPU Clock, 100-MHz SDRAM Clock) Power Down Control W209C provides one PWRDWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and all clock outputs are driven LOW. 0ns 25ns 50ns 75ns Center 1 VCO Internal CPU 100MHz 3V66 66MHz PCI 33MHz APIC 33MHz PwrDwn SDRAM 100MHz REF 14.318MHz USB 48MHz 2 Figure 4. W209C PWRDWN# Timing Diagram[2, 3, 4, 5] Notes: 2. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition. 3. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W209C. 4. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states. 5. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz. Rev 1.0, November 20, 2006 Page 4 of 15 W209C Spread Spectrum Frequency Timing Generator The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 5. As shown in Figure 5, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) 5dB/div Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The output clock is modulated with a waveform depicted in Figure 6. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is ±0.5% of the selected frequency. Figure 6 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. SSFTG Typical Clock Amplitude (dB) -SS% Frequency Span (MHz) +SS% Figure 5. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MAX. FREQUENCY 10% 20% 30% 40% 50% 60% 70% 80% 90% 10% 20% 30% 40% 50% 60% 70% 80% 100% 90% MIN. Figure 6. Typical Modulation Profile Rev 1.0, November 20, 2006 100% Page 5 of 15 W209C 1 bit Start bit 7 bits Slave Address 1 R/W 1 Ack 8 bits Command Code 1 Ack Byte Count = N Ack 1 bit Data Byte 1 8 bits Ack 1 Data Byte 2 8 bits Ack 1 ... Data Byte N 8 bits Ack 1 Stop 1 Figure 7. An Example of a Block Write[6] Serial Data Interface The W209C features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Data Protocol The clock driver serial protocol accepts only block writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. Indexed bytes are not allowed. A block write begins with a slave address and a write condition. After the command code the core logic issues a byte count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed to Table 2. Example of Possible Byte Count Value Byte Count Byte MSB 0000 0000 0000 0000 0000 0000 0000 0000 0010 LSB 0000 0001 0010 0011 0100 0101 0110 0111 0000 Not allowed. Must have at least one byte Data for functional and frequency select register (currently byte 0 in spec) Reads first two bytes of data (byte 0 then byte 1) Reads first three bytes (byte 0, 1, 2 in order) Reads first four bytes (byte 0, 1, 2, 3 in order) Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[7] Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[7] Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order) Max. byte count supported = 32 Notes transfer a maximum of 32 data bytes. The slave receiver address for W209C is 11010010. Figure 7 shows an example of a block write. The command code and the byte count bytes are required as the first two bytes of any transfer. W209C expects a command code of 0000 0000. The byte count byte is the number of additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. Table 2 shows an example of a possible byte count value. A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The command code and byte count bytes are ignored by the W209C. However, these bytes must be included in the data write sequence to maintain proper byte allocation. Table 3. Serial Data Interface Control Functions Summary Control Function Output Disable Description Any individual clock output(s) can be disabled. Disabled outputs are actively held LOW. Reserved function for future device revision or production device testing. Common Application Unused outputs are disabled to reduce EMI and system power. Examples are clock outputs to unused PCI slots. No user application. Register bit must be written as 0. (Reserved) Notes: 6. The acknowledgment bit is returned by the slave/receiver (W209C). 7. Bytes 6 and 7 are not defined for W209C. Rev 1.0, November 20, 2006 Page 6 of 15 W209C W209C Serial Configuration Map 1. The serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 0: Control Register (1 = Enable, 0 = Disable)[8] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 23 21, 22 Name Reserved Reserved Reserved Reserved Reserved 24/48 MHz 48 MHz Reserved Default 0 0 0 0 0 1 1 0 Reserved Reserved Reserved Reserved Reserved (Active/Inactive) (Active/Inactive) Reserved Pin Function 2. All unused register bits (reserved and N/A) should be written to a “0” level. 3. All register bits labeled “Initialize to 0" must be written to zero during initialization. Failure to do so may result in higher than normal operating current. The controller will read back the written value. Byte 1: Control Register (1 = Enable, 0 = Disable)[8] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 32 33 35 36 37 39 40 41 Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description Byte 2: Control Register (1 = Enable, 0 = Disable)[8] Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 19 18 17 15 14 12 11 10 Name PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 PCI0 Default 1 1 1 1 1 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Pin Description Note: 8. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. Rev 1.0, November 20, 2006 Page 7 of 15 W209C Byte 3: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 31 47 Name DCLK Reserved Reserved Reserved APIC Reserved Reserved Reserved Default 1 0 0 0 1 0 1 0 (Active/Inactive) Reserved Reserved Reserved (Active/Inactive) Reserved Reserved Reserved Pin Description Byte 4: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# SEL3 SEL2 SEL1 SEL0 FS(0:4) Override SEL4 Reserved Test Mode Name Default 0 0 0 0 0 0 1 0 See Table 4 See Table 4 See Table 4 See Table 4 0 = Select operating frequency by FS(0:4) strapping 1 = Select operating frequency by SEL(0:4) bit settings See Table 4 Reserved 0 = Normal 1 = Three-stated Pin Function Byte 5: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 0 0 0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Byte 6: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Pin# Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 1 1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Pin Description Rev 1.0, November 20, 2006 Page 8 of 15 W209C Byte 6: Reserved Register (1 = Enable, 0 = Disable) Bit Bit 0 Pin# Input Conditions Data Byte 4, Bit 3 = 1 Bit 2 SEL_4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 7 SEL_3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 SEL_2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 5 SEL_1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 4 SEL_0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 75.3 95.0 129.0 150.0 150.0 110.0 140.0 144.0 68.3 105.0 138.0 140.0 66.8 100.2 133.6 133.6 157.3 160.0 146.6 122.0 127.0 122.0 117.0 114.0 80.0 78.0 166.0 160.0 66.6 100.0 133.3 133.3 SDRAM 113.0 95.0 129.0 113.0 150.0 110.0 140.0 108.0 102.5 105.0 138.0 105.0 100.2 100.2 133.6 100.2 118.0 120.0 110.0 91.5 127.0 122.0 117.0 114.0 120.0 117.0 166.0 160.0 100.0 100.0 133.3 100.0 3V66 75.3 63.3 86.0 75.3 100.0 73.0 93.3 72.0 68.3 70.0 92.0 70.0 66.8 66.8 89.1 66.8 78.6 80.0 73.3 61.0 84.6 81.3 78.0 76.0 80.0 78.0 55.3 53.3 66.6 66.6 88.9 66.6 PCI 37.6 31.6 43.0 37.6 50.0 36.6 46.7 36.0 34.1 35.0 46.0 35.0 33.4 33.4 44.4 33.4 39.3 40.0 36.6 30.5 42.3 40.6 39.0 38.0 40.0 39.0 27.6 26.7 33.3 33.3 44.4 33.3 APIC 18.8 15.8 21.5 18.8 25.0 18.3 23.3 18.0 17.0 17.5 23.0 17.5 16.7 16.7 22.2 16.7 19.6 20.0 18.3 15.2 21.1 20.3 19.5 19.0 20.0 19.5 13.8 13.3 16.6 16.6 22.2 16.6 Spread Spectrum OFF –0.6% OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ±0.45% ±0.45% ±0.45% ±0.45% OFF OFF OFF –0.6% OFF –0.6% OFF OFF OFF OFF OFF OFF –0.6% –0.6% –0.6% –0.6% Name Reserved Default 0 Reserved Output Frequency Pin Description Table 4. Additional Frequency Selections through Serial Data Interface Data Bytes Rev 1.0, November 20, 2006 Page 9 of 15 W209C DC Electrical Characteristics[9] DC parameters must be sustainable under steady state (DC) conditions. Absolute Maximum DC Power Supply Parameter VDDQ3 VDDQ2 TS Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage Storage Temperature Min. –0.5 –0.5 –65 Max. 4.6 3.6 150 Unit V V °C Absolute Maximum DC I/O Parameter Vi/o3 Vi/o3 ESD prot. Description 3.3V Core Supply Voltage 2.5V I/O Supply Voltage Input ESD Protection Min. –0.5 –0.5 2000 Max. 4.6 3.6 Unit V V V Note: 9. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Rev 1.0, November 20, 2006 Page 10 of 15 W209C DC Operating Requirements Parameter VDD3 VDDQ3 VDDQ2 VDD3 = 3.3V±5% Vih3 Vil3 Iil VDDQ2 = 2.5V±5% Voh2 Vol2 VDDQ3 = 3.3V±5% Voh3 Vol3 VDDQ3 = 3.3V±5% Vpoh3 Vpol3 Cin Cxtal Cout Lpin Ta IOL PCI Bus Output High Voltage PCI Bus Output Low Voltage Input Pin Capacitance Xtal Pin Capacitance Output Pin Capacitance Pin Inductance Ambient Temperature Output Low Current PCI0:7 REF2X/FS3 48 MHz 24 MHz SDRAM0:12 CPU0:1 IOH Output High Current PCI0:7 REF2X/FS3 48 MHz 24 MHz SDRAM0:12 CPU0:1 Note: 10. Input Leakage Current does not include inputs with pull-up or pull-down resistors. Description 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 2.5V I/O Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current[10] 2.5V Output High Voltage 2.5V Output Low Voltage 3.3V Output High Voltage 3.3V Output Low Voltage Condition 3.3V±5% 3.3V±5% 2.5V±5% VDD3 0