SST29EE010A-120-4I-P

1 Megabit (128K x 8) Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A Data Sheet FEATURES: • Single Voltage Read and Write Operations – 5.0V-only for the SST29EE010A – 3.0-3.6V for the SST29LE010A – 2.7-3.6V for the SST29VE010A • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 3.0/2.7V – Standby Current: 10 µA (typical) • Fast Page Write Operation – 128 Bytes per Page, 1024 Pages – Page Write Cycle: 5 ms (typical) – Complete Memory Rewrite: 5 sec (typical) – Effective Byte Write Cycle Time: 39 µs (typical) • Fast Read Access Time – 5.0V-only operation: 90 and 120 ns – 3.0-3.6V operation: 150 and 200 ns – 2.7-3.6V operation: 200 and 250 ns • Latched Address and Data • Automatic Write Timing – Internal VPP Generation • End of Write Detection – Toggle Bit – Data# Polling • Hardware and Software Data Protection • TTL I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32 Pin PDIP – 32-Pin PLCC – 32-Pin TSOP (8mm x 20mm & 8mm x 14mm) updating of program, configuration, or data memory. For all system applications, the SST29EE010A/29LE010A/ 29VE010A significantly improve performance and reliability, while lowering power consumption. The SST29EE010A/29LE010A/29VE010A improve flexibility while lowering the cost for program, data, and configuration storage applications. To meet high density, surface mount requirements, the SST29EE010A/29LE010A/29VE010A are offered in 32pin TSOP and 32-lead PLCC packages. A 600-mil, 32pin PDIP package is also available. See Figures 1 and 2 for pinouts. Device Operation The SST page mode EEPROM offers in-circuit electrical write capability. The SST29EE010A/29LE010A/ 29VE010A does not require separate Erase and Program operations. The internally timed write cycle executes both erase and program transparently to the user. The SST29EE010A/29LE010A/29VE010A have industry standard Software Data Protection. The SST29EE010A/29LE010A/29VE010A are compatible with industry standard EEPROM pinouts and functionality. Read The Read operations of the SST29EE010A/29LE010A/ 29VE010A are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PRODUCT DESCRIPTION The SST29EE010A/29LE010A/29VE010A are 128K x 8 CMOS Page Write EEPROMs manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST29EE010A/29LE010A/29VE010A write with a single power supply. Internal Erase/Program is transparent to the user. The SST29EE010A/29LE010A/ 29VE010A conform to JEDEC standard pinouts for bytewide memories. Featuring high performance page write, the SST29EE010A/29LE010A/29VE010A provide a typical byte-write time of 39 µsec. The entire memory, i.e., 128 KBytes, can be written page-by-page in as little as 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a write cycle. To protect against inadvertent write, the SST29EE010A/29LE010A/29VE010A have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST29EE010A/29LE010A/29VE010A are offered with a guaranteed page write endurance of 104 cycles. Data retention is rated at greater than 100 years. The SST29EE010A/29LE010A/29VE010A are suited for applications that require convenient and economical © 1999 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 303-01 2/99 1 1 Megabit Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure 3). Write The Page Write to the SST29EE010A/29LE010A/ 29VE010A uses the JEDEC Standard Software Data Protection (SDP) three-byte command sequence. The Write operation consists of three steps. Step 1 is the three-byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the SST29EE010A/29LE010A/29VE010A. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP three-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal write cycle is initiated by the TBLCO timer after the rising edge of WE# or CE#, whichever occurs first. The write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 4 and 5 for WE# and CE# controlled page write cycle timing diagrams and Figures 13 and 15 for flowcharts. The Write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle, and the internal write cycle. The Software Data Protection consists of a specific three-byte load sequence that allows writing to the selected page and will leave the SST29EE010A/29LE010A/29VE010A protected at the end of the Page Write. The page load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal write cycle consists of the TBLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit. The Page Write operation allows the loading of up to 128 bytes of data into the page buffer of the SST29EE010A/ 29LE010A/29VE010A before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the page write feature of SST29EE010A/ 29LE010A/29VE010A allow the entire memory to be written in as little as 5 seconds. During the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A7 through A16. Any byte not loaded with user data will be written to FF. See Figures 4 and 5 for the page write cycle timing diagrams. If after the completion of the three-byte SDP load sequence the host loads a byte into the page buffer within a byte-load cycle time (TBLC) of 100 µs, the SST29EE010A/29LE010A/29VE010A will stay in the page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 µs (TBLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page load period can continue indefinitely, as long as the host continues to load the device within the byte-load cycle time of 100 µs. The page to be loaded is determined by the page address of the last byte loaded. Software Chip Erase The SST29EE010A/29LE010A/29VE010A provide a Chip Erase operation, which allows the user to simultaneously clear the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Software Chip Erase operation is initiated by using a specific six-byte load sequence. After the load sequence, the device enters into an internally timed cycle similar to the write cycle. During the Erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 8 for timing diagram, and Figure 17 for the flowchart. © 1999 Silicon Storage Technology, Inc. 2 303-01 2/99 1 Megabit Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A Write Operation Status Detection The SST29EE010A/29LE010A/29VE010A provide two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal write cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST29EE010A/29LE010A/29VE010A are in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. Once the write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 6 for Data# Polling timing diagram and Figure 14 for a flowchart. Toggle Bit (DQ6) During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0’s and 1’s, i.e. toggling between 0 and 1. When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 7 for Toggle Bit timing diagram and Figure 14 for a flowchart. The initial read of the Toggle Bit will typically be a “1”. Data Protection The SST29EE010A/29LE010A/29VE010A provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST29EE010A/29LE010A/29VE010A provide the JEDEC approved software data protection scheme for all data alteration operations, i.e., Write and Chip Erase. With this scheme, any Write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. The three byte-load sequence is used to initiate the write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 © 1999 Silicon Storage Technology, Inc. 3 303-01 2/99 1 Megabit Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A Product Identification The product identification mode identifies the device as the SST29EE010A/29LE010A/29VE010A and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST29EE010A/29LE010A/29VE010A. Users may wish to use the software product identification operation to identify the part (i.e. using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 9 for the software ID entry and read timing diagram and Figure 16 for the ID entry command sequence flowchart. The manufacturer and device codes are the same for both operations. Product Identification Mode Exit In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the read operation. The Reset operation may also be used to reset the device to the read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 4 for software command codes, Figure 10 for timing waveform and Figure 16 for a flowchart. TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Manufacturer’s Code 0000 H SST29EE010A Device Code 0001 H SST29LE010A Device Code 0001 H SST29VE010A Device Code 0001 H Data BF H 22 H 23 H 23 H 303 PGM T1.1 FUNCTIONAL BLOCK DIAGRAM OF SST 29EE010A/29LE010A/29VE010A X-Decoder 1,048,576 Bit EEPROM Cell Array A16 - A0 Address Buffer & Latches Y-Decoder and Page Latches CE# OE# WE# Control Logic I/O Buffers and Data Latches DQ7 - DQ0 303 ILL B1.0 © 1999 Silicon Storage Technology, Inc. 4 303-01 2/99 1 Megabit Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A A11 A9 A8 A13 A14 NC WE# VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 303 ILL F01.0 1 2 3 4 5 WE# FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES VCC A12 A15 A16 NC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 VSS NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 NC 6 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 7 8 9 303 ILL F02.0 32-Lead PLCC Top View 21 14 15 16 17 18 19 20 10 11 12 13 14 15 16 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS TABLE 2: PIN DESCRIPTION Symbol Pin Name A16-A7 Row Address Inputs A6-A0 DQ7-DQ0 Column Address Inputs Data Input/output Functions To provide memory addresses. Row addresses define a page for a write cycle. Column Addresses are toggled to load page data. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the write operations To provide 5-volt supply (± 10%) for the SST29EE010A, 3-volt supply (3.0-3.6V) for the SST29LE010A and 2.7-volt supply (2.7-3.6V) for the SST29VE010A Unconnected pins. 303 PGM T2.0 CE# OE# WE# Vcc Chip Enable Output Enable Write Enable Power Supply Vss NC Ground No Connection © 1999 Silicon Storage Technology, Inc. 5 303-01 2/99 1 Megabit Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A TABLE 3: OPERATION MODES SELECTION Mode CE# OE# Read VIL VIL Page Write VIL VIH Standby VIH X Write Inhibit X VIL Write Inhibit X X Software Chip Erase VIL VIH Product Identification Hardware Mode VIL VIL Software Mode SDP Enable Mode VIL VIL VIH VIH WE# VIH VIL X X VIH VIL VIH VIL VIL DQ DOUT DIN High Z High Z/ DOUT High Z/ DOUT DIN Manufacturer Code (BF) Device Code (see notes) Address AIN AIN, See Table 4 X X X AIN, See Table 4 A16 - A1 = VIL, A9 = VH, A0 = VIL A16 - A1 = VIL, A9 = VH, A0= VIH See Table 4 See Table 4 303 PGM T3.0 TABLE 4: SOFTWARE COMMAND CODES Command Sequence Page Write Software Chip Erase Software ID Entry Software ID Exit 1st Bus Write Cycle Addr(1) Data 5555H AAH 5555H AAH 5555H 5555H AAH AAH AAH 2nd Bus Write Cycle Addr(1) Data 2AAAH 55H 2AAAH 55H 2AAAH 2AAAH 2AAAH 55H 55H 55H 3rd Bus Write Cycle Addr(1) Data 5555H A0H 5555H 80H 5555H 5555H 5555H 90H F0H 80H 5555H AAH 2AAAH 55H 5555H 60H 4th Bus Write Cycle Addr(1) Data Addr(2) Data 5555H AAH 5th Bus Write Cycle Addr(1) Data 2AAAH 55H 6th Bus Write Cycle Addr(1) Data 5555H 10H Alternate Software 5555H ID Entry(3) Notes: (1) (2) 303 PGM T4.0 Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”. Page Write consists of loading up to 128 bytes (A6 - A0). (3) Alternate six-byte software Product-ID Command Code (4) The software Chip Erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. Notes for Software Product ID Command Code: 1. With A14 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0, SST29EE010A Device Code = 22H, is read with A0 = 1. SST29LE010A/29VE010A Device Code = 23H, is read with A0 = 1. 2. The device does not remain in Software Product ID Mode if powered down. 3. This device supports both the JEDEC standard three-byte command code sequence and SST’s original six-byte command code sequence. For new designs, SST recommends the three-byte command code sequence be used. © 1999 Silicon Storage Technology, Inc. 6 303-01 2/99 1 Megabit Page Mode EEPROM SST29EE010A / SST29LE010A / SST29VE010A Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C Storage Temperature ...................................................................................................................... -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V Transient Voltage (