SST39LF100-70-4C-WK

1 Mbit (64K x16) Multi-Purpose Flash SST39LF100 / SST39VF100 SST39LF/VF1003.0 & 2.7V 1 Mb (x16) MPF memories Data Sheet FEATURES: • Organized as 64K x16 • Single Voltage Read and Write Operations – 3.0-3.6V for SST39LF100 – 2.7-3.6V for SST39VF100 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) – Standby Current: 3 µA (typical) • Sector-Erase Capability – Uniform 2 KWord sectors • Fast Read Access Time – 45 ns for SST39LF100 – 70 ns for SST39VF100 • Latched Address and Data • Fast Erase and Word-Program – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Word-Program Time: 14 µs (typical) – Chip Rewrite Time: 1 second (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Sets • Packages Available – 40-lead TSOP (10mm x 14mm) – 48-ball TFBGA (6mm x 8mm) PRODUCT DESCRIPTION The SST39LF/VF100 devices are 64K x16 CMOS MultiPurpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF100 and SST39VF100 write (Program or Erase) with a single voltage power supply of 3.0-3.6V and 2.7-3.6V, respectively. Featuring high performance Word-Program, the SST39LF/ VF100 devices provide a typical Word-Program time of 14 µsec. The devices use Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. To protect against inadvertent write, the SST39LF/VF100 have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39LF/VF100 are offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39LF/VF100 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST39LF/VF100 significantly improve performance and reliability, while lowering power consumption. The SST39LF/VF100 inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 363 1 energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST39LF/ VF100 also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39LF/VF100 are offered in 40-lead TSOP and 48-ball TFBGA packages. See Figure 1 for pinout. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Read The Read operation of the SST39LF/VF100 is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 2). Chip-Erase Operation The SST39LF/VF100 provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 7 for timing diagram, and Figure 16 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Word-Program Operation The SST39LF/VF100 are programmed on a word-by-word basis. Before programming, one must ensure that the sector in which the word is programmed is erased. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 3 and 4 for WE# and CE# controlled Program operation timing diagrams and Figure 13 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Write Operation Status Detection The SST39LF/VF100 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal program or erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 2 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines A11-A15 are used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 8 for timing waveforms. Any commands issued during the Sector-Erase operation are ignored. Data# Polling (DQ7) When the SST39LF/VF100 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 5 for Data# Polling timing diagram and Figure 14 for a flowchart. ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 363 2 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Toggle Bit timing diagram and Figure 14 for a flowchart. Table 4 for software operation, Figure 9 for the Software ID Entry and Read timing diagram, and Figure 15 for the Software ID Entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION Address Manufacturer’s ID Device ID SST39LF/VF100 0001H 2788H T1.3 363 Data 00BFH 0000H Data Protection The SST39LF/VF100 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 10 for timing waveform and Figure 15 for a flowchart. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent Writes during power-up or power-down. Software Data Protection (SDP) The SST39LF/VF100 provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST39LF/VF100 devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 are “Don’t Care” during any SDP command sequence. Product Identification The Product Identification mode identifies the devices as SST39LF100 and SST39VF100 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 363 3 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet FUNCTIONAL BLOCK DIAGRAM X-Decoder SuperFlash Memory A0-A15 Address Buffer & Latches Y-Decoder CE# OE# WE# DQ15 - DQ0 363 ILL B1.2 Control Logic I/O Buffers and Data Latches A9 A10 A11 A12 A13 A14 A15 NC WE# VDD NC CE# DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Standard Pinout Top View Die Up 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS A8 A7 A6 A5 A4 A3 A2 A1 A0 OE# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS SST39LF100/SST39VF100 363 ILL F01.3 TOP VIEW (balls facing down) SST39LF/VF100 6 5 4 3 2 1 A13 A12 A14 A9 A8 A10 NC NC A6 A2 A15 NC NC DQ15 VSS A11 DQ7 DQ14 DQ13 DQ6 NC DQ5 DQ12 VDD DQ4 NC DQ2 DQ10 DQ11 DQ3 A5 A1 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS 363 ILL F02b.1 WE# NC NC A7 A3 NC NC A4 A B C D E F G H FIGURE 1: PIN ASSIGNMENTS FOR 40-LEAD TSOP AND 48-BALL TFBGA ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 363 4 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet TABLE 2: PIN DESCRIPTION Symbol A15-A0 DQ15-DQ0 Pin Name Address Inputs Data Input/output Functions To provide memory addresses. During Sector-Erase A15-A11 address lines will select the sector. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 3.0-3.6V for SST39LF100 2.7-3.6V for SST39VF100 CE# OE# WE# VDD VSS NC Chip Enable Output Enable Write Enable Power Supply Ground No Connection Unconnected pins. T2.2 363 TABLE 3: OPERATION MODES SELECTION Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 4 T3.2 363 CE# VIL VIL VIL VIH X X OE# VIL VIH VIH X VIL X WE# VIH VIL VIL X X VIH DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT Address AIN AIN Sector or Block address, XXH for Chip-Erase X X X 1. X can be VIL or VIH, but no other value. ©2001 Silicon Storage Technology, Inc. S71129-02-000 6/01 363 5 1 Mbit Multi-Purpose Flash SST39LF100 / SST39VF100 Data Sheet TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence Word-Program Sector-Erase Chip-Erase Software ID Exit7 Software ID Exit7 1. 2. 3. 4. 5. 6. 1st Bus Write Cycle Addr1 5555H 5555H 5555H XXH 5555H Data2 AAH AAH AAH AAH F0H AAH 2nd Bus Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2 55H 55H 55H 55H 55H 3rd Bus Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H Data2 A0H 80H 80H 90H F0H 4th Bus Write Cycle Addr1 WA3 5555H 5555H Data2 Data AAH AAH 5th Bus Write Cycle Addr1 2AAAH 2AAAH Data2 55H 55H 6th Bus Write Cycle Addr1 SAX4 5555H Data2 30H 10H Software ID Entry5,6 5555H T4.4 363 Address format A14-A0 (Hex), Addresses A15 can be VIL or VIH, but no other value, for the Command sequence DQ15 - DQ8 can be VIL or VIH, but no other value, for the Command sequence WA = Program word address SAX for Sector-Erase; uses A15-A11 address lines The device does not remain in Software Product ID Mode if powered down. With A15-A1 =0; SST Manufacturer’s ID= 00BFH, is read with A0 = 0, SST39LF100/SST39VF100 Device ID = 2788H, is read with A0 = 1 7. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V Transient Voltage (