SST39SF020-90-4C-PH

2 Megabit (256K x 8) Multi-Purpose Flash SST39SF020 Preliminary Specifications FEATURES: • Organized as 256 K X 8 • Single 5.0V Read and Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 20 mA (typical) – Standby Current: 10 µA (typical) • Sector Erase Capability – Uniform 4 KByte sectors • Fast Read Access Time: – 70 and 90 ns • Latched Address and Data • Fast Sector Erase and Byte Program: – Sector Erase Time: 7 ms (typical) – Chip Erase Time: 15 ms (typical) – Byte Program time: 20 µs (typical) – Chip Rewrite Time: 5 seconds (typical) • Automatic Write Timing - Internal Vpp Generation • End of Write Detection – Toggle Bit – Data# Polling • TTL I/O Compatibility • JEDEC Standard – EEPROM Pinouts and command set • Packages Available – 32-Pin PDIP – 32-Pin PLCC – 32-Pin TSOP (8mm x 14mm) 1 2 3 4 5 6 7 PRODUCT DESCRIPTION The SST39SF020 is a 256K x 8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39SF020 device writes (Program or Erase) with a 5.0V-only power supply. The SST39SF020 device conforms to JEDEC standard pinouts for x8 memories. Featuring high performance byte program, the SST39SF020 device provides a maximum byte-program time of 30 µsec. The entire memory can be erased and programmed byte by byte typically in 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, the SST39SF020 device has on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39SF020 device is offered with a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST39SF020 device is suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the SST39SF020 device significantly improves performance and reliability, while lowering power consumption. The SST39SF020 inherently uses less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST39SF020 device also improves flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of endurance cycles that have occurred. Therefore the system software or hardware does not have to be modified or derated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated endurance cycles. To meet high density, surface mount requirements, the SST39SF020 device is offered in 32-pin TSOP and 32pin PLCC packages. A 600 mil, 32-pin PDIP is also available. See Figures 1 and 2 for pinouts. Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while 8 9 10 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon storage Technology, Inc. 326-10 12/98 These specifications are subject to change without notice. 1 2 Megabit Multi-Purpose Flash SST39SF020 Preliminary Specifications keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39SF020 device is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 3). Byte Program Operation The SST39SF020 device is programmed on a byte-bybyte basis. The Program operation consists of three steps. The first step is the three-byte-load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 30 µs. See Figures 4 and 5 for WE# and CE# controlled Program operation timing diagrams and Figure 14 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Sector Erase Operation The Sector Erase operation allows the system to erase the device on a sector by sector basis. The sector architecture is based on uniform sector size of 4 KByte. The Sector Erase operation is initiated by executing a six-byte-command load sequence for software data protection with sector erase command (30H) and sector address (SA) in the last bus cycle. The address lines A12-A17 will be used to determine the sector address. The sector address is latched on the falling edge of the sixth WE# pulse , while the command (30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The end of Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 8 for timing waveforms. Any commands written during the Sector Erase operation will be ignored. © 1998 Silicon Storage Technology, Inc. Chip-Erase Operation The SST39SF020 device provides a Chip-Erase operation, which allows the user to erase the entire memory array to the “1’s” state. This is useful when the entire device must be quickly erased. The Chip Erase operation is initiated by executing a sixbyte software data protection command sequence with Chip Erase command (10H) with address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for timing diagram, and Figure 17 for the flowchart. Any commands written during the Chip Erase operation will be ignored. Write Operation Status Detection The SST39SF020 device provides two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits : Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising edge of WE# which initiates the internal program or erase cycle. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling (DQ7) When the SST39SF020 device is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. The device is then ready for the next operation. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For sector or chip erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart. 2 326-10 12/98 2 Megabit Multi-Purpose Flash SST39SF020 Preliminary Specifications Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 0’s and 1’s, i.e., toggling between 0 and 1. The Toggle Bit will begin with “1”. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector or Chip Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. Data Protection The SST39SF020 device provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39SF020 provides the JEDEC approved software data protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up FUNCTIONAL BLOCK DIAGRAM OF SST39SF020 2,097,152 bit EEPROM Cell Array or power-down. Any Erase operation requires the inclusion of six byte load sequence. The SST39SF020 device is shipped with the software data protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. Product Identification The product identification mode identifies the device as the SST39SF020 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the SST39SF020 device. Users may wish to use the software product identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 10 for the software ID entry and read timing diagram and Figure 16 for the ID entry command sequence flowchart. TABLE 1: PRODUCT IDENTIFICATION TABLE Address Manufacturer’s Code Device Code 0000H 0001H Data BF H B6 H 326 PGM T1.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 11 for timing waveform and Figure 16 for a flowchart. X-Decoder A17 - A0 Address Buffers & Latches Y-Decoder CE# OE# WE# DQ7 - DQ0 326 ILL B1.3 15 16 Control Logic I/O Buffers and Data Latches © 1998 Silicon Storage Technology, Inc. 3 326-10 12/98 2 Megabit Multi-Purpose Flash SST39SF020 Preliminary Specifications A11 A9 A8 A13 A14 A17 WE# VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 326 ILL F01.0 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES (8mm x 14mm) WE# VCC A12 A15 A16 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 32-Pin 6 PDIP 7 8 Top View 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 A17 NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 32-Lead PLCC Top View 21 14 15 16 17 18 19 20 326 ILL F02.0 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PDIPS AND 32-LEAD PLCCS © 1998 Silicon Storage Technology, Inc. 4 326-10 12/98 2 Megabit Multi-Purpose Flash SST39SF020 Preliminary Specifications TABLE 2: PIN DESCRIPTION Symbol Pin Name A17-A0 Address Inputs DQ7-DQ0 Data Input/output Functions To provide memory addresses. During sector erase A17-A12 address lines will select the sector. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the write operations. To provide 5-volt supply (± 10%) Unconnected pins. 326 PGM T2.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CE# OE# WE# Vcc Vss NC Chip Enable Output Enable Write Enable Power Supply Ground No Connection TABLE 3: OPERATION MODES SELECTION Mode CE# OE# Read VIL VIL Program VIL VIH Erase VIL VIH Standby Write Inhibit Product Identification Hardware Mode Software Mode VIH X X VIL VIL X VIL X VIL VIL WE# VIH VIL VIL X X VIH VIH VIH A9 AIN AIN X X X X VH AIN DQ DOUT DIN X High Z High Z/DOUT High Z/DOUT Manufacturer Code (BF) Device Code (B6) ID Code Address AIN AIN Sector address, XXh for chip erase X X X A17 - A1 = VIL, A0 = VIL A17 - A1 = VIL, A0 = VIH See Table 4 326 PGM T3.4 © 1998 Silicon Storage Technology, Inc. 5 326-10 12/98 2 Megabit Multi-Purpose Flash SST39SF020 Preliminary Specifications TABLE 4: SOFTWARE COMMAND SEQUENCE 1st Bus Write Cycle Addr(1) Data Byte Program 5555H AAH Sector Erase 5555H AAH Chip Erase 5555H AAH Software ID Entry 5555H AAH Software ID Exit XXH F0H Software ID Exit 5555H AAH Notes: Address format A14-A0 (Hex), Addresses A15, A16 and A17 are a “Don’t Care” for the Command sequence. (2) SA for sector erase; uses A -A x 17 12 address lines (3) BA = Program Byte address (4) Both Software ID Exit operations are equivalent Notes for Software ID Entry Command Sequence 1. With A17 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0, SST39SF020 Device Code = B6H, is read with A0 = 1. 2. The device does not remain in Software Product ID Mode if powered down. (1) Command Sequence 2nd Bus Write Cycle Addr(1) Data 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 2AAAH 55H 3rd Bus Write Cycle Addr(1) Data 5555H A0H 5555H 80H 5555H 80H 5555H 90H 5555H F0H 4th Bus Write Cycle Addr(1) Data BA(3) Data 5555H AAH 5555H AAH 5th Bus Write Cycle Addr(1) Data 2AAAH 2AAAH 55H 55H 6th Bus Write Cycle Addr(1) Data SAx(2) 30H 5555H 10H 326 PGM T4.0 © 1998 Silicon Storage Technology, Inc. 6 326-10 12/98 2 Megabit Multi-Purpose Flash SST39SF020 Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C Storage Temperature ...................................................................................................................... -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V Transient Voltage (