74ACT02
QUAD 2-INPUT NOR GATE
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HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V
LOW POWER DISSIPATION:
ICC = 2µA(MAX.) at TA=25°C
COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.), V IL = 0.8V (MAX.)
50Ω TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 02
IMPROVED LATCH-UP IMMUNITY
DIP
TSSOP
ORDER CODES
DESCRIPTION
The 74ACT02 is an advanced high-speed CMOS
QUAD 2-INPUT NOR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS tecnology.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
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SOP
PACKAGE
TUBE
DIP
SOP
TSSOP
74ACT02B
74ACT02M
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T&R
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74ACT02MTR
74ACT02TTR
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with protection circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
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PIN CONNECTION AND IEC LOGIC SYMBOLS
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April 2001
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74ACT02
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL
2, 5, 8, 11
3, 6, 9, 12
1, 4, 10, 13
7
1A to 4A
1B to 4B
1Y to 4Y
GND
VCC
14
NAME AND FUNCTION
Data Inputs
Data Inputs
Data Outputs
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
A
B
Y
L
L
H
H
L
H
L
H
H
L
L
L
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
uc
Value
Supply Voltage
od
-0.5 to +7
VI
DC Input Voltage
VO
DC Output Voltage
IIK
DC Input Diode Current
IOK
DC Output Diode Current
IO
DC Output Current
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ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
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Unit
V
-0.5 to VCC + 0.5
-0.5 to VCC + 0.5
V
± 20
mA
± 20
mA
± 50
mA
± 200
mA
V
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
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Supply Voltage
Input Voltage
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VO
Output Voltage
Top
Operating Temperature
bs
dt/dv
Input Rise and Fall Time VCC = 4.5 to 5.5V (note 1)
1) VIN from 0.8V to 2.0V
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Parameter
Value
Unit
4.5 to 5.5
V
0 to VCC
V
0 to VCC
V
-55 to 125
°C
8
ns/V
74ACT02
DC SPECIFICATIONS
Test Condition
Symbol
Parameter
Value
TA = 25°C
VCC
(V)
Min.
Typ.
2.0
2.0
1.5
1.5
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Max.
VIH
High Level Input
Voltage
4.5
5.5
VO = 0.1 V or
VCC-0.1V
VIL
Low Level Input
Voltage
4.5
5.5
VO = 0.1 V or
VCC-0.1V
VOH
High Level Output
Voltage
4.5
IO=-50 µA
4.4
4.49
4.4
4.4
5.5
IO=-50 µA
5.4
5.49
5.4
5.4
4.5
IO=-24 mA
3.86
3.76
3.7
5.5
IO=-24 mA
4.86
4.76
4.7
4.5
IO=50 µA
0.001
0.1
0.1
0.1
5.5
IO=50 µA
0.001
0.1
0.1
0.1
4.5
IO=24 mA
0.36
0.44
5.5
IO=24 mA
0.36
0.44
5.5
VI = VCC or GND
± 0.1
±1
5.5
VI = VCC - 2.1V
VI = VCC or GND
VOL
Low Level Output
Voltage
II
ICCT
Input Leakage Current
Max ICC/Input
ICC
Quiescent Supply
Current
5.5
IOLD
Dynamic Output
Current (note 1, 2)
5.5
IOHD
2.0
2.0
1.5
1.5
2.0
2.0
0.8
0.8
0.8
0.8
1.5
P
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let
VOLD = 1.65 V max
VOHD = 3.85 V min
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0.8
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0.6
2
Unit
20
0.5
±1
µA
1.6
mA
40
µA
75
50
mA
-75
-50
mA
1) Maximum test duration 2ms, one output loaded at time
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50Ω
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
(s)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time
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VCC
(V)
ct
du
5.0(*)
Value
TA = 25°C
-40 to 85°C
-55 to 125°C
Min.
Typ.
Max.
Min.
Max.
Min.
Max.
1.5
5.0
8.0
1.0
11.0
1.0
11.0
Unit
ns
(*) Voltage range is 5.0V ± 0.5V
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CAPACITIVE CHARACTERISTICS
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Symbol
Parameter
Test Condition
TA = 25°C
VCC
(V)
CIN
Input Capacitance
5.0
CPD
Power Dissipation
Capacitance (note
1)
5.0
Value
Min.
fIN = 10MHz
Typ.
Max.
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
4
pF
47
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per gate)
3/8
74ACT02
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500W or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
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74ACT02
Plastic DIP-14 MECHANICAL DATA
mm
DIM.
MIN.
a1
0.51
B
1.39
TYP.
inch
MAX.
MIN.
TYP.
0.020
1.65
0.055
0.065
b
0.5
0.020
b1
0.25
0.010
D
20
0.787
E
8.5
0.335
e
2.54
0.100
e3
15.24
0.600
F
7.1
I
5.1
L
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3.3
Z
MAX.
1.27
2.54
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0.050
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0.280
0.201
0.130
0.100
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P001A
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74ACT02
SO-14 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
A
inch
MAX.
MIN.
TYP.
a1
1.75
0.1
0.068
0.2
a2
0.003
0.007
1.65
b
0.35
b1
0.19
C
MAX.
0.064
0.46
0.013
0.25
0.007
0.5
0.018
0.010
0.019
c1
45 (typ.)
D
8.55
8.75
0.336
E
5.8
6.2
0.228
e
1.27
e3
7.62
4.0
0.149
G
4.6
5.3
0.181
L
0.5
1.27
0.019
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0.68
S
8 (max.)
)
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0.300
3.8
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0.244
0.050
F
M
0.344
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P
0.157
0.208
0.050
0.026
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P013G
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74ACT02
TSSOP14 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
A
MAX.
MIN.
TYP.
MAX.
1.1
0.433
A1
0.05
0.10
0.15
0.002
0.004
0.006
A2
0.85
0.9
0.95
0.335
0.354
0.374
b
0.19
0.30
0.0075
0.0118
c
0.09
0.20
0.0035
0.0079
D
4.9
5
5.1
0.193
0.197
E
6.25
6.4
6.5
0.246
0.252
E1
4.3
4.4
4.48
0.169
0.173
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0.65 BSC
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0
L
0.50
o
A1
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4
8
0.60
0.70
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0.256
0.176
0.0256 BSC
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s
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ct
A2
A
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0.201
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0.020
K
c
4o
8o
0.024
0.028
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D
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PIN 1 IDENTIFICATION
1
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74ACT02
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2001 STMicroelectronics - Printed in Italy - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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