74LVC161284

74LVC161284 LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER s s HIGH SPEED: tPD = 9ns (MAX.) at VCC = 3V LOW POWER DISSIPATION: ICC=20µA (MAX) at VCC=3.6V TA=85°C TTL COMPATIBLE INPUTS VIH=2V (MIN) VIL=0.8(MAX) OPERATING VOLTAGE RANGE: VCC(OPR) = 3.0V to 3.6V A PORT HAVE STANDARD 4mA TOTEM POLE OUTPUT B PORT HIGH DRIVE SOURCE/SINK CAPABILITY OF 14mA SUPPORT IEEE STD 1284-I (LEVEL 1 TYPE) AND IEEE STD 1284-II (LEVEL 2 TYPE) FOR BIDIRECTIONAL PARALLEL COMMUNICATIONS BETWEEN PERSONAL COMPUTER ANT PRINTING PERIPHERALS TRANSLATION CAPABILITY ALLOW OUTPUTS ON CABLE SIDE TO INTERFACE WITH 5V SIGNAL PULL-UP RESISTOR INTEGRATED ON ALL OPEN-DRAIN OUTPUT ELIMINATE THE NEED FOR DISCRETE RESISTOR REPLACE THE FUNCTION OF TWO 74LVC1284 DEVICES ORDER CODES PACKAGE TSSOP TUBE T&R 74LVC161284TTR TSSOP s s s s s PIN CONNECTION s s s DESCRIPTION The 74LVC161284 contains eight high speed non inverting bidirectional buffers and eleven control/ status non-inverting buffers with open drain outputs fabricated in silicon gate C2MOS technology. It’s intended to provide a standard signaling method for a bi-direction parallel peripheral in an Extended Capabilities Port Mode (ECP). The HD (Active HIGH) input pin enables the Cable port to switch from Open Drain to a high drive totem pole output, capable of sourcing 14mA on all thirteen buffer and 84mA on PERI LOGIC OUTPUT buffer. The DIR input determines the direction of data flow on the bidirectional buffers. DIR (Active HIGH) enables data flow from A port to B port. DIR (Active LOW) enables data flow from B port to A port. It is available in the commercial temperature range. May 2003 1/11 74LVC161284 LOGIC DIAGRAM NOTE A: NOTE B: The PMOS transistors prevent backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND. The PMOS transistor is turned off when the associated driver is in the low state. The PMOS transistor prevents backdriving current from the signal pins to VCC/CABLE when VCC/CABLE is open or at GND. PIN DESCRIPTION PIN No 1 2, 3, 4, 5, 6 8, 9, 11, 12, 13, 14, 16, 17 19 20, 21, 22, 23 24 25 29, 28, 27, 26 30 41, 40, 38, 37, 36, 35, 33, 32 47, 46, 45, 44, 43 48 10, 15, 34, 39 7, 18 31, 42 SYMBOL HD A9 to A13 A1 to A8 PLI A14 to A17 HLO HLI C14 to C17 PLO B1 to B8 Y9 to Y13 DIR GND VCC VCC/CABLE NAME AND FUNCTION High Drive Enable Input Side A Input Side A Input or Output Peripheral Logic Input Side A Output Host Logic Output Host Logic Input Side Cable Output Peripheral Logic Output Side Cable Input or Output Side Cable Output Direction Control Input Ground (0V) Positive Supply Voltage Cable Power Supply 2/11 74LVC161284 TRUTH TABLE INPUT OUTPUT DIR L L H H HD L H L H B1-B8 Data to A1-A8 A9-A13 Data to Y9-Y13 C14-C17 Data to C14-C17 A1-A8 Data to B1-B8 A9-A13 Data to Y9-Y13 C14-C17 Data to C14-C17 Y9-Y13 and PLO Open Drain Y9-Y13 and PLO Totem Pole B1-B8 Y9-Y13 and PLO Open Drain B1-B8 Y9-Y13 and PLO Totem Pole OUTPUT ABSOLUTE MAXIMUM RATINGS Symbol VCC VCCcable VIA VIB VIBp VOA VOB VOBp IIK IOK IO Supply Voltage Cable Supply Voltage (must be ≥ VCC) DC Input Voltage A1-A13, PLIN, DIR, HDIN DC Input Voltage B1-B8, C14-C17, HLIN DC Input Voltage B1-B8, C14-C17, HLIN (40ns transient) DC Output Voltage A1-A8, A14-A17, HLIN DC Output Voltage B1-B8, Y9-Y13, PLIN DC Output Voltage B1-B8, Y9-Y13, PLIN (40ns transient) DC Input Diode Current DIR, HD A9-A13, PLIN C14-C17 DC Output Diode Current DC Output Current A1-A8, A14-A17, HLIN B1-B8, Y9-Y13, PLIN A1-A8, HLIN B1-B8, Y9-Y13 PLO = LOW PLO = HIGH ICC or IGND DC VCC or Ground Current per Supply Pin Tstg TL Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +4.6 -0.5 to +7.0 -0.5 to +VCC + 0.5 -0.5 to +5.5 -2 to +7 -0.5 to +VCC + 0.5 -0.5 to +5.5 -2 to +7 - 20 ± 50 - 50 ± 25 ± 50 84 -50 ± 200 -65 to +150 300 mA °C °C mA Unit V V V V V V V V mA mA Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not implied RECOMMENDED OPERATING CONDITIONS Symbol VCC VCCcable VI VO Top Supply Voltage Cable Supply Voltage Input Voltage Open Drain Output Voltage Operating Temperature Parameter Value 3.0 to 3.6 3.0 to 5.5 0 to VCC 0 to 5.5 -40 to 85 Unit V V V V °C 3/11 74LVC161284 DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) VCCcable (V) Value -40 to 85 °C Min. 2 2.3 3.0 to 3.6 3.0 to 5.5 2.6 0.8 0.8 1.6 3.0 3.0 3.0 3.0 3.15 3.0 3.0 3.0 3.0 3.0 3.0 3.6 3.6 All input except B or C ICC IOZ Quiescent Supply Current High Impedance Output Leakage Current Power Off Leakage Current Input Hysteresis Bn A1-A8 Open Drain Y Output B, Y output (to GND) B, Y output (to VCC) An, Bn, PLIN, DIR, HD Cn HLIN B1-B8, Y9-Y13 B1-B8, Y9-Y13, C14-C17 3.6 3.6 3.6 3.6 3.6 3.6 0 0 3.3 3.3 3.3 3.3 3.3 3.0 3.0 3.0 4.5 3.15 3.0 3.0 3.0 4.5 3.0 4.5 3.6 3.6 5.0 5.0 5.0 3.6 5.0 3.6 5.0 5.0 5.0 5.0 5.0 5.0 5.0 VB = VOH VB = VOH IO=-50µA IO=-4mA IO=-14mA IO=-14mA IO=-500µA IO=50µA IO=4mA IO=14mA IO=14mA IO=84mA IO=84mA VI = VCC VI=GND (Pull-up res) VI = VCC or GND VI = VCC IO=0 VI=GND (12xPull-up) VO = VCC VO=GND (Pull-up res) VO = VCC or GND VO=GND (Pull-up res) VI or VO = 0 to 7V VI or VO = 0 to 7V 0.4 0.8 0.2 30 1150 55 1650 Ω Ω V 2.8 2.4 2.0 2.23 3.1 0.2 0.4 0.8 0.77 0.95 0.90 50 -3.5 ±1 0.8 45 20 -3.5 ± 20 -3.5 100 10 µA mA µA mA µA mA µA mA µA µA V V V V Max. Unit VIH High Level Input Voltage An, Bn, PLIN, DIR, HD Cn HLIN An, Bn, PLIN, DIR, HD Cn HLIN VIL Low Level Input Voltage VOH High Level An, HL Output Voltage Bn, Yn Bn, Yn PL VOL Low Level An, HL Output Voltage Bn, Yn Bn, Yn PL PL II Input Current Cn IOFF Vhys ZO RP Output Impedance Pull-up Resistance 4/11 74LVC161284 AC ELECTRICAL CHARACTERISTICS Test Condition Symbol Parameter VCC (V) VCCcable (V) RL=500Ω CL=50pF 3.0 to 3.6 3.0 to 5.5 RL=500Ω CL=50pF RL=500Ω CL=50pF RL=500Ω CL=50pF 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 3.6 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 3.0 to 5.5 RL=500Ω CL=50pF RL=500Ω CL=50pF RL=500Ω CL=50pF RL=500Ω CL=50pF RL=500Ω CL=50pF RL=500Ω CL=50pF RPULL-UP=500Ω CL=50pF Value -40 to 85 °C Min. 1 1 1 1 1 1 1 1 1 1 Max. 7.5 9.0 7.0 11.0 12 8.5 8.5 8.5 8.5 120 ns ns ns ns ns ns ns ns ns ns Unit tPLH tPHL Propagation Delay Time A1-A8 to B1-B8, A9-A13 to Y9-Y13 B1-B8 to A1-A8, C14-C17 to A14-A17 PLIN to PLOUT HLIN to HLOUT DIR to A HD to Bn, Y9-Y13 DIR to A DIR to A HD to Bn, Y9-Y13 tPZH tPZL tPLZ tPHZ tr tf Enable Delay Time Disable Delay Time Rise and Fall Time B1-B8, Y9-Y13 Open Drain Output To Output Skew Time (note1, 2) tOSLH tOSHL 1 2 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn| 2) Parameter guaranteed by design CAPACITANCE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) VCC/CABLE (V) Value TA = 25 °C Min. Typ. 4 6 Max. pF pF Unit CIN Control Input Capacitance (HD, DIR, A9-A13, C14-C17, PLIN, HLIN) I/O Pin Capacitance Open 3.3 Open 5.0 CI/O 5/11 74LVC161284 TEST CIRCUIT TEST tPHL (A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLHIN to PLH) (see waveform 1) tPLH (A1-A8 to B1-B8, A9-A13 to Y9-Y13, PLHIN to PLH, HD to B1-B8, Y9-Y13, PLH) (see waveform 1) tPHL, tPLH (B1-B8 to A1-A8, C14-C17 to A14-A17, HLHIN to HLH) (see waveform 2) tr, tf (A1-A8 to B1-B8, A9-A13 to Y9-Y13) (see waveform 1) tPLZ (DIR to A1-A8) (see waveform 4) tPHZ (DIR to A1-A8) (see waveform 4) tPZL (DIR to A1-A8) (see waveform 3) tPZH (DIR to A1-A8) (see waveform 3) tPLZ (DIR to B1-B8) (see waveform 4) tPHZ (DIR to B1-B8) (see waveform 4) CL = 50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) S1 Open Open Open Open 6V Open 1.4V 4.4V 6V Open S2 VCC GND GND VCC GND GND GND GND GND GND S3 VCC GND GND GND GND GND GND GND GND GND WAVEFORM 1: PROPAGATION DELAY INPUT An TO OUTPUT (f=1MHz; 50% duty cycle) 6/11 74LVC161284 WAVEFORM 2: PROPAGATION DELAY INPUT Bn TO OUTPUT (f=1MHz; 50% duty cycle) VMO = 50%VCC WAVEFORM 3: DATA TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 7/11 74LVC161284 WAVEFORM 4: DIR TO OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 8/11 74LVC161284 TSSOP48 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.50 6.0 0.5 BSC 8˚ 0.75 0˚ 0.020 0.17 0.09 12.4 8.1 BSC 6.2 0.236 0.0197 BSC 8˚ 0.030 0.05 0.9 0.27 0.20 12.6 0.0067 0.0035 0.488 0.318 BSC 0.244 TYP MAX. 1.2 0.15 0.002 0.035 0.011 0.0079 0.496 MIN. TYP. MAX. 0.047 0.006 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 7065588C 9/11 74LVC161284 Tape & Reel TSSOP48 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 8.7 13.1 1.5 3.9 11.9 12.8 20.2 60 30.4 8.9 13.3 1.7 4.1 12.1 0.343 0.516 0.059 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.350 0.524 0.067 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch 10/11 74LVC161284 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 11/11