74LVC374AMTR

74LVC374A OCTAL D-TYPE FLIP-FLOP HIGH PERFORMANCE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V SOP Table 1: Order Codes t c u d o r P e t e l o s b O July 2004 t e l o T&R 74LVC374AMTR 74LVC374ATTR s b O While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. The Output control does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ) (s DESCRIPTION The 74LVC374A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type latch are controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. Figure 1: Pin Connection And IEC Logic Symbols u d o r P e PACKAGE SOP TSSOP ) s ( ct TSSOP Rev. 2 1/14 74LVC374A Figure 2: Input And Output Equivalent Circuit ) s ( ct u d o r P e Table 2: Pin Description t e l o PIN N° SYMBOL NAME AND FUNCTION 1 2, 5, 6, 9, 12, 15, 16,19 3, 4, 7, 8, 13, 14, 17, 18 11 10 20 OE Q0 to Q7 D0 to D7 CK GND VCC 3 State Output Enable Input (Active LOW) 3-State Outputs Data Inputs Clock Ground (0V) Positive Supply Voltage t c u ) (s Table 3: Truth Table s b O INPUTS d o r OE P e H t e l o L L s b O L X : Don’t Care Z :High Impedance 2/14 OUTPUT CK D Q X X Z X NO CHANGE L L H H 74LVC374A Table 4: Absolute Maximum Ratings Symbol VCC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (VCC = 0V) -0.5 to +7.0 V VO DC Output Voltage (High or Low State) (note 1) IIK DC Input Diode Current IOK IO -0.5 to VCC + 0.5 V - 50 mA DC Output Diode Current (note 2) - 50 mA DC Output Current ± 50 mA ± 100 ICC or IGND DC VCC or Ground Current per Supply Pin Tstg Storage Temperature TL Lead Temperature (10 sec) ) s ( ct mA -65 to +150 300 °C °C u d o Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND r P e Table 5: Recommended Operating Conditions Symbol VCC t e l o Parameter bs Supply Voltage (note 1) VI Input Voltage VO Output Voltage (VCC = 0V) VO Output Voltage (High or Low State) ) s ( ct -O Value Unit 1.65 to 3.6 V 0 to 5.5 V 0 to 5.5 V 0 to VCC V IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) ± 24 mA IOH, IOL High or Low Level Output Current (VCC = 2.7 to 3.0V) ± 12 mA IOH, IOL High or Low Level Output Current (VCC = 2.3 to 2.7V) ±8 mA IOH, IOL High or Low Level Output Current (VCC = 1.65 to 2.3V) ±4 mA Top dt/dv o r P du Operating Temperature Input Rise and Fall Time (note 2) e t e ol -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VI from 0.8V to 2V at VCC = 3.0V s b O 3/14 74LVC374A Table 6: DC Specifications Test Condition Symbol VIH VIL VOH VOL II Ioff IOZ ICC ∆ICC Parameter Value -40 to 85 °C -55 to 125 °C VCC (V) Min. High Level Input Voltage 1.65 to 1.95 0.65VCC 0.65VCC 2.3 to 2.7 2.7 to 3.6 1.7 2 1.7 2 Low Level Input Voltage 1.65 to 1.95 0.35VCC 0.35VCC 2.3 to 2.7 2.7 to 3.6 0.7 0.8 0.7 0.8 High Level Output Voltage 1.65 to 3.6 IO=-100 µA VCC-0.2 VCC-0.2 1.65 IO=-4 mA 1.2 1.2 2.3 IO=-8 mA 1.7 1.7 2.7 IO=-12 mA 2.2 2.2 3.0 IO=-18 mA 2.4 3.0 IO=-24 mA 2.2 1.65 to 3.6 IO=100 µA 1.65 IO=4 mA 2.3 IO=8 mA 2.7 IO=12 mA 3.0 IO=24 mA 3.6 VI = 0 to 5.5V Low Level Output Voltage Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ete o r P ol ICC incr. per Input s b O du 3.6 2.7 to 3.6 Min. let o s b 0.45 Max. V V ) s ( ct u d o r P e 2.4 0.2 V 2.2 0.2 0.45 0.7 0.7 0.4 0.4 0.55 0.55 ±5 ±5 µA VI or VO = 5.5V 10 10 µA VI = VIH or VIL VO = 0 to 5.5V ± 10 ± 10 µA VI = VCC or GND 10 10 VI or VO = 3.6 to 5.5V VIH = VCC-0.6V ± 10 ± 10 500 500 (s) -O ct 0 3.6 Max. Unit V µA µA Table 7: Dynamic Switching Characteristics Symbol VOLP VOLV Test Condition Parameter Dynamic Low Level Quiet Output (note 1) TA = 25 °C VCC (V) 3.3 Value Min. CL = 50pF VIL = 0V, VIH = 3.3V Typ. 0.8 -0.8 Unit Max. V 1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 4/14 74LVC374A Table 8: AC Electrical Characteristics Test Condition Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tW ts th tOSLH tOSHL Parameter VCC (V) Propagation Delay Time D to Q 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Propagation Delay 1.65 to 1.95 Time LE to Q 2.3 to 2.7 2.7 3.0 to 3.6 Output Enable Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Output Disable Time 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 LE Pulse Width 1.65 to 1.95 HIGH 2.3 to 2.7 2.7 3.0 to 3.6 Setup Time D to LE 1.65 to 1.95 (HIGH to LOW) 2.3 to 2.7 2.7 3.0 to 3.6 Hold Time D to 1.65 to 1.95 CLOCK, HIGH or 2.3 to 2.7 LOW 2.7 3.0 to 3.6 Output To Output 2.7 to 3.6 Skew Time (note1, 2) CL (pF) RL (Ω) ts = t r (ns) 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 ) (s t c u d o r P e t e l o Value -40 to 85 °C Min. 1.5 1 1.5 1 1 1 -55 to 125 °C Max. TBD TBD 7.8 6.8 TBD TBD 7.8 6.8 TBD TBD 8.7 7.7 TBD TBD 7.6 7.0 Min. 1.5 1 s b O 2 2 TBD TBD 3.3 3.3 TDB TBD 2 2 TBD TBD 1.5 1.5 1 s b O TBD TBD 9.4 8.2 TBD TBD 9.4 8.2 TBD TBD 10.4 9.2 TBD TBD 9.1 8.4 ns ) s ( ct u d o r P e t e l o 2 2 TBD TBD 3.3 3.3 TBD TBD 2 2 TBD TBD 1.5 1.5 Max. 1.5 1 1 1 Unit ns ns ns ns ns ns 1 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn| 2) Parameter guaranteed by design Table 9: Capacitive Characteristics Test Condition Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (note 1) TA = 25 °C VCC (V) 1.8 2.5 3.3 Value Min. fIN = 10MHz Typ. Unit Max. 4 pF 28 30 34 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) 5/14 74LVC374A Figure 3: Test Circuit ) s ( ct u d o r P e RT = ZOUT of pulse generator (typically 50Ω) Table 10: Test Circuit And Waveform Symbol Value 1.65 to 1.95V 2.3 to 2.7V 30pF 30pF CL O ) bs 2.7V 3.0 to 3.6V 50pF 50pF RL = R1 1000Ω 500Ω 500Ω 500Ω VS 2 x VCC 2 x VCC 6V 7V VIH VCC VCC 2.7V 3.0V VCC/2 1.5V 1.5V VCC 3.0V 3.5V s ( t c VM VCC/2 VOH VCC VX VOL + 0.15V VOL + 0.15V VOL + 0.3V VOL + 0.3V VY VOH - 0.15V VOH - 0.15V VOH - 0.3V VOH - 0.3V