74LVX74TTR

74LVX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR (5V TOLERANT INPUTS) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 145MHz (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V AT VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 IMPROVED LATCH-UP IMMUNITY POWER DOWN PROTECTION ON INPUTS DESCRIPTION The 74LVX74 is a low voltage CMOS DUAL D-TYPE FLIP-FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications. SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LVX74M 74LVX74MTR 74LVX74TTR A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V system. It combines high speed performance with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 74LVX74 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 13 1CLR, 2CLR 2, 12 3, 11 1D, 2D 1CK, 2CK 4, 10 1PR, 2PR 5, 9 6, 8 1Q, 2Q 1Q, 2Q 7 14 GND VCC NAME AND FUNCTION Asynchronous Reset Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR D CK Q Q L H L H L L X X X X X X L H H H L H H H L L H H H H H L H H X Qn Qn X : Don’t Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 CLEAR PRESET NO CHANGE 74LVX74 ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage -0.5 to VCC + 0.5 V IIK DC Input Diode Current - 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ICC or IGND DC VCC or Ground Current Tstg Storage Temperature TL Lead Temperature (10 sec) ± 25 mA ± 50 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. RECOMMENDED OPERATING CONDITIONS Symbol V CC Parameter Value Unit Supply Voltage (note 1) 2 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage Top Operating Temperature dt/dv Input Rise and Fall Time (note 2) (VCC = 3.3V) 0 to VCC V -55 to 125 °C 0 to 100 ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2.0V DC SPECIFICATIONS Test Condition Symbol VIH V IL VOH VOL II ICC Parameter Value TA = 25°C VCC (V) Min. Typ. Max. -40 to 85°C -55 to 125°C Min. Min. Max. High Level Input Voltage 2.0 3.0 1.5 2.0 1.5 2.0 1.5 2.0 2.4 2.4 2.4 Low Level Input Voltage 3.6 2.0 3.0 3.6 High Level Output Voltage Low Level Output Voltage Input Leakage Current Quiescent Supply Current 0.5 0.8 0.8 0.5 0.8 0.8 IO=-50 µA 1.9 2.0 1.9 1.9 3.0 IO=-50 µA 2.9 3.0 2.9 2.9 3.0 IO=-4 mA 2.58 2.0 IO=50 µA 0.0 0.0 2.48 0.1 Max. V 0.5 0.8 0.8 2.0 Unit V V 2.4 0.1 0.1 3.0 IO=50 µA 0.1 0.1 0.1 3.0 IO=4 mA 0.36 0.44 0.55 3.6 VI = 5V or GND ± 0.1 ±1 ±1 µA 3.6 VI = VCC or GND 2 20 20 µA V 3/11 74LVX74 DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP V OLV V IHD VILD Parameter Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) Value TA = 25°C VCC (V) Min. 3.3 -0.5 3.3 Typ. Max. 0.3 0.5 -55 to 125°C Min. Min. Max. Unit Max. -0.3 2 C L = 50 pF 3.3 -40 to 85°C V 0.8 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. 4/11 74LVX74 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3ns) Test Condition Symbol Parameter tPLH tPHL Propagation Delay Time CK to Q or Q tPLH tPHL Propagation Delay Time PR or CLR to Q or Q tw tw(L) ts th tREM fMAX tOSLH tOSHL Minimum Pulse Width HIGH or LOW, CK Minimum Pulse Width LOW PR or CLR Minimum Setup Time D to CK HIGH or LOW Minimum Hold Time D to CK HIGH or LOW Minimum Removal Time PR or CLR to CK Maximum Clock Frequency Output To Output Skew Time (note1, 2) VCC (V) CL (pF) 2.7 2.7 Value TA = 25°C -55 to 125°C Typ. Max. Min. Max. Min. Max. 15 50 7.3 9.8 15.0 18.5 1.0 1.0 18.5 22.0 1.0 1.0 18.5 22.0 3.3 (*) 15 5.7 9.7 1.0 11.5 1.0 11.5 3.3 (*) 2.7 2.7 50 8.2 13.2 1.0 15.0 1.0 15.0 15 50 8.4 10.9 15.6 19.1 1.0 1.0 18.5 22.0 1.0 1.0 18.5 22.0 3.3 (*) 15 6.6 10.1 1.0 12.0 1.0 12.0 3.3 (*) 2.7 50 9.1 13.6 1.0 15.5 1.0 15.5 3.3 50 (*) 50 2.7 3.3 Min. -40 to 85°C 50 (*) 50 2.7 50 3.3 (*) 50 2.7 50 3.3 (*) 50 ns 10.0 7.0 10.0 7.0 ns 8.5 6.0 10.0 7.0 10.0 7.0 ns 8.0 5.5 9.5 6.5 9.5 6.5 ns 0.5 0.5 0.5 0.5 0.5 0.5 ns 6.5 5.0 7.5 5.0 7.5 5.0 ns 2.7 50 50 2.7 2.7 15 50 55 45 135 60 50 40 50 40 3.3 (*) 15 95 145 80 80 3.3 (*) 2.7 50 60 85 50 50 3.3 (*) 50 0.5 0.5 ns 8.5 6.0 3.3 (*) 50 Unit 1.0 1.0 1.5 1.5 MHz 1.5 1.5 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V ± 0.3V CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter TA = 25°C VCC (V) CIN Input Capacitance 3.3 C PD Power Dissipation Capacitance (note 1) 3.3 Value Min. fIN = 10 MHz Typ. Max. 4 10 25 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per circuit) 5/11 74LVX74 TEST CIRCUIT C L =15/50pF or equivalent (includes jig and probe capacitance) R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74LVX74 WAVEFORM 2 : PROPAGATION DELAYS, MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle) WAVEFORM 3 : RECOVERY TIME (f=1MHz; 50% duty cycle) 7/11 74LVX74 WAVEFORM 4 : MINIMUM PULSE WIDTH 8/11 74LVX74 SO-14 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8° (max.) PO13G 9/11 74LVX74 TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.60 0.0256 BSC 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 10/11 74LVX74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. STMicroelectronics prod ucts are not authori zed for use as critical components in life suppo rt devices or systems without express written approval of STMicroelectronics.  The ST logo is a registered trademark of STMicroelectronics  2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Swit zerland - United Kingdom  http://w ww.st.com 11/11 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.