74VHCT257A

74VHCT257A QUAD 2 CHANNEL MULTIPLEXER (3-STATE) s s s s s s s s s s HIGH SPEED: tPD = 4.8 ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 257 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.8V (MAX.) SOP TSSOP Table 1: Order Codes PACKAGE SOP TSSOP T&R 74VHCT257AMTR 74VHCT257ATTR DESCRIPTION The 74VHCT257A is an advanced high-speed CMOS QUAD 2-CHANNEL MULTIPLEXER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is composed of four independent 2-channel multiplexers with common SELECT and ENABLE INPUT(OE). The VHCT257A is a non-inverting multiplexer. When the ENABLE INPUT is held "High", all outputs become high impedance state. Figure 1: Pin Connection And IEC Logic Symbols If SELECT INPUT is held "Low", "A" data is selected, when SELECT INPUT is "High", "B" data is chosen. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. December 2004 Rev. 3 1/13 74VHCT257A Figure 2: Input Equivalent Circuit Table 2: Pin Description PIN N° 1 2, 5, 11, 14 3, 6, 10, 13 4, 7, 9, 12 15 8 16 SYMBOL SELECT 1A to 4A 1B to 4B 1Y to 4Y OE GND VCC NAME AND FUNCTION Common Data Select Inputs Data Inputs From Source A Data Inputs From Source B 3 State Multiplexer Outputs 3 State Output Enable Inputs (Active LOW) Ground (0V) Positive Supply Voltage Table 3: Truth Table INPUTS OE H L L L L X: Don’t Care Z: High Impedance OUTPUT A X L H X X B X X X L H Y Z L H L H SELECT X L L H H Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays 2/13 74VHCT257A Table 4: Absolute Maximum Ratings Symbol VCC VI VO VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 ± 20 ± 25 ± 50 -65 to +150 300 Unit V V V V mA mA mA mA °C °C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) Output in OFF State 2) High or Low State Table 5: Recommended Operating Conditions Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (VCC = 5.0 ± 0.5V) Parameter Value 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 20 Unit V V V V °C ns/V 1) Output in OFF State 2) High or Low State 3) VIN from 0.8V to 2V 3/13 74VHCT257A Table 6: DC Specifications Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 0 to 5.5 5.5 5.5 0 IO=-50 µA IO=-8 mA IO=50 µA IO=8 mA VI = VIH or VIL VO = 0V to 5.5V VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V TA = 25°C Min. 2 0.8 4.4 3.94 0.0 0.1 0.36 ±0.25 ± 0.1 4 1.35 0.5 4.5 4.4 3.8 0.1 0.44 ± 2.5 ± 1.0 40 1.5 5.0 Typ. Max. Value -40 to 85°C Min. 2 0.8 4.4 3.7 0.1 0.55 ± 2.5 ± 1.0 40 1.5 5.0 Max. -55 to 125°C Min. 2 0.8 Max. V V V V µA µA µA mA µA Unit VIH VIL VOH VOL IOZ High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current II ICC +ICC IOPD Table 7: AC Electrical Characteristics (Input tr = tf = 3ns) Test Condition Symbol Parameter VCC (*) CL (V) (pF) 5.0 5.0 5.0 5.0 5.0 5.0 5.0 15 50 15 50 15 50 50 TA = 25°C Min. Typ. 4.8 5.5 6.0 7.0 5.8 6.5 5.7 Max. 7.0 8.0 6.8 8.8 6.8 8.8 7.9 Value -40 to 85°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 8.0 9.0 8.0 10.0 8.0 10.0 9.0 -55 to 125°C Min. 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max. 8.0 9.0 8.0 10.0 8.0 10.0 9.0 ns ns ns ns Unit tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ Propagation Delay Time A, B, to Y Propagation Delay Time SELECT to Y Output Enable Time Output Disable Time (*) Voltage range is 5.0V ± 0.5V 4/13 74VHCT257A Table 8: Capacitive Characteristics Test Condition Symbol Parameter TA = 25°C Min. CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) Typ. 4 6 23 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF pF Unit 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/4 (per Channel) Table 9: Dynamic Switching Characteristics Test Condition Symbol Parameter VCC (V) 5.0 TA = 25°C Min. Typ. 0.3 -0.8 CL = 50 pF 2.0 -0.3 V Max. 0.8 Value -40 to 85°C Min. Max. -55 to 125°C Min. Max. Unit VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 5.0 0.8 1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz. 5/13 74VHCT257A Figure 4: Test Circuit TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL =15/ 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) SWITCH Open VCC GND Figure 5: Waveform - Propagation Delays For Inverting Conditions (f=1MHz; 50% duty cycle) 6/13 74VHCT257A Figure 6: Waveform - Propagation Delays For Non-inverting Conditions (f=1MHz; 50% duty cycle) Figure 7: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle) 7/13 74VHCT257A SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.25 1.64 0.46 0.25 0.013 0.007 0.019 0.004 MIN. inch TYP. MAX. 0.068 0.010 0.063 0.018 0.010 0016020D 8/13 74VHCT257A TSSOP16 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0˚ 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8˚ 0.75 0˚ 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8˚ 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 9/13 74VHCT257A Tape & Reel SO-16 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.45 10.3 2.1 3.9 7.9 12.8 20.2 60 22.4 6.65 10.5 2.3 4.1 8.1 0.254 0.406 0.082 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.262 0.414 0.090 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 10/13 74VHCT257A Tape & Reel TSSOP16 MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.7 5.3 1.6 3.9 7.9 12.8 20.2 60 22.4 6.9 5.5 1.8 4.1 8.1 0.264 0.209 0.063 0.153 0.311 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.272 0.217 0.071 0.161 0.319 MIN. TYP. MAX. 12.992 0.519 inch 11/13 74VHCT257A Table 10: Revision History Date 16-Dec-2004 Revision 3 Description of Changes Order Codes Revision - pag. 1. 12/13 74VHCT257A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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