A6902D

A6902D Up to 1 A step down switching regulator with adjustable current limit for automotive applications Features S O-8 • • • • • • • • • • • Qualified following the AEC-Q100 requirements Up to 1 A DC output current Operating input voltage from 8 V to 36 V Output voltage adjustable from 1.235 V to 35 V Precise 3.3 V (±2 %) reference voltage 250 kHz Internally fixed frequency Voltage feedforward Zero-load current operation Internal current limiting Protection against feedback disconnection Thermal shutdown Maturity status link A6902D Applications • • • Automotive applications Adjustable current generator Simple step-down converters with adjustable current limit Description The A6902D is a complete step down switching regulator with adjustable current limit. Based on a voltage mode structure it integrates an additional current error amplifier to implement both a constant voltage and constant current control. The current limit programming is very simple and accurate (± 5%) selecting the proper sensing resistor. The DC-DC converter can be used either as a voltage source with adjustable current limit (set by using the external sense resistor) or as current source to charge NiMH / NiCd batteries or drive voltage load like LEDs. The internal P-Channel DMOS transistor (typ. RDSON 250 mΩ) assures high efficiency and minimum dropout even at high output current level. DS5503 - Rev 7 - June 2022 For further information contact your local STMicroelectronics sales office. www.st.com A6902D Pin description 1 Pin description Figure 1. Pin connection (top view) OUT 1 8 VCC CS+ 2 7 GND CS- 3 6 VREF COMP 4 5 FB Table 1. Pin description DS5503 - Rev 7 Pin n° Name Description 1 OUT Regulator output. 2 CS+ Current error amplifier input (current sense at higher voltage) 3 CS- Current error amplifier input (current sense at lower voltage) 4 COMP 5 FB 6 VREF 3.3 V reference voltage. No cap is need for stability. 7 GND Ground. 8 VCC Unregulated DC input voltage. E/A output for frequency compensation. Feedback input. Connecting directly to this pin results in an output voltage of 1.23 V. An extenal resistive divider is required for higher output voltages. page 2/33 A6902D Absolute maximum ratings 2 Absolute maximum ratings Stressing the device above the rating listed in the table below may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 2. Maximum ratings Symbol V8 V1 I1 Parameter Min. Max. Unit -0.3 40 V OUT pin DC voltage -1 40 OUT pin peak voltage at Δt = 0.1 μs -5 40 Input voltage Maximum output current V int. limit. V4, V5 Analog pins -0.3 4 V V2, V3 Analog pins -0.3 VCC V PTOT Power dissipation at TA ≤ 70 °C 0.7 W TJ TSTG Operating junction temperature range -40 150 °C Storage temperature range -55 150 °C Table 3. Thermal data DS5503 - Rev 7 Symbol Parameter SO-8 Unit RthJA Thermal resistance junction to ambient (device soldered on a standard demonstration board) 110 °C/W page 3/33 A6902D Electrical characteristics 3 Electrical characteristics TJ = -40 to 125 °C, VCC = 12 V, unless otherwise specified. Table 4. Electrical characteristics Symbol VCC RDS(on) IL fSW Parameter Test conditions Operating input voltage range V0 = 1.235 V; I0 = 2 A Min. Max. Unit 36 V 0.250 0.5 Ω 1.8 2.5 3.2 2 2.5 3.2 212 250 280 kHz 100 % 1.272 V 8 MOSFET on resistance Maximum limiting current VCC = 8.5 V (1) VCC = 8.5 V, TJ = 25 °C Switching frequency Duty cycle Typ. 0 A Dynamic characteristics (see test circuit) V5 η Voltage feedback 8 V < VCC < 36 V; 20 mA < I0 < 1 A Efficiency V0 = 5 V, VCC = 12 V 1.198 1.235 90 % DC characteristics Iqop Iq Total operating quiescent current Quiescent current 3 Duty cycle = 0; VFB = 1.5 V 5 mA 2.7 mA Error amplifier VOH High level output voltage VFB = 1 V VOL Low level output voltage VFB = 1.5 V Source output current VCOMP = 1.9 V; VFB = 1 V Io sink Sink output current VCOMP = 1.9 V; VFB = 1.5 V Ib Source bias current Io source DC open loop gain gm Transconductance VOFFS Input offset voltage ICS+ CS+ output current ICS- CS- output current 3.6 V 0.4 160 300 μA 1 1.5 mA 2.5 RL = ∞ 50 ICOMP = -0.1 mA to 0.1 mA; VCOMP = 1.9 V VCS- = 1.8 V; VCS+ = Vcomp V 90 I0 =1 A; RSENSE= 100 mΩ; VOUT < VCC - 2 V I0 = 1 A; RSENSE = 100 mΩ; VOUT < VCC - 2 V 4 μA 58 dB 2.3 mS 100 110 mV 1.5 3 μA 1.5 3 μA 3.3 3.399 V Reference section Reference voltage IREF = 0 to 5 mA; VCC = 8 V to 36 V Line regulation IREF = 0 mA; VCC = 8 V to 36 V 5 10 mV Load regulation IREF = 0 to 5 mA 8 15 mV 18 35 mA Short circuit current 3.2 5 1. With TJ = 85 °C, Ilim_min = 2 A, assured by design, characterization and statistical correlation. DS5503 - Rev 7 page 4/33 A6902D Datasheet parameters over the temperature range 4 Datasheet parameters over the temperature range The 100% of the population in the production flow is tested at three different ambient temperatures (-40 °C; +25 °C, +125 °C) to guarantee the datasheet parameters inside the junction temperature range (-40 °C; +125 °C). The device operation is so guaranteed when the junction temperature is inside the (-40 °C; +150 °C) temperature range. The designer can estimate the silicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation (please refer to the Section 8.4 Thermal considerations). However the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the TSHTDWN (+150 °C ± 10 °C) temperature. All the datasheet parameters can be guaranteed to a maximum junction temperature of +125 °C to avoid triggering the thermal shutdown protection during the testing phase because of self-heating. DS5503 - Rev 7 page 5/33 A6902D Functional description 5 Functional description The main internal blocks are shown in the device block diagram in figure below. • • • • • • • • • • A voltage regulator supplying the internal circuitry. A voltage monitor circuit checks the input and the internal voltages. A fully integrated sawtooth oscillator with a frequency of 250 kHz ± 15 %, including also the voltage feed forward function. Two embedded current limitation circuits which control the current that flows through the power switch. The pulse-by-pulse current limit forces the power switch OFF cycle by cycle if the current reaches an internal threshold, while the frequency shifter reduces the switching frequency in order to significantly reduce the duty cycle. A transconductance error amplifier for output voltage regulation. A transconductance error amplifier for adjustable constant current operation. A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive the internal power. A high side driver for the internal P-MOS switch. An inhibit block for stand-by operation. A circuit to implement the thermal protection function. Figure 2. Block diagram VCC VOLTAGES MONITOR SUPPLY Current E/A CS+ CS- + THERMAL SHUTDOWN - 1.235V 3.5V VREF BUFFER VREF PEAK TO PEAK CURRENT LIMIT COMP Voltage E/A FB + 1.235V DRIVER + PWM - D Q Q OSCILLATOR FREQUENCY SHIFTER GND 5.1 PDMOS POWER OUT Power supply and voltage reference The internal regulator circuit (shown in Figure 3. Internal circuit) consists of a start-up circuit, an internal voltage pre-regulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks. The pre-regulator block supplies the Bandgap cell with a pre-regulated voltage VREG that has a very low supply voltage noise sensitivity. DS5503 - Rev 7 page 6/33 A6902D Voltage monitors 5.2 Voltage monitors An internal block continuously senses the VCC, VREF and VBG. If the voltages go higher than their thresholds, the regulator begins operating. There is also an hysteresis on the VCC (UVLO). Figure 3. Internal circuit VCC STARTER PREREGULATOR VREG BANDGAP IC BIAS VREF 5.3 Oscillator Figure below shows the block diagram of the oscillator circuit. The clock generator provides the switching frequency of the device, which is internally fixed at 250 kHz. The frequency shifter block acts to reduce the switching frequency in case of strong overcurrent or short circuit. The clock signal is then used in the internal logic circuitry and is the input of the ramp generator. The ramp generator circuit provides the sawtooth signal, used for PWM control and the internal voltage feedforward. Figure 4. Oscillator circuit block diagram FREQUENCY SHIFTER CLOCK GENERATOR 5.4 CLOCK RAMP GENERATOR RAMP Current protection The A6902D features different current protections: DS5503 - Rev 7 page 7/33 A6902D Error amplifiers • • An inner current loop, composed by the transconductance current error amplifier and the sensing resistor, that implements a precise switching current source regulating an adjustable real average current. This operation regulates 100 mV across the sensing resistor and it requires a small signal stability analysis to design the system bandwidth / phase margin (see Section 7 Closing the loop). The maximum bandwidth is fSW / 5 = 50 kHz for a valid small analysis so the minimum time to react to an external load transient is about five switching cycles. A second level “pulse by pulse” current protection, sensing the current flowing in the embedded power element. This protection is faster than the previous as it can disable the power element with negligible delay when the over current comparator is triggered during the power element conduction time. However, due to the noise created by the switching activity of the power MOSFETs, the current sense is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as “masking time” or “blanking time” (270 ns typ.). The current threshold of the over-current comparator is given in Table 4. Electrical characteristics. Both of the protections implement a constant current strategy as the device limits the output current. The Constant Current Loop, called CCL (see Section 7.2.2 Constant current loop), is adjustable and precise but slower than the embedded Over Current Protection called “OCP” (see Section 6.2 OCP protection), which is very fast but with fixed and spreaded current threshold over the population. The OCP protects the device and external load in case of fast and unexpected line / load transient like a short circuit event. 5.5 Error amplifiers The current outputs of the two internal error amplifiers are ORed and compared to the oscillator saw tooth to perform PWM control (voltage mode structure). A compensation network valid for both voltage and current loop is shared in the COMP pin to achieve adequate phase margin. 5.5.1 Voltage loop The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (1.235 V) and the inverting input (FB) is connected to the external divider or directly to the output voltage. The uncompensated error amplifier has the following characteristics: Table 5. Uncompensated voltage error amplifier characteristics 5.5.2 Description Value Transconductance 2300 µS Low frequency gain 70 dB Minimum sink/source current 1500 µA / 300 µA Output voltage swing 0.4 V / 3.65 V Input bias current 2.5 µA Constant current loop The current error amplifier is a transconductance operational amplifier with a typical offset equal to 100 mV which directly senses the voltage across the sensing resistor. The uncompensated current error amplifier has the following characteristics. Table 6. Uncompensated voltage error amplifier characteristics DS5503 - Rev 7 Description Value Transconductance 1900 µS Low frequency gain 60 dB Minimum sink/source current 1500 µA / 300 µA Output voltage swing 0.4 V / 3.65 V page 8/33 A6902D PWM comparator and power stage 5.6 PWM comparator and power stage This block compares the oscillator saw tooth and the error amplifier output signals to generate the PWM signal for the driving stage. The power stage is a highly critical block, as it functions to guarantee a correct turn ON and turn OFF of the PDMOS. The turn ON of the power element, or more accurately, the rise time of the current at turn ON, is a very critical parameter. At a first approach, it appears that the faster the rise time, the lower the turn ON losses. However, there is a limit introduced by the recovery time of the recirculation diode. In fact, when the current of the power element is equal to the inductor current, the diode turns OFF and the drain of the PDMOS is able to go high. But during its recovery time, the diode can be considered a high value capacitor and this produces a very high peak current, responsible for numerous problems: • • • • Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasites. Turn ON overcurrent leads to a decrease in the efficiency and system reliability. Major EMI problems. Shorter freewheeling diode life. The fall time of the current during turn OFF is also critical, as it produces voltage spikes (due to the parasites elements of the board) that increase the voltage drop across the PDMOS. In order to minimize these problems, a new driving circuit topology has been used and the block diagram is shown in figure below. The basic idea is to change the current levels used to turn the power switch ON and OFF, based on the PDMOS and the gate clamp status. This circuitry allows the power switch to be turned OFF and ON quickly and addresses the freewheeling diode recovery time problem. The gate clamp is necessary to ensure that VGS of the internal switch does not go higher than VGSmax. The ON/OFF Control block protects against any cross conduction between the supply line and ground. Figure 5. Driving circuitry VCC IOFF VgsMAX GATE CLAMP STOP DRIVE DRAIN 5.7 PDMOS ON/OFF CONTROL ON L OUT OFF ION VOUT D COUT ILOAD Thermal shutdown The shutdown block generates a signal that turns OFF the power stage if the temperature of the chip goes higher than a fixed internal threshold (150 ± 10 °C). The sensing element of the chip is very close to the PDMOS area, ensuring fast and accurate temperature detection. A hysteresis of approximately 20 °C keeps the device from turning ON and OFF continuously. DS5503 - Rev 7 page 9/33 A6902D Additional features and protection 6 Additional features and protection 6.1 Feedback disconnection If the feedback is disconnected, the duty cycle increases towards the maximum allowed value, bringing the output voltage close to the input supply. This condition could destroy the load. To avoid this hazardous condition, the device is turned OFF if the feedback pin is left floating. 6.2 OCP protection The OCP features two types of current limit protections: pulse-by-pulse and frequency foldback. The schematic of the current limitation circuitry for the pulse-by-pulse protection is shown in figure below. The output power PDMOS transistor is split into two parallel PDMOS transistors. The smallest one includes a resistor in series, RSENSE. The current is sensed through RSENSE and if it reaches the threshold, the mirror becomes unbalanced and the PDMOS is switched off until the next falling edge of the internal clock pulse. Due to this reduction of the ON time, the output voltage decreases. The frequency shifter function is enabled by the overcurrent event and it skips up to three switching pulses depending on the feedback voltage. In strong overcurrent conditions the device can reduce the switching frequency down to 1/3 of the nominal 250 kHz to keep the switch current limited. Figure 6. Current limit circuitry VCC RSENSE A1 RTH A2 IL DRIVER NOT OUT A1/A2=95 I I PWM In overcurrent protection mode, when the peak current reaches the current limit, the device reduces the TON down to its minimum value (approximately 250 ns) and the switching frequency to approximately one third of its nominal value even when synchronized to an external signal. In these conditions, the duty cycle is strongly reduced and, in most applications, this is enough to limit the current to ILIM. In any event, in case of heavy shortcircuit at the output (VOUT = 0 V) and depending on the application conditions (Vcc value and parasitic effect of external components) the current peak could reach values higher than ILIM. This can be understood considering the inductor current ripple during the ON and OFF phases: • ON phase (1) V − VOUT − DCRL + RDSON ∙ IL ∆ IL, TON = IN ∙ TON L • OFF phase (2) V + VOUT − DCRL ∙ IL ∆ IL, TOFF = D ∙ TOFF L DS5503 - Rev 7 page 10/33 A6902D Output overvoltage protection where VD is the voltage drop across the diode, DCRL is the series resistance of the Inductor. In short-circuit conditions VOUT is negligible so during TOFF the voltage across the inductor is very small as equal to the voltage drop across parasitic components (typically the DCR of the inductor and the forward voltage of the freewheeling diode) while during TON the voltage applied to the inductor is maximized as approximately equal to VIN. In case a short circuit at the output is applied and VIN = 12 V the inductor current is controlled in most of the applications. When the application must sustain the short-circuit condition for an extended period, the external components (mainly the inductor and diode) must be selected based on this value. In case the VIN is very high, it could occur that the ripple current during TOFF (Eq. (2)) does not compensate the current increase during TON (Eq. (1)). In this case ΔILTON > ΔILTOFF so the current escalates and the balance between Eq. (1) and Eq. (2) occurs at a current slightly higher than the current limit. This must be taken into account in particular to avoid the risk of an abrupt inductor saturation. 6.3 Output overvoltage protection Overvoltage protection, or OVP, is achieved by using an internal comparator connected to the feedback, which turns OFF the power stage when the OVP threshold is reached. This threshold is typically 30% higher than the feedback voltage. 6.4 Zero load operation Due to the fact that the internal power is a PDMOS, no bootstrap capacitor is required and so the device works properly even with no load at the output. In this case it works in burst mode, with a random burst repetition rate. DS5503 - Rev 7 page 11/33 A6902D Closing the loop 7 Closing the loop 7.1 Error amplifier and compensation network The output L-C filter of a step-down converter contributes with 180 degrees phase shift in the control loop. For this reason a compensation network between the COMP pin and GROUND is added. The simplest compensation network together with the equivalent circuit of the error amplifier are shown in figure below. RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability but it is useful to reduce the noise of the COMP pin. The transfer function of the error amplifier and its compensation network is: (3) 1 + s ∙ RC ∙ CC A0 s = AV0 ∙ 2 s ∙ R0 ∙ C0 + CP ∙ RC ∙ CC + s ∙ R0 ∙ CC + R0 ∙ C0 + CP + RC ∙ CC + 1 Where (4) AV0 = Gm ∙ R0 DS5503 - Rev 7 page 12/33 A6902D Error amplifier and compensation network Figure 7. Error amplifier and compensation network E/A COMP + FB - Cp Rc Cc V+ Rc ΔV GmΔV Ro Co 0.8MΩ 10pF Cp Cc Figure 8. Voltage loop block diagram Figure 9. Constant current loop block diagramConstant current loop block diagram DS5503 - Rev 7 page 13/33 A6902D LC filter The poles of this transfer function are (assuming Cc >> C0 + CP): (5) FP1 = 2πR1 C 0 C FP2 = (6) 1 2πRC C0 + CP whereas the zero is defined as: (7) FZ1 = 2πR1 C C C FP1 is the low frequency pole which sets the bandwidth, while the zero FZ1 is usually put near to the frequency of the double pole of the L-C filter (see below). FP2 is usually at a very high frequency. 7.2 LC filter The L-C filter has different contributions depending on the active loop so the design of the compensation network must guarantee a proper bandwidth / phase margin for both operations. 7.2.1 Voltage loop The transfer function of the power stage is given by: (8) 1 GPWR_VM s = 1 1 RLOAD + R + 1 ES s ∙ COUT s ∙ LIND + RDC + RSENSE + 1 1 1 RLOAD + R + 1 ES s ∙ COUT R ∙ R +1R 1 2 R1, R2 represents the output voltage divider. The previous equation can be rewritten and simplified, assuming RES and RDC negligible compared to RLOAD: (9) 1 + 2π ∙ F s R1 Z_ESR_VM GPWR_VM s = GLC0 2 ∙ R1 + R2 s s 1 + 2π ∙ Q ∙ F + 2π ∙ F LC LC R LOAD GLC0 = R ≅1 LOAD + RDC + RSENSE FZ_ESR_VM = 2πR 1C ES OUT FP_LC = 1 RLOAD + RES 2π LIND ∙ COUT ∙ R LOAD + RDC + RSENSE Q≈ L IND ≈ LIND ∙ COUT 1 2π LIND ∙ COUT RLOAD + COUT ∙ RSENSE The singularity introduced by the ESR of the output capacitor, FZ_ESR_VM, is essential to increase the phase margin of the loop. 7.2.2 Constant current loop The transfer function of the output filter is given by: DS5503 - Rev 7 page 14/33 A6902D LC filter (10) GPWR_CM s = RSENSE s ∙ LIND + RDC + RSENSE + 1 1 1 + RLOAD R + 1 ES s ∙ COUT The previous equation can be rewritten and simplified, assuming RES and RDC negligible compared to RLOAD: GPWR_CM s = FZ_ESR_CM = FP_LC = 1 + 2π ∙ F s Z_ESR_CM 2 ∙ RSENSE s s 1 + 2π ∙ Q ∙ F + 2π ∙ F LC LC 1 1 ≈ 2πC 2πCOUT ∙ RLOAD + RES OUT ∙ RLOAD 1 1 ≈ RLOAD + RES 2π LIND ∙ COUT 2π LIND ∙ COUT ∙ R LOAD + RDC + RSENSE Q≈ L IND LIND ∙ COUT RLOAD + COUT ∙ RSENSE As a consequence, the frequency of the zero in current loop operation depends on the loading conditions, whereas the current and voltage power loop transfer functions have the same denominator. In terms of principle it is possible to compensate the current loop with ceramic capacitor at the output, placing fZ_ESR_CM inside the system bandwidth to guarantee enough phase margin for a given loading range. Negligible ESR means fZ_ESR_VM >> fP_LC and so the voltage loop results stable only in discontinuous conduction mode / no load operation but unstable working in continuous conduction mode. An application that fits this operation is when the voltage loop implements just an OVP protection for load disconnection or end of charge detection in battery charging application. 7.2.3 PWM comparator In voltage mode control loop the PWM comparator in Figure 2. Block diagram generates a PWM control signal for the driving circuitry comparing the internal saw tooth waveform and the output of the error amplifier. The transfer function of the PWM modulator, from the error amplifier output (COMP pin) to the switching net (OUT pin) results in an almost constant gain, due to the voltage feed-forward which generates the saw tooth signal with amplitude proportional to the input voltage: (11) V V 1 GPWM s = ∆ VIN = K ∙ IN VIN = 0.076 OSC This means that even if the input voltage changes, the error amplifier does not change its value to keep the loop in regulation, thus ensuring a better line regulation and faster line transient response. In summary, the open loop gain can be expressed as: (12) GTOT s = GPWM s ∙ GPWR_VM s ∙ A0 s GPWM s ∙ GPWR_CM s ∙ A0 s For constant current or constant voltage operation, respectively. DS5503 - Rev 7 page 15/33 A6902D Application information 8 Application information 8.1 Input capacitor selection The input capacitor must be able to support the maximum input operating voltage and the maximum RMS input current. Since step-down converters draw current from the input in pulses, the input current is squared and the height of each pulse is equal to the output current. The input capacitor has to absorb all this switching current. For this reason, the quality of these capacitors has to be very high to minimize the power dissipation generated by the internal ESR, thereby improving system reliability and efficiency. The input capacitor critical parameter is usually the RMS current rating, which must be higher than the RMS input current. The RMS input current (flowing through the input capacitor) is estimated by: (13) ICIN, RMS ≅ IOUT ∙ D ∙ 1 − D The maximum input RMS current is achieved when D = 50%. Based on above requirements of current rating and low ESR, a typical choice is a ceramic capacitor 50 V rated, in the range of 4.7 to 10 µF. Alternative solutions, like low ESR aluminum or polymer capacitors, can also fit if the above requirements are satisfied. High dv/dt voltage spikes on the input side can be critical for DC/DC converters. A good power layout and input voltage filtering help to minimize this issue. In addition to the above considerations, a 1 μF/50 V ceramic capacitor as close as possible to the VCC and GND pins is always suggested to adequately filter VCC spikes. The amount of input voltage ripple can be roughly estimated by: (14) D∙ 1−D VIN, PP ≅ IOUT ∙ C ∙ F + IOUT ∙ RES IN SW In case of MLCC ceramic input capacitors, the equivalent series resistance (RES) is almost negligible. 8.2 Output capacitor selection The output capacitor is very important in order to satisfy the output voltage ripple requirement. Using a small inductor value is useful to reduce the size of the choke but increases the current ripple. So, to reduce the output voltage ripple, a low ESR capacitor is required. Nevertheless, the ESR of the output capacitor introduces a zero in the open loop gain, which helps to increase the phase margin of the system. The current in the output capacitor has a triangular waveform which generates a voltage ripple across it. This ripple is due to the capacitive component (charge and discharge of the output capacitor) and the resistive component (due to the voltage drop across its ESR). So the output capacitor must be selected in order to meet the voltage ripple requirements. The amount of the voltage ripple can be estimated starting from the current ripple obtained by the inductor selection. Assuming ΔIL the inductor current ripple, the output voltage ripple is roughly estimated by: (15) + ∆ IL ∙ RES, OUT ∆ VOUT, PP ≅ ∆ IL ∙ 8 ∙ F 1∙ C SW OUT Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR value. The output capacitor is important also for loop stability: it fixes the double LC filter pole and, above all, the zero due to its ESR. This component must be selected considering all the above requirements. 8.3 Inductor selection The inductance value fixes the current ripple flowing through the output capacitor. The minimum inductance value, in order to have the expected current ripple, must be selected. DS5503 - Rev 7 page 16/33 A6902D Thermal considerations The target current ripple value is typically in the range of 20% - 40% of the output current. In the continuous conduction mode (CCM), the required inductance value can be calculated as follow. (16) V VOUT ∙ 1 − VOUT IN LIND = ∆ IL ∙ FSW In order to guarantee a maximum current ripple in every condition, Eq. (16) must be evaluated in case of maximum input voltage, assuming VOUT fixed. Increasing the value of the inductance help to reduce the current ripple but, at the same time, strongly impacts the converter response time to a dynamic load change. The response time is the time required by the inductor to change its current from the initial to the final value. Until the inductor has finished its charging (or discharging) time, the output current is supplied (or recovered) by the output capacitors. Further, if the compensation network is properly designed, during a load variation the device is able to properly change the duty cycle so improving the control loop transient response. When this condition is reached the response time is only limited by the time required to change the inductor current, basically by VIN, VOUT and L. Minimizing the response time, at the end, can help to decrease the output filter total cost and to reduce the application area. 8.4 Thermal considerations RthJ-A is the equivalent static thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the pin leads is the one conducting the largest amount of heat. The static Rth J-A measured on the application is about 110 °C/W. The junction temperature of device will be estimated as follow: (17) T J = TA + RtℎJA ∙ PTOT The dissipated power of the device is tied to three different sources: (18) PON = RDSON ∙ IOUT 2 ∙D Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN, but in practice it is substantially higher than this value to compensate for the losses in the overall application. For this reason, the switching losses related to the RDSON increases compared to an ideal case. RDSON has a typical value of 0.25 Ω @ 25 °C and increases up to a maximum value of 0.5 Ω @ 125 °C. We can consider a value of 0.4 Ω. • Switching losses due to turning ON and OFF. These are derived using the following equation: (19) T +T PSW = VIN ∙ IOUT ∙ RISE 2 FALL ∙ FSW = VIN ∙ IOUT ∙ TTRAN ∙ FSW Where TRISE and TFALL represent the switching times of the power element that cause the switching losses when driving an inductive load (see figure below). TTRAN is the equivalent switching time, approximately 70 ns. DS5503 - Rev 7 page 17/33 A6902D Maximum output voltage Figure 10. Switching losses VIN OUT VDS IO ISWITCH -VF PSW PON TFALL • PON TRISE Quiescent current losses (20) PQ = VIN ∙ IQ Where IQ is the quiescent current, with typical value 2.5 mA @ VIN = 12 V. The resulting power losses are given by: (21) 8.5 PTOT = PON + PSW + PQ Maximum output voltage The current error amplifier inputs require a biasing point at least 2 V below the VCC for proper operation, as written in Table 4. Electrical characteristics. Adding the expected 100 mV (typical) voltage drop between VCS+ and VCS-, the maximum output voltage that guarantees the proper biasing point of the current sense circuitry is: (22) VOUT, MAX = VIN, MIN − 2.1V The accuracy of the trimmed voltage offset (100 mV ± 5%) between the OTA inputs is not guaranteed if the biasing point is out of specification. To overcome the above described limitation the low-side current sensing schematic can be implemented, as shown in figure below. DS5503 - Rev 7 page 18/33 A6902D Layout considerations Figure 11. Low-side current sensing implementation L1 6 VIN 8 VREF OUT VCC CS+ A6902D 4 COMP C1 GND C4 C3 CSFB 1 VLOAD+ 2 VLOAD- 3 R1 5 7 D1 C5 R2 Rsns R3 GND Here the current error amplifier inputs are biased at the device ground so the duty cycle limitation is no more present. The device can manage 100% duty cycle thanks to the P-CHANNEL embedded power element. This solution is feasible if the load can be left floating (i.e. no more strictly referred to GND). 8.6 Layout considerations The layout of switching DC-DC converters is very important to minimize noise and interference. Power-generating portions of the layout are the main cause of noise and so high switching current loop areas should be kept as small as possible and lead lengths as short as possible. High impedance paths (in particular the feedback connections) are susceptible to interference, so they should be routed as far as possible from the high current paths. A layout example is provided in figure below. Figure 12. Layout example Compensation network far from high current paths Extended ground plane on the bottom side Minimum size of feedback pin connections to avoid pickup R C C R1 5 R2 Very small high current circulating path to minimize radiation and high frequency resonance problems VIN 6 4 A6902D 3 7 2 8 1 L RSNS VOUT Cin Connection to ground plane through VIAs D Cout GND Output capacitor directly connected to heavy ground DS5503 - Rev 7 page 19/33 A6902D Layout considerations The input and output loops are minimized to avoid radiation and high frequency resonance problems. The feedback pin connections to the external divider are very close to the device to avoid pick-up noise. Another important issue is the ground plane of the board. It is very important to connect TOP to BOTTOM ground to improve the thermal dissipation. DS5503 - Rev 7 page 20/33 A6902D Application circuit 9 Application circuit Figure below shows the evaluation board application circuit, where the input supply voltage, VCC, can range from 8 V to 36 V and the programmed output voltage is 3.3 V. Figure 13. Evaluation board application circuit A6902D VIN 8.0V to 36V 6 8 L1 22µH VREF OUT VCC CS+ CS- 4 C1 10µF 50V CERAMIC C3 220pF COMP GND C2 22nF 7 FB 1 R3 100m VOUT,MAX 3.3V 2 3 R1 5.6k 5 D1 STPS2L40 R3 5.1k R2 3.3k C4 150µF 10V GND Table 7. Component list Reference Part number Description Manufacturer C1 GRM32ER61H106KA12L 10 μF, 50 V Murata C2 10 nF, 5%, 0603 C3 33 pF, 5%, 0603 C4 DS5503 - Rev 7 POSCAP 10TPB150ML 150 μF, 25 mΩ R1 5.6 kΩ, 1%, 0.1 W, 0603 R2 3.3 kΩ, 1%, 0.1 W, 0603 R3 22 kΩ, 1%, 0.1 W, 0603 Sanyo D1 STPS2L40U 2 A, 40 V STMicroelectronics L1 DO1813HC-223 22 μH, 1,2 A sat / 0,25 Ω Coilcraft U1 A6902D STMicroelectronics page 21/33 A6902D Application circuit Figure 14. PCB layout (component side) Figure 15. PCB layout (BOTTOM side) Figure 16. PCB layout (TOP side) DS5503 - Rev 7 page 22/33 A6902D Typical characteristics 10 Typical characteristics Figure 17. Line regulation Figure 18. Shutdown current vs. junction temperature Figure 19. Output voltage vs. junction temperature Figure 20. Switching frequency vs. junction temperature Figure 21. Quiescent current vs. junction temperature DS5503 - Rev 7 Figure 22. Efficiency vs. output current page 23/33 A6902D Package information 11 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. DS5503 - Rev 7 page 24/33 A6902D SO8 package information 11.1 SO8 package information Figure 23. SO8 package outline Table 8. SO-8 mechanical data Dim. mm Min. Typ. inch Max. Min. Typ. Max. A 1.35 1.75 0.053 0.069 A1 0.1 0.25 0.004 0.01 A2 1.10 1.65 0.043 0.065 b 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 4.80 5.00 0.189 0.197 3.80 4.00 0.15 0.157 D (1) E e 0.127 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k ddd 0° (min), 8° (max) 0.10 0.004 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm (0.006 inch) in total (both side) DS5503 - Rev 7 page 25/33 A6902D SO8 package information Figure 24. SO-8 footprint recommended DS5503 - Rev 7 page 26/33 A6902D Ordering information 12 Ordering information Table 9. Order codes Order code A6902D A6902D13TR DS5503 - Rev 7 Package SO8 Packing Tube Tape and reel page 27/33 A6902D Revision history Table 10. Document revision history Date Revision 02-Oct-2007 1 First release 5-Nov-2007 2 Updated: Electrical characteristics table 2-May-2008 3 Updated: Electrical characteristics table 28-Aug-2008 4 Updated: Coverpage and Electrical characteristics table 23-Apr-2009 5 Updated: first feature in coverpage 24-Oct-2018 6 Added: Functional description Section 5 Functional description 14-Jun-2022 7 Added Figure 24. SO-8 footprint recommended DS5503 - Rev 7 Changes page 28/33 A6902D Contents Contents 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Datasheet parameters over the temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 8 5.1 Power supply and voltage reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5.2 Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.3 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.4 Current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5.5 Error amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.5.1 Voltage loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.5.2 Constant current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.6 PWM comparator and power stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.7 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Additional features and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 6.1 Feedback disconnection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 OCP protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.3 Output overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 Zero load operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 7.1 Error amplifier and compensation network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.2 LC filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.1 Voltage loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.2 Constant current loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.3 PWM comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8.1 Input capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.2 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.3 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.4 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8.5 Maximum output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6 Layout considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 10 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 DS5503 - Rev 7 page 29/33 A6902D Contents 11 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 11.1 12 SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 DS5503 - Rev 7 page 30/33 A6902D List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical characteristics . . . . . . . . . . . . . . . . . . . . . Uncompensated voltage error amplifier characteristics Uncompensated voltage error amplifier characteristics Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . . . . . DS5503 - Rev 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 3 . 4 . 8 . 8 21 25 27 28 page 31/33 A6902D List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. DS5503 - Rev 7 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driving circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current limit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error amplifier and compensation network . . . . . . . . . . . . . . . . . . . . . . Voltage loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constant current loop block diagramConstant current loop block diagram Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-side current sensing implementation. . . . . . . . . . . . . . . . . . . . . . . Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluation board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB layout (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB layout (BOTTOM side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB layout (TOP side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Shutdown current vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . Output voltage vs. junction temperature . . . . . . . . . . . . . . . . . . . . . . . . Switching frequency vs. junction temperature . . . . . . . . . . . . . . . . . . . . Quiescent current vs. junction temperature. . . . . . . . . . . . . . . . . . . . . . Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SO-8 footprint recommended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 6 . 7 . 7 . 9 10 13 13 13 18 19 19 21 22 22 22 23 23 23 23 23 23 25 26 page 32/33 A6902D IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS5503 - Rev 7 page 33/33