A6986HTR

A6986H Datasheet Automotive 38 V, 2 A synchronous step-down switching regulator with 30 μA quiescent current Features Product status link • • • • • AEC-Q100 qualified 2 A DC output current 4 V to 38 V operating input voltage Low consumption mode or low noise mode 30 µA IQ at light-load (LCM VOUT = 3.3 V) • 8 µA IQ-SHTDWN • Adjustable fSW (250 kHz - 2 MHz) • Fixed output voltage (3.3 V and 5 V) or adjustable from 0.85 V to VIN • • • • • • • • Embedded output voltage supervisor Synchronization Adjustable soft-start time Internal current limiting Overvoltage protection Output voltage sequencing Peak current mode architecture RDS(on) HS = 180 mΩ, RDS(on) LS = 150 mΩ • Thermal shutdown Applications A6986H • • • • Designed for automotive systems Battery powered applications Car body applications (LCM) Car audio and low noise applications (LNM) Description The A6986H automotive grade device is a step-down monolithic switching regulator able to deliver up to 2 A DC. The output voltage adjustability ranges from 0.85 V to VIN. The 100% duty cycle capability and the wide input voltage range meet the cold crank and load dump specifications for automotive systems. The “low consumption mode” (LCM) is designed for applications active during car parking, so it maximizes the efficiency at light-load with controlled output voltage ripple. The “low noise mode” (LNM) makes the switching frequency constant and minimizes the output voltage ripple overload current range, meeting the low noise application specification like car audio. The output voltage supervisor manages the reset phase for any digital load (µC, FPGA). The RST open collector output can also implement output voltage sequencing during the power-up phase. The synchronous rectification, designed for high efficiency at medium - heavy load, and the high switching frequency capability make the size of the application compact. Pulse by pulse current sensing on both power elements implements an effective constant current protection. DS12861 - Rev 3 - August 2020 For further information contact your local STMicroelectronics sales office. www.st.com A6986H Application schematic 1 Application schematic Figure 1. Application schematic uC RST 4 15 VIN 2 10uF 5 1uF 6 3 8 470nF 68nF 10nF SYNCH RST VIN VBIAS VCC FSW MLF LX LX VOUT 10uH 240k FB SS/INH 17 16 13 14 A6986H DELAY EP 1 COMP SGND PGND 10 11 9 75k 7 PGND 12 2.2p 20uF 330p 82k signal GND power GND DS12861 - Rev 3 GND page 2/71 A6986H Pin settings 2 Pin settings 2.1 Pin connection Figure 2. Pin connection (top view) 2.2 RST 1 16 VBIAS VCC 2 15 VIN SS/INH 3 14 LX 13 LX 12 PGND EXPOSED PAD TO SGND+PGND SYNCH/ISKIP 4 FSW 5 MLF 6 11 PGND COMP 7 10 SGND DELAY 8 9 VOUT Pin description Table 1. Pin description DS12861 - Rev 3 N° Pin Description 1 RST The RST open collector output is driven low when the output voltage is out of regulation. The RST is released after an adjustable time DELAY once the output voltage is over the active delay threshold. 2 VCC Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies the embedded analog circuitry. 3 SS/INH 4 SYNCH/ ISKP 5 FSW A pull-up resistor (E24 series only) to VCC or pull down to GND selects the switching frequency. Pin strapping is active only before the soft-start phase to minimize the IC consumption. 6 MLF A pull-up resistor (E24 series only) to VCC or pull-down to GND selects the low consumption mode/low noise mode and the active RST threshold. Pin strapping is active only before the soft-start phase to minimize the IC consumption. 7 COMP Output of the error amplifier. The designed compensation network is connected at this pin. 8 DELAY An external capacitor connected to this pin sets the time DELAY to assert the rising edge of the RST o.c. after the output voltage is over the reset threshold. If this pin is left floating, RST is like a Power Good. 9 VOUT Output voltage sensing 10 SGND Signal GND 11 PGND Power GND 12 PGND Power GND An open collector stage can disable the device clamping this pin to GND (INH mode). An internal current generator (4 µA typ.) charges the external capacitor to implement the softstart. The pin features master / slave synchronization in LNM (see Section 5.8.1 ) and skip current level selection in LCM (see Section 5.8.2 ). In LNM, leave this pin floating when it is not used. page 3/71 A6986H Pin description DS12861 - Rev 3 N° Pin Description 13 LX Switching node 14 LX Switching node 15 VIN DC input voltage 16 VBIAS - Exposed pad Typically connected to the regulated output voltage. An external voltage reference can be used to supply part of the analog circuitry to increase the efficiency at light-load. Connect to GND if not used. Exposed pad must be connected to SGND, PGND page 4/71 A6986H Maximum ratings 2.3 Maximum ratings Stressing the device above the rating listed in Table 2 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 2. Absolute maximum ratings Symbol Min. Max. Unit VIN -0.3 40 V DELAY -0.3 VCC+ 0.3 V PGND SGND - 0.3 SGND + 0.3 V SGND - - V VCC -0.3 (VIN+ 0.3) or (max. 4) V SS /INH -0.3 VIN+ 0.3 V -0.3 VCC+ 0.3 V -0.3 VCC+ 0.3 V VOUT -0.3 10 V FSW -0.3 VCC+ 0.3 V SYNCH -0.3 VIN+ 0.3 V VBIAS -0.3 (VIN+ 0.3) or (max. 6) V RST -0.3 VIN+ 0.3 V LX -0.3 VIN+ 0.3 V MLF COMP DS12861 - Rev 3 Description See Table 1. Pin description TJ Operating temperature range -40 150 °C TSTG Storage temperature range - -65 to 150 °C TLEAD Lead temperature (soldering 10 s.) - 260 °C IHS, ILS High-side / low-side switch current - 2 A page 5/71 A6986H Thermal data 2.4 Thermal data Table 3. Thermal data Symbol 2.5 Parameter Value Unit RthJA Thermal resistance junction ambient (device soldered on the STMicroelectronics demoboard) 40 °C/W RthJC Thermal resistance junction to exposed pad for board design (not suggested to estimate TJ from power losses) 5 °C/W ESD protection Table 4. ESD protection Symbol Parameter Test conditions HBM ESD DS12861 - Rev 3 ESD protection voltgage Value Unit ±2 kV CDM corner pins ± 750 CDM non-corner pins ± 500 V page 6/71 A6986H Electrical characteristics 3 Electrical characteristics Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. Symbol VIN VIN_H VIN_L Parameter Operating input voltage range VCC UVLO rising threshold VCC UVLO falling threshold Test conditions Note Min. Typ. Max. - - 4 - 38 - - 2.7 - 3.5 - - 2.4 - 3.5 Unit V Duty cycle < 20% - 2.55 - - IPK Peak current limit Duty cycle = 100% closed loop operation - 2.1 - - IVY Valley current limit - - 2.7 - - LCM, VSYNCH = GND (1) 0.6 0.8 LCM, VSYNCH = VCC (2) - 0.2 - - ISKIPH ISKIPL Programmable skip current limit A IVY_SNK Reverse current limit LNM or VOUT overvoltage - 0.8 1 2 RDS(on) HS High-side RDSON ISW=1 A - - 0.18 0.36 RDS(on) LS Low-side RDSON ISW=1 A - - 0.15 0.30 fSW Selected switching frequency FSW pinstrapping before SS - IFSW FSW biasing current SS ended - LCM/LNM Low noise mode / low consumption MLF pinstrapping before SS - Ω See Table 6 - 0 500 nA See Table 7, Table 8 and Table 9 mode selection IMLF MLF biasing current SS ended - - 0 500 nA D Duty cycle - (2) 0 - 100 % TON MIN Minimum on-time - - - 80 - ns VBIAS = GND (no switchover) - 2.9 3.3 3.6 VBIAS = 5 V (switchover) - 2.9 3.3 3.6 - 2.85 - 3.2 - 2.78 - 3.15 - 4 8 15 VCC regulator VCC LDO output voltage Switch internal supply from VIN SWO VBIAS threshold to VBIAS (3 V< VBIAS VTHR - 1.19 1.234 1.258 V ID CH CDELAY charging current VFB> VTHR - 1 2 3 µA Thermal shutdown TSHDWN Thermal shutdown temperature - (2) - 165 - THYS Thermal shutdown hysteresis - (2) - 30 - °C 1. Parameter tested in static condition during testing phase. Parameter value may change over dynamic application conditions. 2. Not tested in production. 3. LCM enables SLEEP mode at light-load. 4. TJ = - 40 °C. 5. Measured at fsw = 250 kHz. DS12861 - Rev 3 page 9/71 A6986H Electrical characteristics Table 6. fSW selection TJ = - 40 to 135 °C, VIN= 12 V unless otherwise specified. Symbol RVCC (E24 series) fSW RGND (E24 series) Tj fSW min. fSW typ. fSW max. 0Ω NC (1) 225 250 275 1.8 Ω NC - 285 - 3.3 kΩ NC - 330 - 5.6 kΩ NC - 380 - 10 kΩ NC - 435 - 450 500 550 - 575 - - 660 - - 755 - - 870 - 900 1000 1100 - 1150 - - 1310 - - 1500 - NC 0Ω 18 kΩ NC 33 kΩ NC 56 kΩ NC NC 1.8 kΩ (1)(2) (3) (1) (3) (3) kHz NC 3.3 kΩ NC 5.6 kΩ NC 10 kΩ NC 18 kΩ NC 33 kΩ (3) 1575 1750 1925 NC 56 kΩ (3) 1800 2000 2200 (2) (3) Unit 1. Synchronization as slave in LNM between 275 kHz and 1400 kHz. 2. Not tested in production 3. Synchronization as slave in LNM between 475 kHz and 2200 kHz Table 7. LNM/ LCM selection (A6986H3V3) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. Symbol RVCC(E24 1%) RGND(E24 1%) Operating mode VRST DS12861 - Rev 3 0Ω NC 8.2 kΩ NC 18 kΩ NC 39 kΩ VRST/VOUT (tgt. value) VRST min. VRST typ. VRST max. Unit 93% 3.008 3.069 3.130 80% 2.587 2.640 2.693 87% 2.814 2.871 2.928 NC 96% 3.105 3.168 3.231 NC 0Ω 93% 3.008 3.069 3.130 NC 8.2 kΩ 80% 2.587 2.640 2.693 NC 18 kΩ 87% 2.814 2.871 2.928 NC 39 kΩ 96% 3.105 3.168 3.231 LCM LNM V page 10/71 A6986H Electrical characteristics Table 8. LNM/ LCM selection (A6986H5V) TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified. Symbol RVCC(E24 1%) RGND(E24 1%) Operating mode VRST 0Ω NC 8.2 kΩ NC 18 kΩ NC 39 kΩ VRST/VOUT (tgt. value) VRST min. VRSTtyp. VRSTmax. Unit 93% 4.557 4.650 4743 80% 3920 4000 4080 87% 4263 4350 4437 NC 96% 4704 4800 4896 NC 0Ω 93% 4557 4650 4743 NC 8.2 kΩ 80% 3920 4000 4080 NC 18 kΩ 87% 4263 4350 4437 NC 39 kΩ 96% 4704 4800 4896 LCM LNM V Table 9. LNM/ LCM selection (A6986H) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. Symbol RVCC(E24 1%) RGND(E24 1%) Operating mode VRST DS12861 - Rev 3 0Ω NC 8.2 kΩ ±1% NC 18 kΩ ±1% NC 39 kΩ ±1% VRST/VOUT (tgt. value) VRST min. VRSTtyp. VRSTmax. Unit 93% 0.779 0.791 0.802 80% 0.670 0.680 0.690 87% 0.728 0.740 0.751 NC 96% 0.804 0.816 0.828 NC 0Ω 93% 0.779 0.791 0.802 NC 8.2 kΩ ±1% 80% 0.670 0.680 0.690 NC 18 kΩ ±1% 87% 0.728 0.740 0.751 NC 39 kΩ ±1% 96% 0.804 0.816 0.828 LCM LNM V page 11/71 A6986H Parameters over the temperature range 4 Parameters over the temperature range The 100% of the population in the production flow is tested at three different ambient temperatures (-40 °C, +25 °C, +135 °C) to guarantee the datasheet parameters inside the junction temperature range (-40 °C, +135 °C). The device operation is guaranteed when the junction temperature is inside the (-40 °C, +150 °C) temperature range. The designer can estimate the silicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation. However the embedded thermal protection disables the switching activity to protect the device in case the junction temperature reaches the TSHTDWN(+165 °C typ.) temperature. All the datasheet parameters can be guaranteed to a maximum junction temperature of +135 °C to avoid triggering the thermal shutdown protection during the testing phase because of self-heating. DS12861 - Rev 3 page 12/71 A6986H Functional description 5 Functional description The A6986H device is based on a “peak current mode”, constant frequency control. As a consequence, the intersection between the error amplifier output and the sensed inductor current generates the PWM control signal to drive the power switch. The device features LNM (low noise mode) that is forced PWM control, or LCM (low consumption mode) to increase the efficiency at light-load. The main internal blocks shown in the block diagram in Figure 3. Internal block diagram are: • Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the device features lowdropout operation • A fully integrated sawtooth oscillator with adjustable frequency • A transconductance error amplifier • An internal feedback divider GDIV INT • • • • • • • • • • • The high-side current sense amplifier to sense the inductor current A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements The soft-start blocks to ramp the error amplifier reference voltage and so decreases the inrush current at power-up. The SS/INH pin inhibits the device when driven low The switchover capability of the internal regulator to supply a portion of the quiescent current when the VBIAS pin is connected to an external output voltage The synchronization circuitry to manage master / slave operation and the synchronization to an external clock The current limitation circuit to implement the constant current protection, sensing pulse by pulse high-side / low-side switch current. In case of heavy short-circuit the current protection is fold back to decrease the stress of the external components A circuit to implement the thermal protection function The OVP circuitry to discharge the output capacitor in case of overvoltage event MLF pin strapping sets the LNM/LCM mode and the thresholds of the RST comparator FSW pinstrapping sets the switching frequency The RST open collector output Figure 3. Internal block diagram COMP SYNC FSW VIN SS/INH SS/INH 0 VOUT GDIV INT TSS PEAK CL E/A OVP POWER PMOS SENSE PMOS OSCILLATOR VREF LOOP LOOP CONTROL CONTROL SLOPE + - GND LX DRIVER DRIVER + DELAY L.N. / L.C. RST TH. SENSE Vcc NMOS ZERO CROSSING POWER NMOS GND RST VALLEY CL DELAY DS12861 - Rev 3 MLF GND page 13/71 A6986H Power supply and voltage reference 5.1 Power supply and voltage reference The internal regulator block consists of a start-up circuit, the voltage pre-regulator that provides current to all the blocks and the bandgap voltage reference. The starter supplies the start-up current when the input voltage goes high and the device is enabled (SS/INH pin over the inhibits threshold). The pre-regulator block supplies the bandgap cell and the rest of the circuitry with a regulated voltage that has a very low supply voltage noise sensitivity. Switchover feature The switchover scheme of the pre-regulator block features to derive the main contribution of the supply current for the internal circuitry from an external voltage (3 V < VBIAS VSS_END (9) RUP and RDWN are selected to guarantee: The time to ramp the internal voltage reference can be calculated as follows VSS_FINAL − VSS START TSS = CSS ⋅ RSS_EQ ⋅ In( ) VSS_FINAL − VSS END (10) that is the equivalent soft-start time to ramp the output voltage. Figure 8. External soft-start network VSTEP driven shows the soft-start phase with the following component selection: RUP = 180 kΩ, RDWN = 33 kΩ, CSS = 200 nF, the 1N4148 is a small signal diode and VSTEP = 13 V. DS12861 - Rev 3 page 17/71 A6986H Soft-start and inhibit Figure 8. External soft-start network VSTEP driven The circuit in Figure 7. Enable the device with external voltage step introduces a time delay between VSTEP and the switching activity that can be calculated as: VSS_FINAL TSS = CSS ⋅ RSS_EQ ⋅ In( ) VSS_FINAL − VSS START (11) Figure 9. External soft-start after UVLO or thermal shutdown shows how the device discharges the soft-start capacitor after an UVLO or thermal shutdown event in order to restart the switching activity ramping the error amplifier reference voltage. Figure 9. External soft-start after UVLO or thermal shutdown DS12861 - Rev 3 page 18/71 A6986H Soft-start and inhibit 5.3.1 Ratiometric startup The ratiometric start-up is implemented sharing the same soft-start capacitor for a set of the A6986H devices Figure 10. Ratiometric startup V VOUT3 VOUT2 VOUT1 t As a consequence all the internal current generators charge in parallel the external capacitor. The capacitor value is dimensioned accordingly, as per equation below: CSS = nA6986H ⋅ SSGAIN ⋅ ISSCH ⋅ TSS 4μA ⋅ TSS = nA6986H ⋅ 3 ⋅ VFB 0.85V (12) where nA6986H represents the number of devices connected in parallel. For better tracking of the different output voltages the synchronization of the set of regulators is suggested. Figure 11. Ratiometric startup operation DS12861 - Rev 3 page 19/71 A6986H Error amplifier 5.3.2 Output voltage sequencing The A6986H device implements sequencing connecting the RST pin of the master device to the SS/INH of the slave. The slave is inhibited as long as the master output voltage is outside regulation so implementing the sequencing, see Figure 12. Output voltage sequencing. Figure 12. Output voltage sequencing V VOUT3 VOUT2 VOUT1 t tDELAY1 tDELAY2 tDELAY3 High flexibility is achieved thanks to the programmable RST thresholds (Table 7. LNM/ LCM selection (A6986H3V3) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. and Table 8. LNM/ LCM selection (A6986H5V) TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.) and programmable delay time. To minimize the component count the DELAY pin capacitor can be also omitted so the pin works as a normal Power Good. 5.4 Error amplifier The voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose non inverting input is connected to the internal voltage reference (0.85 V), while the inverting input (FB) is connected to the external divider or directly to the output voltage. Table 10. Uncompensated error amplifier characteristics Description Value Transconductance 155 µS Low frequency gain 100 dB The error amplifier output is compared with the inductor current sense information to perform PWM control. The error amplifier also determines the burst operation at light-load when the LCM is active. 5.5 Output voltage line regulation The regulator features an enhanced line regulation thanks to the peak current mode architecture. Figure 13. VOUT = 3.3 V line regulation shows negligible output voltage variation (normalized to the value measured at VIN = 12 V) over the entire input voltage range for the A6986H with VOUT = 3.3V. DS12861 - Rev 3 page 20/71 A6986H Output voltage load regulation Figure 13. VOUT = 3.3 V line regulation 0.10% ΔVOUT[V] 0.05% 0.00% -0.05% -0.10% 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 VIN [V] 5.6 Output voltage load regulation Figure 14. VOUT = 3.3 V load regulation shows negligible output voltage variation (normalized to the value measured at IOUT = 0 A) over the entire output current range for the A6986H with VOUT = 3.3 V, measured on the A6986H evaluation board (see Section 8 Application board). Figure 14. VOUT = 3.3 V load regulation 0.10% ΔVOUT[%] 0.05% 0.00% -0.05% -0.10% 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 IOUT[A] DS12861 - Rev 3 page 21/71 A6986H High-side switch resistance vs. input voltage 5.7 High-side switch resistance vs. input voltage Figure 15. Normalized RDS(on),HS variation shows the high-side switch RDS(on) variation over the entire input voltage operating range normalized at the value measured at VIN = 12 V (see Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.). Figure 15. Normalized RDS(on),HS variation RDS(on),HS @ IOUT =1A (normalized @ V IN =12V) RDSON,HS Deviation [%] 3% 2% 1% 0% -1% -2% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 VIN [V] 5.8 Light-load operation The MLF pinstrapping during the power-up phase determines the light-load operation (refer to Table 7. LNM/ LCM selection (A6986H3V3) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. and Table 8. LNM/ LCM selection (A6986H5V) TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified.). 5.8.1 Low noise mode (LNM) The low noise mode implements a forced PWM operation over the different loading conditions. The LNM features a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed VIN. The regulator in steady loading condition never skips pulses and it operates in continuous conduction mode (CCM) over the different loading conditions, thus making this operation mode ideal for noise sensitive applications. DS12861 - Rev 3 page 22/71 A6986H Light-load operation Figure 16. Low noise mode operation Typical applications for the LNM operation are car audio and sensors. 5.8.2 Low consumption mode (LCM) The low consumption mode maximizes the efficiency at light-load. The regulator prevents the switching activity whenever the switch peak current request is lower than the ISKIP threshold. As a consequence the A6986H device works in bursts and it minimizes the quiescent current request in the meantime between the switching operation. In LCM operation, the pin SYNCH/ISKIP level dynamically defines the ISKIP current threshold (see Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.) as shown in Table 11. ISKIP programmable current threshold. Table 11. ISKIP programmable current threshold SYNCH / ISKIP (pin 4) ISKIP current threshold Low ISKIPH = 0.6 A typical High ISKIPL = 0.2 A typical The ISKIP programmability helps to optimize the performance in terms of the output voltage ripple or efficiency at the light-load, that are parameters which disagree each other by definition. A lower skip current level minimizes the voltage ripple but increases the switching activity (time between bursts gets closer) since less energy per burst is transferred to the output voltage at the given load. On the other side, a higher skip level reduces the switching activity and improves the efficiency at the light-load but worsen the voltage ripple. No difference in terms of the voltage ripple and conversion efficiency for the medium and high load current level, that is when the device operates in the discontinuous or continuous mode (DCM vs. CCM). The A6986H allows changing the skip current threshold level while the device is switching in order to adapt the pulse skipping operation to the loading condition. The time needed to detect and implement this transition is negligible with respect to the switching period. DS12861 - Rev 3 page 23/71 A6986H Light-load operation When the A6986H is configured in the low consumption mode, the SYNCH/ISKIP pin operates as a logic gate input pin with an internal pull-down (4.5 µA typ.) guaranteeing the ISKIPH operation when leaving the pin floating. Table 12. SYNCH/ISKIP pin voltage thresholds and driving current reports the VSYNCH/ISKIP thresholds and the minimum current needed to drive the pin. Table 12. SYNCH/ISKIP pin voltage thresholds and driving current Parameter Value VSKIP_TH_L_MAX 0.65 V VSKIP_TH_H_MIN 1.6 V ISYNCH/ISKIP_DRIVING_MIN ± 10 µA Figure 17. A6986H skip current level transition at ILOAD = 150 mA with L = 10 µH shows a skip current threshold transition at ILOAD = 150 mA measured on the A6986H - VOUT = 3.3 V with fsw = 500 kHz and L = 10 µH: • • When V(SYNCH/ISKIP) < VSKIP_TH_L_MAX, the A6986H operates in the pulse skipping mode minimizing current consumption When V(SYNCH/ISKIP) > VSKIP_TH_H_MIN, the A6986H operates in the continuous conduction mode minimizing the output voltage ripple Figure 17. A6986H skip current level transition at ILOAD = 150 mA with L = 10 µH Figure 18. Light-load efficiency comparison at different ISKIP - linear scale and Figure 19. Light-load efficiency comparison at different ISKIP - log scale report the efficiency measurements to highlight the ISKIPH and ISKIPL efficiency gap at the light-load also in comparison with the LNM operation. The same efficiency at the medium / high load is confirmed at different ISKIP levels. DS12861 - Rev 3 page 24/71 A6986H Light-load operation Figure 18. Light-load efficiency comparison at different ISKIP - linear scale VIN=13.5 V; VOUT=3.3V; fsw=500kH z 90 85 EFFICIENCY [%] 80 75 LCM ISKIPH=600mA 70 LCM ISKIPL=200mA 65 LNM LNM - SWO LCM_ISKIPH - SWO 60 LCM_ISKIPL - SWO 55 50 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 ILOAD [A] Figure 19. Light-load efficiency comparison at different ISKIP - log scale VIN=13.5V; VOUT=3.3 V; fsw=5 00kH z 100 90 EFFICIENCY [%] 80 70 LCM ISKIPH=600mA 60 LCM ISKIPL=200mA 50 LNM 40 30 LNM - SWO 20 LCM_ISKIPH - SWO 10 LCM_ISKIPL - SWO 0 0.001 0.1 0.01 ILOAD [A] Figure 20. LCM operation with ISKIPH = 600 mA typ. at zero load and Figure 21. LCM operation with ISKIPL = 200 mA typ. at zero load show the LCM operation at the different ISKIP level. Figure 20. LCM operation with ISKIPH = 600 mA typ. at zero load shows the ISKIPH = 600 mA typ. and so 50 mV output voltage ripple. Figure 21. LCM operation with ISKIPL = 200 mA typ. at zero load shows the ISKIPL = 200 mA typ. and so less than 20 mV output voltage ripple. DS12861 - Rev 3 page 25/71 A6986H Light-load operation Figure 20. LCM operation with ISKIPH = 600 mA typ. at zero load Figure 21. LCM operation with ISKIPL = 200 mA typ. at zero load DS12861 - Rev 3 page 26/71 A6986H Light-load operation The LCM operation satisfies the requirements of the unswitched car body applications (KL30). These applications are directly connected to the battery and are operating when the engine is disabled. The typical load when the car is parked is represented by a CAN transceiver and a microcontroller in sleep mode (total load is around 20 - 30 µA). As soon as the transceiver recognizes a valid word in the bus, it awakes the µC and the rest of the application. The typical input current request of the module when the car is parked is 100 µA typ. to prevent the battery discharge over the parking time. In order to minimize the regulator quiescent current request from the input voltage, the VBIAS pin can be connected to an external voltage source in the range 3 V < VBIAS < 5.5 V (see Section 5.1 Power supply and voltage reference). Given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value: T ∫0 BURST (iL(t) ⋅ dt) ΔQIL VOUT RIPPLE = = COUT COUT (13) Figure 22. LCM operation over loading condition (part 1) DS12861 - Rev 3 page 27/71 A6986H Light-load operation Figure 23. LCM operation over loading condition (part 2-pulse skipping) Figure 24. LCM operation over loading condition (part 3-pulse skipping) DS12861 - Rev 3 page 28/71 A6986H Light-load operation Figure 25. LCM operation over loading condition (part 4-CCM) 5.8.3 Quiescent current in LCM with switchover The current absorbed from the input voltage in the low consumption mode while regulating the output voltage at the zero output load depends on the input voltage value and the selected skip current level, as shown in Figure 26. Quiescent current at VOUT = 3.3 V and zero output load and Figure 27. Quiescent current at VOUT = 5 V and zero output load Figure 26. Quiescent current at VOUT = 3.3 V and zero output load When VIN is adequately higher than VOUT (see Figure 26. Quiescent current at VOUT = 3.3 V and zero output load ) the device works in the bursts mode operation, minimizing the power consumption over the entire input voltage (see Section 5.8.2 Low consumption mode (LCM)). DS12861 - Rev 3 page 29/71 A6986H Light-load operation Figure 27. Quiescent current at VOUT = 5 V and zero output load A6986H input current with VBIAS =VOUT=5V and ILOAD =0 LCM-500kHz 120 ISKIPH ISKIPL IQUIESC_VIN [µA] 100 80 60 40 20 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 VIN [V] When VIN approaches VOUT (see Figure 27. Quiescent current at VOUT = 5 V and zero output load and zoomed Figure 28. Quiescent current at VIN while regulating VOUT = 5 V at zero output load) the device increases the switching activity towards the continuous conduction mode operation for the internal slope contribution effect on the programmed skip current threshold. As a consequence the quiescent current increases. When VIN is lower than VOUT (see Figure 28. Quiescent current at VIN while regulating VOUT = 5 V at zero output load), the device enters in the low-dropout operation with the high-side always switched on. In this operating condition, all the internal circuit blocks are active and the quiescent current corresponds to what measured in the low noise mode operation (see IQ OP VIN and IQ OP VBIAS in Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. given VFB = GND). Figure 28. Quiescent current at VIN while regulating VOUT = 5 V at zero output load A6986H Input Current VBIAS =VOUT =5V and I LOAD =0 LCM -500kHz 16 ISKIPH ISKIPL 14 I QUIESC_VIN [mA] 12 10 8 6 Drop Out No SLEEP Mode 4 Pulse Skipping SLEEP Mode Continuous Conduction Mode 2 0 4 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8 6 VIN [V] DS12861 - Rev 3 page 30/71 A6986H Switchover feature 5.9 Switchover feature The switchover maximizes the efficiency at the light-load that is crucial for LCM applications. The switchover operation features to derive the main contribution of the supply current for the internal circuitry from an external voltage (3 V < VBIAS < 5.5 V is typically connected to the regulated output voltage). This helps to decrease the equivalent quiescent current seen at VIN. In case the regulator output voltage is not compatible with the VBIAS input voltage range, it is possible to use an auxiliary voltage source for the switchover operation. The external auxiliary voltage source must always respect the condition 3 V < VAUX < 5.5 V, and must be derived from the A6986H power supply (VIN - pin 15) for proper power sequencing of the internal circuits. 5.9.1 LCM The LCM operation satisfies the high efficiency requirements of the battery powered applications. In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current drawn from the input voltage can be calculated as: VBIAS 1 IQVIN = IQOPVIN + ⋅ ⋅ IQOPVBIAS ηA6986H VIN (14) where IQ OP VIN, IQ OP VBIAS are defined in Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. and ηA6986H is the efficiency of the conversion in the working point. 5.9.2 LNM Eq. (14) is also valid when the device works in LNM and it can increase the efficiency at the medium load since the regulator always operates in the continuous conduction mode. 5.10 Overcurrent protection The current protection circuitry features a constant current protection, so the device limits the maximum peak current (see Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.) in overcurrent condition. The A6986H device implements a pulse by pulse current sensing on both power elements (high-side and low-side switches) for effective current protection over the duty cycle range. The high-side current sensing is called “peak” the low-side sensing “valley”. The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a minimum conduction time of the power element. This time is called “masking time” because the information from the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. As a consequence, the peak current protection is disabled for a masking time after the high-side switch is turned on, the valley for a masking time after the low-side switch is turned on. In other words, the peak current protection can be ineffective at extremely low duty cycles, the valley current protection at extremely high duty cycles. The A6986H device assures an effective overcurrent protection sensing the current flowing in both power elements. In case one of the two current sensing circuitry is ineffective because of the masking time, the device is protected sensing the current on the opposite switch. Thus, the combination of the “peak” and “valley” current limits assures the effectiveness of the overcurrent protection even in extreme duty cycle conditions. The valley current threshold is designed higher than the peak to guarantee a proper operation. In case the current diverges because of the high-side masking time, the low-side power element is turned on until the switch current level drops below the valley current sense threshold. The low-side operation is able to prevent the high-side turn on, so the device can skip pulses decreasing the switching frequency. DS12861 - Rev 3 page 31/71 A6986H Overcurrent protection Figure 29. Valley current sense operation in overcurrent condition Figure 29. Valley current sense operation in overcurrent condition shows the switching frequency reduction during the valley current sense operation in case of extremely low duty cycle (VIN = 12 V, fSW = 2 MHz short-circuit condition). In a worst case scenario (like Figure 29. Valley current sense operation in overcurrent condition) of the overcurrent protection the switch current is limited to: IMAX = IVALLEYTH + VIN − VOUT ⋅ TMASKHS L (15) where IVALLEY_TH is the current threshold of the valley sensing circuitry (see Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.) and TMASK_HS is the masking time of the high-side switch 100 ns typ.). In most of the overcurrent conditions the conduction time of the high-side switch is higher than the masking time and so the peak current protection limits the switch current. IMAX = IPEAK_TH DS12861 - Rev 3 (16) page 32/71 A6986H OCP and switchover feature Figure 30. Peak current sense operation in overcurrent condition The DC current flowing in the load in overcurrent condition is: 5.11 IDCOC(VOUT) = IMAX − OCP and switchover feature IRIPPLE(VOUT) VIN − VOUT = IMAX − ( ⋅ TON) 2 2⋅L (17) Output capacitor discharging the current flowing to ground during heavy short-circuit events is only limited by parasitic elements like the output capacitor ESR and short-circuit impedance. Due to parasitic inductance of the short-circuit impedance, negative output voltage oscillations can be generated with huge discharging current levels (see Figure 12. Output voltage sequencing). DS12861 - Rev 3 page 33/71 A6986H OCP and switchover feature Figure 31. Output voltage oscillations during heavy short-circuit Figure 32. Zoomed waveforms DS12861 - Rev 3 page 34/71 A6986H Overvoltage protection The VBIAS pin absolute maximum ratings (see Table 2. Absolute maximum ratings) must be satisfied over the different dynamic conditions. If the VBIAS is connected to GND there are no issues (see Figure 31. Output voltage oscillations during heavy short-circuit and Figure 32. Zoomed waveforms). A small resistor value (few ohms) in series with the VBIAS can help to limit the pin negative voltage (see Figure 33. VBIAS in heavy short-circuit event) during heavy short-circuit events if it is connected to the regulated output voltage. Figure 33. VBIAS in heavy short-circuit event 5.12 Overvoltage protection The overvoltage protection monitors the VOUT pin and enables the low-side MOSFET to discharge the output capacitor if the output voltage is 20% over the nominal value. This is a second level protection and should never be triggered in normal operating conditions if the system is properly dimensioned. In other words, the selection of the external power components and the dynamic performance determined by the compensation network should guarantee an output voltage regulation within the overvoltage threshold even during the worst case scenario in term of load transitions. The protection is reliable and also able to operate even during normal load transitions for a system whose dynamic performance is not in line with the load dynamic request. As a consequence the output voltage regulation would be affected. Figure 34. Overvoltage operation shows the overvoltage operation during a negative steep load transient for a system configured in low consumption mode and designed with a not optimized compensation network. This can be considered as an example for a system with dynamic performance not in line with the load request. The A6986H device implements a 1 A typ. negative current limitation to limit the maximum reversed switch current during the overvoltage operation. Moreover, the overvoltage protection also activates the internal pull-down on RST pin. Once OVP is deactivated, the A6986H releases the RST pin after the delay programmed by DELAY capacitor (6 ms in Figure 34. Overvoltage operation). DS12861 - Rev 3 page 35/71 A6986H Thermal shutdown Figure 34. Overvoltage operation 5.13 Thermal shutdown The shutdown block disables the switching activity if the junction temperature is higher than a fixed internal threshold (165 °C typical). The thermal sensing element is close to the power elements, ensuring fast and accurate temperature detection. A hysteresis of approximately 30 °C prevents the device from turning ON and OFF continuously. When the thermal protection runs away a new soft-start cycle will take place. DS12861 - Rev 3 page 36/71 A6986H Closing the loop 6 Closing the loop Figure 35. Block diagram of the loop 6.1 GCO(s) control to output transfer function The accurate control to output transfer function for a buck peak current mode converter can be written as: S ωZ GCO(s) = RLOAD ⋅ gCS ⋅ ⋅ ⋅ FH(s) RLOAD ⋅ TSW S ⋅ [mC ⋅ (1 − D) − 0.5] 1 + ω 1+ L p 1 1+ (18) where RLOAD represents the load resistance, gCS the equivalent sensing transconductance of the current sense circuitry, wp the single pole introduced by the power stage and wz the zero given by the ESR of the output capacitor. FH(s) accounts the sampling effect performed by the PWM comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. 1 ωZ = ESR ⋅ COUT where: mc ⋅ (1 − D) − 0.5 1 ωp = + RLOAD ⋅ COUT L ⋅ COUT ⋅ fSW Se mC = 1 + Sn Se = VPP ⋅ gCS ⋅ fSW (19) (20) (21) VIN − VOUT Sn = L Sn represents the on time slope of the sensed inductor current, Se the on time slope of the external ramp (VPP peak-to-peak amplitude) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%. Se can be calculated from the parameter VPP × gCS given in Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. . DS12861 - Rev 3 page 37/71 A6986H Error amplifier compensation network The sampling effect contribution FH(s) is: FH(s) = where: 6.2 1+ 1 (22) s S2 ωn ⋅ Qp + 2 ωn ωn = π ⋅ fSW 1 Qp = π ⋅ [mc ⋅ (1 − D) − 0.5] (23) Error amplifier compensation network The typical compensation network required to stabilize the system is shown in Figure 36. Transconductance embedded error amplifier: Figure 36. Transconductance embedded error amplifier RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability but it is useful to reduce the noise at the output of the error amplifier. The transfer function of the error amplifier and its compensation network is: AV0 ⋅ (1 + s ⋅ RC ⋅ Cc) A0(s) = 2 s ⋅ R0 ⋅ (C0 + Cp) ⋅ RC ⋅ Cc + s ⋅ (R0 ⋅ Cc + R0 ⋅ (C0 + Cp) + Rc ⋅ Cc) + 1 (24) Where Avo = Gm · Ro The poles of this transfer function are (if Cc >> C0 + CP): 1 fPLF = 2 ⋅ π ⋅ R0 ⋅ Cc DS12861 - Rev 3 (25) page 38/71 A6986H Voltage divider whereas the zero is defined as: 6.3 1 fPHF = 2 ⋅ π ⋅ R0 ⋅ (C0 + Cp) (26) 1 fZ = 2 ⋅ π ⋅ Rc ⋅ Cc Voltage divider (27) The contribution of the internal voltage divider for fixed output voltage devices is: R2 VFB 0.85 = 0.2575 GDIV(s) = = = R1 + R2 VOUT 3.3 R2 VFB 0.85 = 0.17 GDIV(s) = = = 5 R1 + R2 VOUT A6986H3V (28) A698HF5V while for the adjustable output part number A6986H is: R2 GDIV(s) = R1 + R2 A6986H (29) A small signal capacitor in parallel to the upper resistor (see Figure 37. Leading network example) of the voltage divider implements a leading network (fzero < fpole), sometimes necessary to improve the system phase margin: Figure 37. Leading network example uC RST 4 VIN 15 2 5 6 3 8 SYNCH RST VIN VBIAS VCC FSW MLF LX LX VOUT 13 14 Cr1 FB SS/INH 17 16 A6986H DELAY EP 1 COMP SGND PGND 10 11 R1 9 Rc 7 PGND 12 Cp Cc R2 signal GND Power GND GND The Laplace transformer of the leading network is: where R2 GDIV(s) = ⋅ R1 + R2 (1 + s + R1 ⋅ CR1) R1 ⋅ R2 (1 + s ⋅ ⋅C ) R1 + R2 R1 1 fZ = 2 ⋅ π ⋅ R1 ⋅ CR1 fp = 1 R1 ⋅ R2 2⋅π⋅ ⋅C R1 + R2 R1 (30) (31) fZ < fp DS12861 - Rev 3 page 39/71 A6986H Total loop gain 6.4 Total loop gain In summary, the open loop gain can be expressed as: G(s) = GDIV(s) ⋅ GCO(s) ⋅ A0(s) (32) example 1: VIN = 12 V, VOUT = 3.3 V, ROUT = 1.67 Ω Selecting the A6986H with VOUT=3.3 V, fSW = 500 kHz, L = 10 µH, COUT = 20 µF and ESR = 3 mΩ, RC = 75 kΩ, CC = 330 pF, CP = 2.2 pF (please refer to Table 19. A6986H 3V3 demonstration board BOM), the gain and phase bode diagrams are plotted respectively in Figure 38. Module plot and Figure 39. Phase plot. Figure 38. Module plot BW = 55 kHZ phase margin = 60 ° Figure 39. Phase plot The blue solid trace represents the transfer function including the sampling effect term (see Eq. (22)), the dotted blue trace neglects the contribution. DS12861 - Rev 3 page 40/71 A6986H Compensation network design 6.5 Compensation network design The maximum bandwidth of the system can be designed up to fSW/6 up to 150 kHz maximum to guarantee a valid small signal model. where: 2 ⋅ π ⋅ BW ⋅ COUT ⋅ VOUT RC = 0.85V ⋅ gCS ⋅ gm TYP (33) ωp fPOLE = 2⋅π (34) ωp is defined by Eq. (20), gCS represents the current sense transconductance (see Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.) and gm TYP the error amplifier transconductance. 5 CC = 2 ⋅ π ⋅ RC ⋅ BW (35) Example 2: Considering VIN = 12 V, VOUT = 3.3 V, L = 6.8 µH, COUT = 10 µF, fSW = 500 kHz, IOUT = 1 A. The maximum system bandwidth is 80 kHz. Assuming to design the compensation network to achieve a system bandwidth of 70 kHz: fPOLE = 2.7 kHz so accordingly with Eq. (33) and Eq. (35): (36) VOUT RLOAD = = 3.3Ω IOUT RC = 48.5kΩ ≈ 47kΩ CC = 237pF ≈ 270pF (37) (38) (39) The gain and phase bode diagrams are plotted respectively in Figure 40. Magnitude plot for example 2 and Figure 41. Phase plot for example 2. Figure 40. Magnitude plot for example 2 DS12861 - Rev 3 page 41/71 A6986H Compensation network design Figure 41. Phase plot for example 2 DS12861 - Rev 3 page 42/71 A6986H Application notes 7 Application notes 7.1 Output voltage adjustment The error amplifier reference voltage is 0.85 V typical. The output voltage is adjusted accordingly as per equation below: (see Figure 42. A6986H application circuit). R1 VOUT = 0.85 ⋅ (1 + ) R2 (40) Cr1 capacitor is sometimes useful to increase the small signal phase margin (please refer to Section 6.5 Compensation network design). Figure 42. A6986H application circuit uC RST 4 VIN 15 2 5 6 3 8 SYNCH RST VIN VBIAS VCC FSW MLF LX LX 13 14 VOUT Cr1 FB SS/INH 17 16 A6986H DELAY EP 1 COMP SGND PGND 10 11 Rc 7 PGND 12 R1 9 Cp Cc R2 signal GND Power GND 7.2 GND Switching frequency A resistor connected to the FSW pin features the selection of the switching frequency. The pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven floating in order to minimize the quiescent current from VIN. Please refer to Table 6. fSW selection TJ = - 40 to 135 °C, VIN= 12 V unless otherwise specified. to identify the pull-up / pull-down resistor value. fSW = 250 kHz / fSW = 500 kHz preferred codifications do not require any external resistor. 7.3 MLF pin A resistor connected to the MLF pin features the selection of the between low noise mode / low consumption mode and the different RST thresholds. The pinstrapping is performed at power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven floating in order to minimize the quiescent current from VIN. Please refer to Table 7. LNM/ LCM selection (A6986H3V3) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified., Table 8. LNM/ LCM selection (A6986H5V) TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified., and Table 9. LNM/ LCM selection (A6986H) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified. to identify the pull-up / pull-down resistor value. (LNM, RST threshold 93%) / (LCM, RST threshold 93%) preferred codifications don't require any external resistor. 7.4 Voltage supervisor The embedded voltage supervisor (composed of the RST and the DELAY pins) monitors the regulated output voltage and keeps the RST open collector output in low impedance as long as the VOUT is out of regulation. In order to ensure a proper reset of digital devices with a valid power supply, the device can delay the RST assertion with a programmable time. DS12861 - Rev 3 page 43/71 A6986H Voltage supervisor Figure 43. Voltage supervisor operation The comparator monitoring the FB voltage has four different programmable thresholds (80%, 87%, 93%, 96% nominal output voltage) for high flexibility (see Section 7.3 MLF pin, Table 7. LNM/ LCM selection (A6986H3V3) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified., Table 8. LNM/ LCM selection (A6986H5V) TJ = -40 to 135 °C, VIN = 12 V unless otherwise specified., and Table 9. LNM/ LCM selection (A6986H) TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.). When the RST comparator detects the output voltage is in regulation, a 2 mA internal current source starts to charge an external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then released as soon as VDELAY = 1.234 V (see Figure 43. Voltage supervisor operation). The CDELAY is dimensioned as follows: CDELAY = ISSCH ⋅ TDELAY 2μA ⋅ TDELAY = VDELAY 1.234V (41) The maximum suggested capacitor value is 270 nF. The A6986H also activates internal pull-down on RST pin in case overvoltage protection is triggered. As soon as the output voltage goes below OVP threshold (20% typ.), the 2 µA internal current source starts to charge an external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then released as soon as VDELAY = 1.234 V(see figure below). DS12861 - Rev 3 page 44/71 A6986H Synchronization (LNM) Figure 44. Voltage supervisor operation during OVP 7.5 Synchronization (LNM) The synchronization feature helps the hardware designer to prevent beating frequency noise that is an issue when multiple switching regulators populate the same application board. 7.5.1 Embedded master - slave synchronization The A6986H synchronization circuitry features the same switching frequency for a set of regulators simply connecting their SYNCH pin together, so preventing beating noise. The master device provides the synchronization signal to the others since the SYNCH pin is I/O able to deliver or recognize a frequency signal. For proper synchronization of multiple regulators, all of them have to be configured with the same switching frequency (see Table 6. fSW selection TJ = - 40 to 135 °C, VIN= 12 V unless otherwise specified.), so the same resistor connected at the FSW pin. In order to minimize the RMS current flowing through the input filter, the A6986H device provides a phase shift of 180° between the master and the SLAVES. If more than two devices are synchronized, all slaves will have a common 180° phase shift with respect to the master. Considering two synchronized A6986H which regulate the same output voltage (i.e.: operating with the same duty cycle), the input filter RMS current is optimized and is calculated as: IRMS = IOUT ⋅ 2D ⋅ (1 − 2D) 2 IOUT ⋅ (2D − 1) ⋅ (2 − 2D) 2 ifD < 0.5 (42) ifD > 0.5 The graphical representation of the input RMS current of the input filter in the case of two devices with 0° phase shift (synchronized to an external signal) or 180° phase shift (synchronized connecting their SYNCH pins) regulating the same output voltage is provided in the figure below. To dimension the proper input capacitor please refer to Section 7.6.1 Input capacitor selection). DS12861 - Rev 3 page 45/71 A6986H Synchronization (LNM) Figure 45. Input RMS current RMS current normalized (Irms/IOUT) 0.5 0.4 two regulators operating in phase 0.3 two regulators operating out of phase 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1 Duty cycle Figure 46. Two regulators not synchronized shows two not synchronized regulators with unconnected SYNCH pin. Figure 46. Two regulators not synchronized Figure 47. Two regulators synchronized shows the same regulators working synchronized having the SYNCH pins connected. The MASTER regulator (LX_reg2 trace) delivers the synchronization signal to the SLAVE device (LX_reg1). The SLAVE regulator works in phase with the synchronization signal, which is out of phase with the MASTER switching operation. DS12861 - Rev 3 page 46/71 A6986H Synchronization (LNM) Figure 47. Two regulators synchronized 7.5.2 External synchronization signal Multiple A6986H can be synchronized to an external frequency signal fed to the SYNCH pin. In this case the regulator set is phased to the reference and all the devices will work with 0° phase shift. The minimum synchronization pulse width is 100 ns and the frequency range of the synchronization signal is: • [275 kHz - 1.4 MHz] if fSW_PROGRAMMED < 500 kHz • [475 kHz - 2.2 MHz] if fSW_PROGRAMMED ≥ 500 kHz (see Figure 48. Synchronization pulse definition). Figure 48. Synchronization pulse definition 275 kHz < fSYNCHRO < 1.4 MHz if fSW_PROGRAMMED < 500 kHz typ 475 kHz < fSYNCHRO < 2.2 MHz if fSW_PROGRAMMED ≥ 500 kHz typ fSYNCHRO 100 nsec. min. fSYNCHRO 100 nsec. min. Since the internal slope compensation contribution that is required to prevent subharmonic oscillations in peak current mode architecture depends on the oscillator frequency, it is important to select the same oscillator frequency for all regulators (all of them operate as SLAVE) as close as possible to the frequency of the reference signal (please refer to Table 6. fSW selection TJ = - 40 to 135 °C, VIN= 12 V unless otherwise specified.). As a consequence all the regulators have the same resistor value connected to the FSW pin, so the slope compensation is optimized accordingly with the frequency of the synchronization signal. The slope compensation contribution is latched at power-up and so fixed during the device operation. DS12861 - Rev 3 page 47/71 A6986H Synchronization (LNM) The A6986H normally operates in the MASTER mode, driving the SYNCH line at the selected oscillator frequency as shown in Figure 49. A6986H synchronization driving capability and Figure 46. Two regulators not synchronized. In the SLAVE mode the A6986H sets the internal oscillator at 250 kHz typ. (see Table 6. fSW selection TJ = - 40 to 135 °C, VIN= 12 V unless otherwise specified.) and drives the line accordingly. Figure 49. A6986H synchronization driving capability In order to safely guarantee that each regulator recognizes itself in SLAVE mode when synchronized, the external master must drive the SYNCH pin with a clock signal frequency higher than the maximum oscillator spread of the selected line in Table 6. fSW selection TJ = - 40 to 135 °C, VIN= 12 V unless otherwise specified.for at least 10 internal clock cycles. Once recognized as SLAVE the synchronization range is: • 275 - 1.4 MHz if fSW < 500 kHz • 475 kHz - 2.2 MHz if fSW >=500 kHz example 1: selecting RFSW = 0 Ω to VCC Table 13. Example of oscillator frequency selection Symbol RVCC (E24 series) RGND (E24 series) fSW min. fSW typ. fSW max. fSW NC 0Ω 225 250 275 the device enters in slave mode after 10 pulses at frequency higher than 275 kHz and so it is able to synchronize to a clock signal in the range 275 kHz - 1.4 MHz (see Figure 48. Synchronization pulse definition). Example 2: selecting RFSW = 0 Ω to GND Table 14. Example of oscillator frequency selection (2) DS12861 - Rev 3 Symbol RVCC (E24 series) RGND (E24 series) fSW min. fSW typ. fSW max. fSW NC 0Ω 450 500 550 page 48/71 A6986H Synchronization (LNM) The device enters in slave mode after 10 pulses at frequency higher than 550 kHz and so it is able to synchronize to a clock signal in the range 475 kHz - 2.2 MHz (see Figure 48. Synchronization pulse definition). As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the slope compensation is dimensioned accordingly with FSW resistors so it is important to limit the switching operation around a working point close to the selected oscillator frequency (FSW resistor). As a consequence, to guarantee the full output current capability and to prevent the subharmonic oscillations, the MASTER may limit the driving frequency range within ± 5% of the selected frequency. A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the peak current capability (see IPK parameter in Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.) since the internal slope compensation signal may be saturated. The device keeps operating in slave mode as far as the master is able to drive the SYNCH pin faster than 275 kHz, otherwise the A6986H goes back into MASTER mode at the programmed RFSW oscillator frequency after successfully driving one pulse 250 kHz typ. (see Figure 50. Slave-to-master mode transition) in the SYNCH line. Figure 50. Slave-to-master mode transition The external master can force a latched SLAVE mode driving the SYNCH pin low at power-up, before the softstart begins the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event is triggered regardless FSW resistor value, that otherwise counts to design the slope compensation. The same considerations above are also valid. The master driving capability must be able to provide the proper signal levels at the SYNCH pin (see Table 5. Electrical characteristics TJ = - 40 to 135 °C, VIN = 12 V unless otherwise specified.): DS12861 - Rev 3 • Low level < VSYN THL = 0.7 V sinking 5 mA • High level > VSYN THH = 1.2 V sourcing 0.7 mA page 49/71 A6986H Design of the power components Figure 51. Master driving capability to synchronize the A6986H 7.6 7.6.1 Design of the power components Input capacitor selection The input capacitor voltage rating must be higher than the maximum input operating voltage of the application. During the switching activity a pulsed current flows into the input capacitor and so its RMS current capability must be selected accordingly with the application conditions. Internal losses of the input filter depends on the ESR value so usually low ESR capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher conversion efficiency. The maximum RMS input current flowing through the capacitor can be calculated as: D D IRMS = IOUT ⋅ (1 − ) ⋅ η η (43) Where IOUT is the maximum DC output current, D is the duty cycles, ƞ is the efficiency. This function has a maximum at D = 0.5 and, considering h = 1, it is equal to IOUT/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as: VOUT + ΔVLOWSIDE DMAX = VINMIN + ΔVLOWSIDE − VINMIN + ΔVHIGHSIDE (44) VOUT + ΔVLOWSIDE DMIN = VINMAX + ΔVLOWSIDE − VINMIN + ΔVHIGHSIDE (45) Where DVHIGH_SIDE and DVLOW_SIDE are the voltage drops across the embedded switches. The peak-to-peak voltage across the input filter can be calculated as follows: IOUT D D CIN = ⋅ (1 − ) ⋅ + ESR ⋅ (IOUT + ΔIL) VPP ⋅ fSW η η (46) In case of negligible ESR (MLCC capacitor) the equation of CIN as a function of the target VPP can be written as follows: IOUT D D CIN = ⋅ (1 − ) ⋅ VPP ⋅ fSW η η (47) Considering ƞ=1 this function has its maximum in D = 0.5: IOUT CINMIN = 4 ⋅ VPPMAX ⋅ fSW (48) Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5% VIN_MAX. DS12861 - Rev 3 page 50/71 A6986H Design of the power components Table 15. Input capacitors Manufacturer TDK Taiyo Yuden 7.6.2 Series Size Cap value (µF) Rated voltage (V) C3225X7S1H106M 1210 10 50 C3216X5R1H106M 1206 - - UMK325BJ106MM-T 1210 - - Inductor selection The inductor current ripple flowing into the output capacitor determines the output voltage ripple (please refer to Section 7.6.3 Output capacitor selection). Usually the inductor value is selected in order to keep the current ripple lower than 20% - 40% of the output current over the input voltage range. The inductance value can be calculated by equation below: ΔIL = VIN − VOUT VOUT ⋅ TON = ⋅ TOFF L L (49) Where TON and TOFF are the on and off time of the internal power switch. The maximum current ripple, at fixed VOUT, is obtained at maximum TOFF that is at minimum duty cycle (see Section 7.6.1 Input capacitor selection to calculate minimum duty). So fixing ΔIL = 20% to 40% of the maximum output current, the minimum inductance value can be calculated: VOUT 1 − DMIN LMIN = ⋅ ΔILMAX fSW (50) where fSW is the switching frequency 1/(TON + TOFF). For example for VOUT = 3.3 V, VIN = 12 V, IOUT = 2 A and FSW = 500 kHz the minimum inductance value to have ΔIL = 30% of IOUT is about 8.2 µH. The peak current through the inductor is given by: ΔIL IL, PK = IOUT + 2 (51) So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit. In the table below, some inductor part numbers are listed. Table 16. Inductors Manufacturer Series Coilcraft XAL50xx XAL60xx 7.6.3 Inductor value (µH) 2.2 to 22 Saturation current (A) 6.5 to 2.7 12.5 to 4 Output capacitor selection The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output voltage ripple, that depends on the capacitor value and the equivalent resistive component (ESR). As a consequence the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. The voltage ripple equation can be calculated as: ΔILMAX ΔVOUT = ESR ⋅ ΔILMAX + 8 ⋅ COUT ⋅ fSW (52) Usually the resistive component of the ripple can be neglected if the selected output capacitor is a multi layer ceramic capacitor (MLCC). The output capacitor is important also for loop stability: it determines the main pole and the zero due to its ESR. (See Section 6 Closing the loop to consider its effect in the system stability). DS12861 - Rev 3 page 51/71 A6986H Design of the power components For example with VOUT = 3.3 V, VIN = 12 V, fSW = 500 kHz, ΔIL = 0.6 A, (resulting by the inductor value) and COUT = 20 µF MLCC : ΔVOUT ΔILMAX 1 1 0.6 7.5mV ⋅ )= = 0.23 % ≅ ⋅ =( VOUT VOUT COUT ⋅ fSW 3.3 8 ⋅ 20μF ⋅ 500kHz 3.3 (53) The output capacitor value has a key role to sustain the output voltage during a steep load transient. When the load transient slew rate exceeds the system bandwidth, the output capacitor provides the current to the load. In case the final application specifies high slew rate load transient, the system bandwidth must be maximized and the output capacitor has to sustain the output voltage for time response shorter than the loop response time. In Table 17. Output capacitors some capacitor series are listed. Table 17. Output capacitors Manufacturer Series Cap value (μF) Rated voltage (V) ESR (mΩ) GRM32 22 to 100 6.3 to 25