ALTAIR04-900

ALTAIR04-900 Off-line all-primary-sensing switching regulator Datasheet - production data • Low standby consumption • Overcurrent protection against transformer saturation and secondary diode short-circuit • SO16N package Applications SO16N • SMPS for energy metering • Auxiliary power supplies for 3-phase input industrial systems Features • AC-DC adapters • Optoless primary side constant voltage operations Description • Adjustable and mains-independent maximum output current for safe operations during overload/short-circuit conditions The ALTAIR04-900 is a high voltage all-primarysensing switcher, operating directly from the rectified mains with minimum external parts. It combines a high-performance low voltage PWM controller chip and a 900 V avalanche-rugged power section in the same package. • 900 V avalanche-rugged internal power section • Quasi-resonant valley switching operation Figure 1. Block diagram +V out +Vi n Is tart-up Vcc Int ernal s upply bus P ROT ECTION & FE EDFORWARD LOGI C DRA IN SUPP LY & UV LO V ref UV LO Prot IFF B LA NK ING TIME STA RT ER 3.3 V Rzcd ZCD/F B TURN -ON LOGI C Vc DE MAG LOGIC Q R LE B + S Rfb UV LO Q 1V Iref R - + S /H R S Q R Intern. s upply bus S - I FF - + Prot + 2.5 V RFF COMP IREF Rcomp GND Cref S OURCE Rsens e Cc om p October 2014 This is information on a product in full production. DocID18211 Rev 3 1/29 www.st.com Contents ALTAIR04-900 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 5.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.2 High voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 Zero-current detection and triggering block . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 Constant voltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 Constant current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.6 Voltage feed-forward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.7 Burst-mode operation (no load or very light load) . . . . . . . . . . . . . . . . . . 18 5.8 Soft-start and starter block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9 Hiccup-mode OCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.10 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 Test board: evaluation data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 Test board: main waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/29 DocID18211 Rev 3 ALTAIR04-900 1 Description Description This device combines two silicons in the same package: a low voltage PWM controller and a 900 V avalanche-rugged power section. The controller is in current-mode specifically designed for off-line quasi-resonant flyback converters. The device provides a constant output voltage using the primary-sensing feedback. This eliminates the need for the optocoupler, the secondary voltage reference, as well as the current sensor, still maintaining an accurate regulation. Besides, the maximum deliverable output current can be set so to increase the end-product safety and reliability during fault events. Quasi-resonant operation is guaranteed by a transformer demagnetization sensing input which turns on the power section. The same input also serves the output voltage monitoring, to perform CV regulation, and to achieve mains-independent maximum deliverable output current (line voltage feed-forward). The maximum switching frequency is top-limited 166 kHz, so that at light-to-medium load a special function automatically lowers the operating frequency still maintaining the valley switching operation. When the load is very light, the device enters a controlled burst-mode operation that, along with the built-in high voltage start-up circuit and the low operating current, minimizes the standby power. Although an auxiliary winding is required in the transformer to correctly perform CV/CC regulation, the chip powers itself directly from the rectified mains. This is important during CC regulation, where the flyback voltage, generated by the winding, drops below UVLO threshold. However, if ultra low no-load input consumption is required to comply with the most strict energy-saving recommendations, then the device needs to be powered by the auxiliary winding. These functions optimize power handling under different operating conditions. The device offers protection features that, in auto restart-mode, increase end-product safety and reliability: • Auxiliary winding disconnection, or brownout • Detection • Shorted secondary rectifier, or transformer saturation DocID18211 Rev 3 3/29 29 Pin connection 2 ALTAIR04-900 Pin connection Figure 2. Pin connection (top view) Note: SOURCE 1 16 DRAIN SOURCE 2 15 DRAIN Vcc 3 14 DRAIN GND 4 13 DRAIN IREF 5 12 N.C. ZCD/FB 6 11 N.A. COMP 7 10 N.A. N.A. 8 9 N.A. The copper area has to be placed under the drain pins to dissipate heat. Table 1. Pin functions Number 1, 2 Function Power section source and input to the PWM comparator. The current, flowing through MOSFET, is sensed by a resistor connected between the pin and GND. The resulting voltage is compared with an internal reference (0.75 V max.) to determine the MOSFET turn-off. The SOURCE pin is equipped with 250 ns blanking time, after the gate-drive output goes high for noise immunity. If a second comparison level located at 1 V is exceeded the IC is stopped and restarted after Vcc has dropped below 5 V. 3 Vcc Supply voltage of the device. An electrolytic capacitor, connected between this pin and ground, is initially charged by the internal high voltage start-up generator; when the device runs, the same generator keeps it charged if the voltage, supplied by the auxiliary winding, is not sufficient. This feature is disabled if a protection is tripped. Sometimes a small bypass capacitor (0.1 µF typ.) to GND might be useful to get a clean bias voltage for the signal part of IC. 4 GND Ground. Current return both for IC signal part and the gate-drive. All ground connections of bias components should be tied to a trace and kept separated from any pulsed current return. IREF CC regulation loop reference voltage. An external capacitor has to be connected between this pin and GND. An internal circuit develops a voltage on this capacitor used as the reference for peak drain current of the MOSFET during CC regulation. The voltage is automatically adjusted to keep the average output current constant. 5 4/29 Name DocID18211 Rev 3 ALTAIR04-900 Pin connection Table 1. Pin functions (continued) Number Name Function 6 ZCD/FB Transformer demagnetization sensing for quasi-resonant operation. Input/output voltage monitoring. A negative-going edge triggers the MOSFET turn-on. The current sourced by the pin during on-time is monitored to compensate the internal delay of the current sensing circuit and achieve a CC regulation independent of the mains voltage. If this current does not exceed 50 µA, either a floating pin or a low input voltage is assumed, the device is stopped and restarted after Vcc has dropped below 5 V. Besides, the pin voltage is sampled-and-held right at the end of the transformer demagnetization to get an accurate image of the output voltage to be fed to the inverting input of the internal transconductance-type error amplifier, whose non-inverting input is 2.5 V. The maximum IZCD/FB sunk/sourced current doesn’t exceed ±2 mA (AMR) in all Vin range conditions. No capacitor is allowed between the pin and the auxiliary transformer. 7 COMP Output of the internal transconductance error amplifier. The compensation network is placed between this pin and GND to achieve stability and good dynamic performance of the voltage control loop. 8-11 N.A Not available. These pins must be left not connected. 12 N.C Not internally connected. 13 to 16 DRAIN Drain connection of the internal power section. The internal high voltage start-up generator sinks current from these pins as well. Pins are connected to the internal metal frame to facilitate heat dissipation. DocID18211 Rev 3 5/29 29 Maximum ratings ALTAIR04-900 3 Maximum ratings 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol VDS ID Pin 1,2, 13-16 Drain-to-source (ground) voltage Value Unit -1 to 900 V 0.7 A 25 mJ 1,2, 13-16 Drain current Single pulse avalanche energy (Tj = 25 °C, ID = 0.7 A) Eav 1,2, 13-16 Vcc 3 Supply voltage (Icc < 25 mA) Self limiting V IZCD/FB 6 Zero-current detector current ±2 mA Vcomp 8 Analog input -0.3 to 3.6 V 0.9 W Junction temperature range -40 to 150 °C Storage temperature -55 to 150 °C Ptot Power dissipation @TA = 50 °C Tj Tstg 3.2 Parameter Thermal data Table 3. Thermal data Symbol 6/29 Parameter Max. value Rthj-pin Thermal resistance, junction-to-pin 10 Rthj-amb Thermal resistance, junction-to-ambient 110 Unit °C/W DocID18211 Rev 3 ALTAIR04-900 4 Electrical characteristics Electrical characteristics (TJ = -40 to 125 °C, Vcc = 14 V; unless otherwise specified) Table 4. Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Power section V(BR)DSS Drain-source breakdown IDSS RDS(on) Coss ID< 100 µA; Tj = 25 °C 900 V VDS = 850 V; Tj = 125 °C (See Figure 4 and note) Off-state drain current 80 Id=250 mA; Tj = 25 °C Drain-source on-state resistance 16 Id=250 mA; Tj = 125 °C Effective (energy-related) output capacitance 19 µA Ω 38 (See Figure 3) High voltage start-up generator VStart Min. drain start voltage Icharge < 100 µA 40 50 60 5.5 7 Vcc start-up charge current VDRAIN> VStart; Vcc < VccOn Tj = 25 °C 4 Icharge mA VDRAIN> VStart; Vcc < VccOn (1) VCCrestart Vcc restart voltage (Vcc falling) V +/-10% 9.5 10.5 11.5 V After protection tripping 5 Supply voltage Vcc Operating range After turn-on VccOn Turn-on threshold (1) 12 VccOff Turn-off threshold (1) Zener voltage Icc = 20 mA VZ 11.5 23 V 13 14 V 9 10 11 V 23 25 27 V (See Figure 5) 200 300 µA Supply current Iccstart-up Start-up current Iq Quiescent current (See Figure 6) 1 1.4 mA Icc Operating supply current @ 50 kHz (See Figure 7) 1.4 1.7 mA Fault quiescent current During hiccup and brownout (See Figure 8) 250 350 µA 100 125 175 µs 400 500 700 µs Iq(fault) Start-up timer TSTART Start timer period TRESTART Restart timer period during burst-mode DocID18211 Rev 3 7/29 29 Electrical characteristics ALTAIR04-900 Table 4. Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit Zero-current detector IZCDb Input bias current VZCD = 0.1 to 3 V 0.1 1 µA VZCDH Upper clamp voltage IZCD = 1 mA 3.0 3.3 3.6 V VZCDL Lower clamp voltage IZCD = - 1 mA -90 -60 -30 mV VZCDA Arming voltage Positive-going edge 100 110 120 mV VZCDT Triggering voltage Negative-going edge 50 60 70 mV IZCDON Min. source current during MOSFET on-time -25 -50 -75 µA TBLANK Trigger blanking time after MOSFET turn-off VCOMP ≥ 1.3 V 6 VCOMP = 0.9 V 30 IZCD = 1 mA 45 µs Line feed-forward RFF Equivalent feed-forward resistor Ω Transconductance error amplifier Tj = 25 °C (1) 2.46 Tj = -40 to 125 °C and Vcc = 12 V to 23 V (1) 2.42 1.3 VREF Voltage reference gm Transconductance ΔICOMP = ±10 µA VCOMP = 1.65 V Gv Voltage gain Open loop GB Gain-bandwidth product 2.5 2.54 V 2.58 2.2 3.2 mS 73 dB 500 KHz Source current VZCD = 2.3 V, VCOMP = 1.65 V 70 100 µA Sink current VZCD = 2.7 V, VCOMP = 1.65 V 400 750 µA VCOMPH Upper COMP voltage VZCD = 2.3 V 2.7 V VCOMPL Lower COMP voltage VZCD = 2.7 V 0.7 V 1 V 65 mV ICOMP VCOMPBM Burst-mode threshold Hys Burst-mode hysteresis Current reference VIREFx GI VCREF Maximum value VCOMP = VCOMPL (1) 1.5 1.6 1.7 Current loop gain VCOMP = VCOMPH 0.5 0.6 0.7 0.38 0.4 0.42 V 200 250 300 ns Current reference voltage V Current sense tLEB td(H-L) VCSx VCSdis Leading-edge blanking Delay-to-output 300 Max. clamp value dVcs/dt = 200 mV/µs Hiccup-mode OCP level (1) 1. Parameters track one to each other 8/29 DocID18211 Rev 3 (1) ns 0.7 0.75 0.8 V 0.92 1 1.08 V ALTAIR04-900 Electrical characteristics Figure 3. COSS output capacitance variation 500 C OSS (pF) 400 300 200 100 0 0 25 50 75 100 125 150 V DS (V) Figure 4. Off-state drain and source current test circuit I q(f ault ) 1 5V A Vc c 2. 5V F B/ Z C D I dss D R AI N + C U R R EN T C ON TR OL C OMP Note: A I R EF GN D 850 V S OU R C E The measured IDSS is the sum between the current across the start-up resistor and the MOSFET off-state drain current. Figure 5. Start-up current test circuit ,F FVW DUWXS $   9 9 FF  9 ' 5 $,1 & 85 5 (1 7 & 21 75 2/ ) % = & ' & 203 ,5 () DocID18211 Rev 3 *1' 628 5 & ( 9/29 29 Electrical characteristics ALTAIR04-900 Figure 6. Quiescent current test circuit , TB PH DV $  9 9FF '5 $, 1  9 & 85 5 (1 7 & 21 75 2/ ) % = & '  N & 2 03 , 5 () *1 ' 62 85 & (  9 9 N  9 Figure 7. Operating supply current test circuit , FF $   N :  9 N 9FF  N ' 5 $, 1  9 & 85 5 (1 7 & 21 75 2/ )% = & '  N  N  9 & 2 03 , 5 ()  *1' 6 28 5 & (     9  N+ ] 9 Note: The circuit across the ZCD pin is used for the switch-on synchronization. Figure 8. Quiescent current during fault test circuit , TI DX OW  $ 9 9 FF  9 ' 5 $,1 & 85 5 (1 7 & 21 75 2/ ) % = & ' & 203 10/29 DocID18211 Rev 3 ,5 () *1' 628 5 & ( ALTAIR04-900 5 Application information Application information The device is an all-primary-sensing switching regulator, based on quasi-resonant flyback topology. According to the load conditions of the converter, the device can work in different modes (see Figure 9): 1. QR-mode at heavy load. Quasi-resonant operation synchronizes MOSFET turn-on and the demagnetization of the transformer by detecting the resulting negative-going edge of the voltage across any winding of the transformer. The system works close to the boundary between discontinuous (DCM) and continuous conduction (CCM) of the transformer. Therefore, the switching frequency is different according to different line/load conditions (see the hyperbolic-like portion of the curves in Figure 9). Minimum turn-on losses, low EMI emissions and safe behavior in short-circuit are the main benefits of this operation. 2. Valley-skipping-mode at light-to-medium load. According to voltage on COMP pin, the device defines the maximum operating frequency of the converter. As the load is reduced, MOSFET turn-on doesn’t occur on the first valley but on the second one, the third one and so on. In this manner, the switching frequency doesn’t rise (piecewise linear portion in Figure 9). 3. Burst-mode with or without very light load. When the load is extremely light or disconnected, the converter enters a controlled on/off operation with a constant peak current. Decreasing the load results even few hundred hertz minimizes all frequencyrelated losses and makes it easier to comply with energy saving regulations or recommendations. Being the peak current very low, no issue of audible noise arises. Figure 9. Multi-mode operation of the ALTAIR04-900 f osc Input voltage f sw Valley-skipping mode Burst-mode Quasi-resonant mode 0 Pin DocID18211 Rev 3 Pinmax 11/29 29 Application information 5.1 ALTAIR04-900 Power section and gate driver The power section guarantees the safe avalanche operation within the specified energy rating as well as high dv/dt capability. The MOSFET has a V(BR)DSS of 900 V min. and a typical RDS(on) of 16 Ω. The gate driver is designed to supply a controlled gate current during both turn-on and turnoff in order to minimize common-mode EMI. Under UVLO conditions, an internal pull-down circuit holds the gate low in order to ensure that the MOSFET cannot be turned on accidentally. 5.2 High voltage start-up generator Figure 10 shows the internal schematic of the high voltage start-up generator (HV generator). The HV current generator is supplied through the DRAIN pin and it is enabled only if the input bulk capacitor voltage is higher than VStart threshold, 50 VDC typically. When the HV current generator is on, the Icharge current (5.5 mA typical value) is delivered to the capacitor on the Vcc pin. With reference to the timing diagram in Figure 10, when power is applied to the circuit and the voltage on the input bulk capacitor is high, the HV generator is sufficiently biased to start operating, thus it draws about 5.5 mA (typical) from the bulk capacitor. This current charges the bypass capacitor connected between the Vcc pin and ground and rises its voltage linearly. As the Vcc voltage reaches the start-up threshold (13 V typ.) the chip starts operating, the internal MOSFET is enabled to switch and the HV generator is cut off by the Vcc_OK signal asserted high. The IC is powered by the energy stored in the Vcc capacitor. The chip powers itself directly from the rectified mains: when the voltage on the Vcc pin falls below Vccrestart (10.5V typ.), during each MOSFET off-time, the HV current generator turns on and charges the supply capacitor until it reaches the VccOn threshold. In this manner, the self-supply circuit develops a high voltage to sustain the operation of the device. This feature is useful during CC regulation, when the flyback voltage generated by the auxiliary winding alone, may not be able to keep Vcc above Vcc restart. At converter power-down, the system loses regulation as soon as the input voltage falls below VStart. This avoids converter restart attempts and assures monotonic output voltage decay at system power-down. 12/29 DocID18211 Rev 3 ALTAIR04-900 Application information Figure 10. Timing diagram: normal power-up and power-down sequences Vin V Start Vcc t VccON Vccresta rt t DRAIN I charg e tt 5.5 mA Normal operation CV mode Power-on t Power-off Zero-current detection and triggering block The zero-current detection (ZCD) and triggering blocks switch on the MOSFET if a negative-going edge falling below 50 mV is applied to the ZCD/FB pin. The triggering block must be previously armed by a positive-going edge exceeding 100 mV. This feature detects transformer demagnetization for QR operation, where the signal for ZCD input is obtained by the transformer auxiliary winding, also used to supply the IC. Figure 11. ZCD block, triggering block R zcd ZCD/FB ZCD CLAMP BLAN KIN G TI ME STAR TER Rf b Aux TU RN -ON LOGI C 110mV 60mV S + 5.3 Normal operation CC mode Q Fr om CC /CV Block LEB To D riv er R F rom OC P The triggering block is blanked after MOSFET turn-off to prevent any negative-going edge, following leakage inductance demagnetization, from triggering the ZCD circuit erroneously. This blanking time is dependent on the voltage on COMP pin: it is TBLANK = 30 µs for VCOMP = 0.9 V, and decreases almost linearly down to TBLANK = 6 µs for VCOMP = 1.3 V. The voltage on the pin is both top and bottom-limited by a double clamp, as illustrated in the internal diagram of ZCD block (see Figure 11). The upper clamp is typically 3.3 V, while the lower clamp is -60 mV. The interface between the pin and the auxiliary winding is a resistor DocID18211 Rev 3 13/29 29 Application information ALTAIR04-900 divider. Its resistance ratio as well as the individual resistance values have to be properly chosen (see “Section 5.4: Constant voltage operation” and “Section 5.6: Voltage feedforward block”). The maximum IZCD/FB sunk/sourced current must not exceed ±2 mA (AMR) in all Vin range conditions. No capacitor is allowed between ZCD pin and the auxiliary transformer. The switching frequency is 166 kHz top-limited, as the converter operating frequency can increase excessively at light load and on high input voltage. A starter block is also used to start up the system, that is, to turn on the MOSFET during the converter power-up, when any or a very small signal is available on ZCD pin. The starter frequency is 2 kHz if COMP pin is below burst-mode threshold, 1 V, while it becomes 8 kHz if this voltage exceeds this value. After the first few cycles initiated by the starter, as the voltage developed across the auxiliary winding arms the ZCD circuit, MOSFET turn-on starts to be locked to transformer demagnetization, hence setting up QR operation. The starter is also active when the IC is in CC regulation and the output voltage is not so high to allow the ZCD triggering. If the demagnetization completes, hence a negative-going edge appears on ZCD pin, after a time exceeding TBLANK time, the MOSFET turns on again, with some delay to assure minimum voltage at turn-on. If, instead, the negative-going edge appears before TBLANK has elapsed, it is ignored and the first negative-going edge after TBLANK turns on the MOSFET. Therefore one or more drain ringing cycles are skipped (“valley-skipping-mode”, Figure 12) and the switching frequency cannot exceed 1/TBLANK. Figure 12. Drain ringing cycle skipping as the load is progressively reduced VDS VDS VDS t TON TFW t t TV Tosc Tosc Pin = Pin' ( limit condition) Tosc Pin = P in'' < Pin' P in = P in''' < P in'' When the system operates in valley-skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the MOSFET changes with discrete steps of one ringing cycle, while the off-time needed for cycle-bycycle energy balance may fall in between. Thus one or more longer switching cycles are compensated by one or more shorter cycles and vice versa. However, this mechanism is absolutely normal and there is no appreciable impact on the performance of the converter or on its output voltage. 14/29 DocID18211 Rev 3 ALTAIR04-900 Constant voltage operation The IC is specifically designed to work in the primary regulation and the output voltage is sensed through a voltage partition of the auxiliary winding, just before the auxiliary rectifier diode. Figure 13 shows the internal schematic of the constant voltage-mode and the external connections. Figure 13. Voltage control principle: internal schematic ZCD/FB - R zcd S/ H EA + + Aux 2. 5V Rf b To PWM Logic - 5.4 Application information D EMAG LOGI C CV F rom Rsense COMP R C Due to the parasitic wire resistance, the auxiliary voltage is representative of the output just when the secondary current becomes zero. For this purpose, the signal on ZCD/FB pin is sampled-and-held at the end of the transformer demagnetization to get an accurate image of the output voltage and it is compared with the error amplifier internal reference. The COMP pin is used for the frequency compensation: usually, an RC network, which stabilizes the overall voltage control loop, is connected between this pin and ground. The output voltage can be defined according to the following formula: Equation 1 V REF R FB = ------------------------------------------------------ ⋅ R ZCD N AUX -------------- ⋅ V OUT – V REF N SEC where NSEC and NAUX are the numbers of secondary and auxiliary turns respectively. RZCD value depends on the application parameters (see “Section 5.6: Voltage feed-forward block”). DocID18211 Rev 3 15/29 29 Application information 5.5 ALTAIR04-900 Constant current operation Figure 14 presents the principle used to control the average output current of a flyback converter. The output voltage of the auxiliary winding is used by the demagnetization block to generate the control signal for the switch Q1. R resistor absorbs a current VC/R, where VC is the voltage developed across the capacitor CREF. The flip-flop output is high as long as the transformer delivers current on the secondary side. This is shown in Figure 15. The capacitor CREF has to be chosen so that its voltage VC can be considered as a constant. Since it is charged and discharged by currents in the range of 10 µA (ICREF is typically 20 µA) at the switching frequency rate, a capacitance value in the range of 4.7-10 nF suits to switching frequencies of 10 kHz. The average output current can be expressed as follows: Equation 2 I N PRI G I ⋅ V CR EF OUT = ------------- ⋅ --------------------------------N SEC ( 2 ⋅ R SENSE ) where NPRI is the primary turn number. This formula shows that the average output current does not depend neither on the input or the output voltage, nor on transformer inductance values. The external parameters defining the output current, are the transformer ratio n and the sense resistor RSENSE. GI current loop gain and VCREF current reference voltage are internally defined. Figure 14. Current control principle . Ir ef To PWM Logic - Gi CC + R F rom R sense Q1 S R zcd ZCD/FB Q D EMAG LOGI C R Rfb Aux IREF C 16/29 DocID18211 Rev 3 ALTAIR04-900 Application information Figure 15. Constant current operation: switching cycle waveforms T IP t Is t Q t ICREF IC I CREF = − 5.6 VC R t Voltage feed-forward block The current control structure uses the voltage VC to define the output current, according to equation 2. Actually, the CC comparator is affected by Td an internal propagation delay, which switches off the MOSFET with a peak current higher than the foreseen value. This current overshoot is equal to: Equation 3 ∆IP = VIN ⋅ Td LP where LP is the primary inductance and it introduces an error on the calculated CC set point, depending on the input voltage. The device implements a line feed-forward function, which solves the issue by introducing an input offset voltage on the current sense signal, in order to adjust the cycle-by-cycle current limitation. The internal schematic is shown in Figure 16. DocID18211 Rev 3 17/29 29 Application information ALTAIR04-900 Figure 16. Feed-forward compensation: internal schematic DRAIN ZCD/FB F eedf orward Logic . Rfb Aux I FF CC Block - R zcd PWM LOGI C CC + Rff SOURCE Rsens e RZCD resistor can be calculated as follows: Equation 4 RZCD = NAUX LP ⋅ RFF ⋅ NPRI Td ⋅ RSENSE The peak drain current does not depend on the input voltage. Concerning RZCD value: during the MOSFET on-time, the current, sourced from ZCD/FB pin, IZCD, is compared with an internal reference current IZCDON ( - 50 µA typical). If IZCD < IZCDON, the brownout function is active and IC shuts down. This feature is important when the auxiliary winding is accidentally disconnected and considerably increases the end-product safety and reliability. 5.7 Burst-mode operation (no load or very light load) When the voltage on COMP pin falls 65 mV below a fixed threshold, VCOMPBM, the IC is disabled, the MOSFET is in off-state and its consumption reduced to a lower value to minimize Vcc capacitor discharge. Due to this condition, the converter operates in burst-mode (one pulse train every TSTART = 500 µs), with a minimum energy transfer. Therefore, the output voltage decreases: after 500 µs the controller switches on the MOSFET again and the sampled voltage on the ZCD pin is compared with the internal reference. If the voltage on the EA output, as a result of the comparison, exceeds the VCOMPL threshold, the device restarts switching, otherwise it is off for another period of 500 µs. The converter works in burst-mode with a nearly constant peak current. A load decrease causes a frequency reduction, which can go down even to few hundreds hertz, thus minimizing all frequency-related losses and meeting energy saving regulations. This kind of operation, shown in the timing diagrams (see Figure 17) along with the others previously described, is noise-free since the peak current is low. 18/29 DocID18211 Rev 3 ALTAIR04-900 Application information Figure 17. Load-dependent operating modes: timing diagrams COMP 65 mV hys ter. VCOMPL I DS TSTA R T Normal-mode 5.8 TS TA RT TS TA R T Burst-mode TST AR T Normal-mode Soft-start and starter block The soft-start feature is automatically implemented by the constant current block, as the primary peak current is limited on the CREF capacitor. During the startup, as the output voltage is zero, IC starts in CC-mode without high peak current operations. The voltage on the output capacitor increases slowly and the soft-start feature is assured. Actually the CREF value is not important to define the soft-start time, as its duration depends on other circuit parameters, such as: transformer ratio, sense resistor, output capacitors and load. The user can define the best appropriate value. DocID18211 Rev 3 19/29 29 Application information 5.9 ALTAIR04-900 Hiccup-mode OCP The device is also protected against short-circuit of the secondary rectifier, short-circuit on the secondary winding or a hard-saturated flyback transformer. A comparator monitors continuously the voltage on RSENSE and activates a protection circuitry if this voltage exceeds 1 V. To distinguish a malfunction from a disturbance (induced during ESD tests), the first time the comparator is tripped, the protection circuit enters a “warning state”. If in the following switching cycle the comparator is not tripped, a temporary disturbance is assumed and the protection logic is reset in its idle state; if the comparator is tripped again a real malfunction is assumed and the device stops. This condition is latched as long as the device is supplied. Any energy comes from the selfsupply circuit; hence the voltage on the Vcc capacitor decays and crosses the UVLO threshold after some time, which clears the latch. The internal start-up generator is still off, then the Vcc voltage still needs to go below its restart voltage before the Vcc capacitor is charged again and the device restarted. Finally, this results in a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the power circuit. This special condition is illustrated in the timing diagram of Figure 18. Figure 18. Hiccup-mode OCP: timing diagram Secondary diode is shorted here VCC VccON VccOF F Vccrest V SOU RCE Vcs dis t 1V t Two switching cycles V DS t 20/29 DocID18211 Rev 3 ALTAIR04-900 5.10 Application information Layout recommendations A proper printed circuit board layout is very important for the correct operation of any switchmode converter. Placing components carefully, routing traces correctly, appropriate trace widths and compliance with isolation distances are very important matters. In particular: • The compensation network should be connected as closer as possible to the COMP pin, keeping short the trace for the GND • Signal ground should be routed separately from power ground, as well as from the sense resistor trace Figure 19. Suggested routing for the converter 287 $&,1 $&,1 *1' '5$,1 9FF )%=&' &203 $/7$,5 *1' DocID18211 Rev 3 ,5() 6285&( 21/29 29 Typical applications 6 ALTAIR04-900 Typical applications Figure 20. Test board schematic: 4.5 W (9 V - 500 mA) wide range mains adapter  ' 7 / 9 $ X) 6736 / $& ,1 %5 5 & X) 9 /  : $& ,1 &  X) 9 5 N & Q) & X) & X) &  Q) 5  N X+ ' 677+ / *1' & ) ' 5 1   & X) 8 5 . )7 $/7$,5 9FF 9 ) %= & '  & 85 5(1 7 &21 752/  , 5() & 2 03 5 . &  '5 $,1 *1 '  Q)  9@                2XWSXW&XUUHQW>P$@ DocID18211 Rev 3      2XWSXW&XUUHQW>P$@ 23/29 29 Typical applications 6.2 ALTAIR04-900 Test board: main waveforms Figure 26. 110 VAC, no-load M: 400 s/div Figure 27. 264 VAC, no-load M: 400 s/div Figure 28. 110 VAC, full load M: 400 s/div 24/29 Figure 29. 234 VAC, full load M: 400 s/div DocID18211 Rev 3 ALTAIR04-900 7 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 30. SO16N drawings B* DocID18211 Rev 3 25/29 29 Package mechanical data ALTAIR04-900 Table 5. SO16N mechanical data mm Dim. Typ. Min. Max. A 1.55 1.43 1.68 A1 0.15 0.12 0.18 A2 1.52 1.48 1.56 b 0.40 0.375 0.425 c 0.238 D 9.85 9.82 9.88 E 6.00 5.90 6.10 E1 3.90 3.87 3.93 e 1.27 0.425 0.50 h L 0.635 0.585 0.685 k 4 2 8 ccc 0.04 Figure 31. SO16N footprint 26/29 DocID18211 Rev 3 ALTAIR04-900 8 Ordering information Ordering information Table 6. Ordering information Order codes Package ALTAIR04-900 Packaging Tube SO16N ALTAIR04-900TR Tape and reel DocID18211 Rev 3 27/29 29 Revision history 9 ALTAIR04-900 Revision history Table 7. Document revision history 28/29 Date Revision Changes 11-Nov-2010 1 Initial release 25-Jan-2011 2 Updated Chapter Table 4. on page 7 07-Oct-2014 3 Updated Table 2: Absolute maximum ratings, Section 4: Electrical characteristics and Section 7: Package mechanical data. Minor text changes. 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All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID18211 Rev 3 29/29 29