E-L9634

L9634 OCTAL INTELLIGENT SQUIB DRIVER ASIC PRELIMINARY DATA 1 ■ ■ ■ ■ ■ ■ FEATURES Figure 1. Package EIGHT SQUIB DEPLOYMENT DRIVERS DEPLOYMENT CURRENT AND TIME PROGRAMMABLE VIA SPI, (1.2A/2ms AND 1.75A/4ms) CAPABILITY TO DEPLOY WITH 1.47A (2.14A) UNDER 40V (21V) LOAD-DUMP CONDITION AND THE LOW SIDE MOS SHORTED TO -1V. 5.5MHZ SPI INTERFACE WITH MESSAGE VALIDATION 4 CHANNELS OF DISCRETE/SERIAL LOGIC ARMING INTERFACE PROGRAMMABLE VIA SPI DEPLOYMENT DRIVER SELFDIAGNOSTICS: – SHORT TO BATTERY/GROUND AND OPEN CIRCUIT – SQUIB RESISTANCE MEASUREMENT – SHORT BETWEEN CHANNELS DETECTIONS – HIGH AND LOW SIDE MOS TESTS – GROUND LOSS DETECTION -40 °C TO +85 °C OPERATING AMBIENT TEMPERATURE 4KV ESD CAPABILITY ON ALL OUTPUTDRIVER PINS AND 2KV ON ALL OTHERS Part Number t e l o L9634 2 ■ ■ d e t e ol o r P u d o r P e Table 1. Order Codes ) (s t c u ) s ( ct TQFP44 Package TQFP44 s b O DESCRIPTION The L9634 is an Octal Intelligent Squib Driver ASIC. It is packaged in a 44pin Thin Quad Flat Pack (TQFP) package and designed using ST's proprietary BCD4 technology. The UH30 is intended to deploy up to eight airbag squib circuits and provide diagnostics for each of the deployment drivers. Each of the eight drivers is sized to deliver up to 1.75A minimum for up to 4ms. The deployment current and time are both programmable via the SPI port s b O October 2004 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev. 1 1/36 L9634 Figure 2. Block Diagram MISO MOSI VRMEAS SCLK CS SPI IREF POR TEST/ DEPEN VDD Logic + ADC VRES2 VRES0 HSD HSD Isense SQH0 SQL0 GND0 ARM01/ ARMIN VRES1 Isense Diagnostic Diagnostic LSD LSD Isense Isense gnd0 Discrete / Serial Mode Discrete / Serial Mode HSD HSD SQH1 SQL1 Isense Diagnostic LSD ct Isense GND1 gnd0 du VRES4 o r P HSD Isense e t e l o s b O ARM45/ ARMCLK VRES5 SQH3 SQL3 Isense GND3 gnd0 VRES6 HSD Isense LSD LSD SQH6 SQL6 Isense gnd0 GND6 gnd0 Discrete / Serial Mode Discrete / Serial Mode HSD HSD SQH5 SQL5 gnd0 ARM67/ ARMOUT VRES7 Isense Diagnostic Diagnostic LSD LSD Isense GND5 ARM23/ ARMEN VRES3 LSD Diagnostic Isense 2/36 s b O Diagnostic Diagnostic Isense GND4 ) (s r P e t e l o SQH7 SQL7 Isense GND7 gnd0 ) s ( ct u d o GND2 gnd0 Isense SQH4 SQL4 SQH2 SQL2 L9634 VRES3 VRES2 SQH2 SQL2 GND2 VRMEAS GND1 SQL1 SQH1 VRES1 VRES0 Figure 3. Pin Connection (Top view) 44 43 42 41 40 39 38 37 36 35 34 SQH0 1 33 SQH3 SQL0 2 32 SQL3 GND0 3 31 GND3 ARMCLK / ARM45 4 30 SCLK ARMOUT / ARM67 5 29 MOSI ARMEN / ARM23 6 28 MISO ARMIN / ARM01 7 27 VDD TEST / DEPEN 8 26 IREF GND7 9 25 GND4 SQL7 10 24 SQL4 SQH7 11 23 12 13 14 15 16 17 18 19 20 21 22 ) s ( ct u d o r P e SQH4 let s ( t c VRES4 N° Pin 1 SQH0 High Side Driver Output for Channel 0 Out 2 SQL0 Low Side Driver Output for Channel 0 Out 3 GND0 4 ARMCLK ARM45 5 6 ARMOUT 7 r P e - ARM Serial Mode Clock Input In Discrete Arm Signal for Channel 4 & 5 In ARM Serial Mode Data Output t e l o Out Discrete Arm Signal for Channel 6 & 7 In ARMEN ARM Serial Mode Data Enable In ARM23 Discrete Arm Signal for Channel 2 & 3 In ARMIN ARM Serial Mode Data Input In ARM01 Discrete Arm Signal for Channel 0 & 1 In Test Input Pin In Deployment Enable In Power Ground 7 - TEST DEPEN 9 u d o Power Ground 0 I/O Type ARM67 bs O 8 Description SQH5 o s b O ) Table 2. Pin Function VRES5 SQL5 CS GND5 GND6 SQL6 SQH6 VRES6 VRES7 D04AT523 GND7 10 SQL7 Low Side Driver Output for Channel 7 Out 11 SQH7 High Side Driver Output for Channel 7 Out 12 VRES7 Reserve Voltage for Loop Channel 7 In 13 VRES6 Reserve Voltage for Loop Channel 6 In 14 SQH6 High Side Driver Output for Channel 6 Out 15 SQL6 Low Side Driver Output for Channel 6 Out 16 GND6 Power Ground 6 - 17 CS SPI Chip Select In 3/36 L9634 Table 2. Pin Function (continued) N° Pin Description I/O Type 18 GND5 Power Ground 5 19 SQL5 Low Side Driver Output for Channel 5 Out 20 SQH5 High Side Driver Output for Channel 5 Out 21 VRES5 Reserve Voltage for Loop Channel 5 In 22 VRES4 Reserve Voltage for Loop Channel 4 In 23 SQH4 High Side Driver Output for Channel 4 Out 24 SQL4 Low Side Driver Output for Channel 4 Out 25 GND4 Power Ground 4 26 IREF External Current Reference Resistor 27 VDD VDD Supply Voltage 28 MISO SPI Data Out 29 MOSI SPI Data In 30 SCLK SPI Clock 31 GND3 Power Ground 3 - - ) s ( ct Out In Out 32 SQL3 Low Side Driver Output for Channel 3 33 SQH3 High Side Driver Output for Channel 3 34 VRES3 Reserve Voltage for Loop Channel 3 35 VRES2 Reserve Voltage for Loop Channel 2 36 SQH2 High Side Driver Output for Channel 2 37 SQL2 Low Side Driver Output for Channel 2 38 GND2 Power Ground 2 39 VRMEAS 40 GND1 ro du P e o s b let In In - Out Out In In Out O ) Out - s ( t c Supply Voltage for Resistance Measurement In Power Ground 1 - du 41 SQL1 Low Side Driver Output for Channel 1 42 SQH1 High Side Driver Output for Channel 1 43 VRES1 Reserve Voltage for Loop Channel 1 In 44 VRES0 Reserve Voltage for Loop Channel 0 In e t e ol Out o r P Out Table 3. Absolute Maximum Ratings *) bs Symbol VDD O Parameter Value Unit Supply voltage -0.3 to 6.5 V VRMEAS voltage -0.3 to 40 V VRES voltage -0.3 to 40 V SQHX, SQLX squib high and low side drv Vin Discrete input voltage Tj Maximum junction temperature -1 to 40 V -0.3 to 6.5 V +150 °C *) Maximum ratings are absolute values: exceeding any one of these values may cause permanent damage to the integrated circuit. Table 4. Thermal Data Symbol Parameter Rthj-amb Thermal Resistance Junction to Ambient Rthj-case Thermal Resistance Junction to Case Tstg 4/36 Storage Temperature Value Unit 68 °C/W 14 °C/W -50 to +175 °C L9634 3 ELECTRICAL CHARACTERISTICS Table 5. Electrical Characteristics (VRES = 6.5 to 40V, VDD = 4.9 to 5.1V, VRMEAS = 7.0V to 26.5V, Tamb = -40°C to +95°C unless otherwise specified) Symbol VRST IDD VIH VIL Parameter Test Condition Min. VIH_DEPEN VIL_DEPEN VIL_TEST IPD VOH V mA Normal operation 5 Short to –1V on SQH 5 Short to –1V on SQL 5 Deployment 20 Input Logic = 1 2.0 Input Logic = 0 Input Leakage Current MOSI, SCLK VIN = VDD e t e ol VIN = 0 to VIH -1 DEPEN Input Voltage bs TEST Input Voltage O ) Input Pulldown Current ARMx, CS VIN = VIL to VDD DEPEN VIN = VIL to VDD Output Voltage MISO du IOH = -800µA o r P MISO Tri-State Current e t e ol s ( t c Pr V mV 1 µA 2.0 V 0.8 50 mV 8.5 V 10 50 µA 10 100 5.5 VDD– 0.8 IOL = 1.6mA V 0.4 MISO = VDD MISO = 0V ) s ( ct u d o 0.8 50 VOL IZ 4.7 VDD Input Current VHYS VIH_TEST Unit VDD drops until deployment drivers are disabled Input Voltage MOSI, SCLK, CS, ARMx 4.2 Max. VDD Internal Voltage Reset VHYS ILKG Typ. 10 µA 50 µA -10 Deployment Drivers DC specification s b O ILKG SQH Leakage ISTG ILKG VRESx Bias Current1 ILKG SQL Leakage VRMEAS=VDD=0, VRESx=36V, VSQH= 0V VRMEAS=18V; VDD=5V; VSQH= -1V -5 VRMEAS=18V; VDD=5V; VRESx=36V;SQH shorted to SQL mA 10 VRMEAS=Vdd=0, VSQL=18V -10 ISTG VRMEAS=18V; VDD=5V; VSQL= -1V -5 ISTB VRMEAS=18V; VDD=5V; VSQL= 18V 10 µA µA mA 5 mA SQL Pulldown Current VSQLx = 1.8V - VDD 500 700 µA SGth Short to Ground Threshold VDD = 5.0V 1.9 2.1 V SBth Short to Battery Threshold VDD = 5.0V 3.9 4.1 V IPD 5/36 L9634 Table 5. Electrical Characteristics (continued) (VRES = 6.5 to 40V, VDD = 4.9 to 5.1V, VRMEAS = 7.0V to 26.5V, Tamb = -40°C to +95°C unless otherwise specified) Symbol Parameter Test Condition Min. VDD = 5.0V Max. Unit 1.9 Typ. 2.1 V 100 300 mV 38 42 mA 45 55 mA OCth Open Circuit Threshold VI_th MOS Test Load Voltage Detection ISRC Resistance Measurement Current Source ISINK Resistance Measurement Current Sink RDSon Total High and Low Side On Resistance High Side MOS + Low Side MOS VRES = 6.9V; I = 1.2A @95°C 1.5 RDSon Total High and Low Side On Resistance High Side MOS + Low Side MOS VRES = 6.9V; IVRES = 1.1A @95°C 1.5 RDSon High Side MOS On Resistance VRES = 40V; IVRES = 1.1A; Ta = 95°C RDSon Low Side MOS On Resistance VRES = 40V; IVRES = 1.1A; Ta = 95°C Deployment Current (Channel 0, 3, 4, and 7) MOSI: Command Mode D11=0; RLOAD=3.75Ω; VRES=6.9 to 40V VDD = 5.0V; VRMEAS = 7.0V to 26.5V ) s ( ct Ω du o r P Ω 0.50 Ω 1.0 Ω 1.2 1.47 A MOSI: Command Mode D11=1; RLOAD=5.3Ω; VRES=12V to 21V 1.75 2.14 Low side MOS current limit (Channel 0, 3, 4, and 7) MOSI: Command Mode D11=1/ 0; RLOAD=5.3Ω; VSQH=18V 1.75 2.14 A Deployment Current (Channel 1, 2, 5, and 6) MOSI: Command Mode D11=0; RLOAD=3.75Ω; VRES=6.9 to 40V 1.34 1.64 A MOSI: Command Mode D11=1; RLOAD=5.3Ω; VRES=12V to 21V 1.95 2.39 Low side MOS current limit (Channel 1, 2, 5, and 6) MOSI: Command Mode D11=1/ 0; RLOAD=5.3Ω; VSQH=18V 1.95 2.39 A O Diagnostics Bias Current VSQH=0V; Part is configured to run in diagnostics mode via SPI -7 -4 IPD VBIAS Diagnostics Bias Voltage ISQH = -1.5mA 2.7 3.3 V RIREF IREF Resistance Threshold IDEPLOY ILIM IDEPLOY IBIAS RL_RANGE ADCACC ADCRES IPEAK 6/36 bs O ) s ( t c u d o r P e t e l o bs ILIM e t e ol Open Circuit 62.5 Short Circuit 2.5 Load Resistance Range %0000 0000 = 0.0Ω; %1111 1111 = 10.0Ω 0.0 ADC Accuracy 10.0 W RL = 4.0Ω to 10.0Ω 5 % RL = 0.0Ω to 4.0Ω 5 counts 2.0 IFINAL ADC Resolution MOS Transient Response Peak Current kΩ kΩ 8 See Figure 19 and Figure 20 bits L9634 Table 5. Electrical Characteristics (continued) (VRES = 6.5 to 40V, VDD = 4.9 to 5.1V, VRMEAS = 7.0V to 26.5V, Tamb = -40°C to +95°C unless otherwise specified) Symbol Parameter Test Condition Min. Typ. Max. Unit 20 µs µs Deployment Drivers AC Specification tPOR POR De-glitch Timer tON MOSs turn on time ARMx and DEPEN pins asserted Measured from falling edge CS to 90% of IFINAL; See Figure 19 and Figure 20 150 tsettle MOSs settling time ARMx and DEPEN pins asserted Measured from falling edge CS to 90% - 110% of IFINAL; See Figure 19 and Figure 20 300 tPULSE 5 Pulse Stretch Timer See “Pulse Stretch Timer table” 1. Not applicable during the diagnostic. 60 ms t e l o Figure 4. MOS Settling time and turn-on time 1 ) (s 0 r P e u d o ) s ( ct µs s b O t c u d e t e ol o r P s b O 7/36 L9634 Figure 5. MOS Settling time and turn-on time 2 ) s ( ct u d o Table 5. Electrical Characteristics Symbol Parameter Test Condition t e l o tP_ACC Pulse Stretch Timer Accuracy tGLITCH Pulse Stretcher De-glitch timer tDEPLOY Deployment Time 2; VRES = 6.9 - 40V (see table) ) (s s b O VRES = 12 – 21V3; (see table) tTIMEOUT d tFLT_DLY o r P e t e l -20 Max. Unit 20 % 25 µs 2 2.25 ms 4 4.5 10 Rmeas Current di/dt Typ. 5 Time from falling edge of CS until SPI diagnostic complete flag is set, in case of Short to GND for a single channel diagnostic. Fault Detection Filter2 ISLEW Min. t c u Diagnostic Bias Current Time r P e 2.5 ms 50 µs 40 mA/µs Resistance Measurement Time2 Duration when IDIAG_SRC and IDIAG_SINK are connected to SQH and SQL during a Resistance Measurement 2.5 ms tMOS_ON MOS test turn-on time2 On-time of a LS/HS driver during a MOS test 2.5 ms tDETECT MOS test detection window2 Time window to check for a LS/ HS MOS fault on a single loop 7.5 ms LS/HS MOS turn off propagation delay2 Time is measured from the valid LS/HS MOS condition to the LS/ HS turn off 10 µs Diagnostic Time3 For a single loop; MOS Test Disabled 5 ms For 8 loops MOS Tests Disabled 40 tRES o s b O tPROP_DLY tDIAG1 tDIAG_MULT 2. Application information only; not tested. 3. Time from Falling edge of CS until SPI “diagnostic” flag is set. 8/36 L9634 Table 6. SPI Timing (All SPI timing is performed with a 200pF load on MISO unless otherwise noted) Limits Min Max Item Symbol Parameter - fop Transfer Frequency 1 tSCK 2 tLEAD 3 tLAG 4 tSCLKHS 5 tSCLKLS 6 tSUS MOSI Input Setup Time 20 - 7 tHS MOSI Input Hold Time 20 - 8 tA MISO Access Time - 66 Unit dc 5.50 MHz SCLK Period 181 - ns Enable Lead Time 65 - ns Enable Lag Time 50 - ns SCLK High Time 65 - ns SCLK Low Time 65 - ns 9 tDIS MISO Disable Time (Note 1) - 100 10 tVS MISO Output Valid Time - 45 11 tHO MISO Output Hold Time (Note 1) 0 12 tRO Rise Time (Design Information) - 13 tFO Fall Time (Design Information) 14 tCSN CS Negated Time ) s ( ct ns du ns ns 30 ns - o r P 30 ns 100 - ns ete ol ns ns - ns Notes: 1. Parameters tdis and tho is measured with no additional capacitive load beyond the normal test fixture capacitance on the MISO pin. Additional capacitance during the disable time test erroneously extends the measured output disable time, and minimum capacitance on MISO is the worst case for output hold time. Figure 6. SPI Timing Diagram ) (s s b O t c u d e t e ol o r P s b O 9/36 L9634 Table 7. Arming Serial Mode Timing (All Arming serial mode timing is performed with a 50pF load on ARMOUT unless otherwise noted) Item Symbol - fop Transfer Frequency dc 2 Unit MHz 1 tARMCLK ARMCLK Period 500 ns 2 tLEAD Enable Lead Time 250 ns 3 tLAG Enable Lag Time 100 ns 4 tARMCLK_HS ARMCLK High Time 220 ns 5 tARMCLK_LS ARMCLK Low Time 220 ns 6 tSUS ARMIN Input Setup Time 30 ns 7 tHS ARMIN Input Hold Time 10 ns 8 tA ARMOUT Access Time 9 tVS ARMOUT Output Valid Time 10 tHO ARMOUT Output Hold Time 11 tRO Rise Time (Design Information) 12 tFO Fall Time (Design Information) 13 tARMEN_N ) (s t c u d e t e ol s b O 125 ete o r P 200 b O l o s ) s ( ct ns du 190 10 ARMEN Negated Time Figure 7. Arming Serial Mode Timing 10/36 Limits Min Max Parameter o r P ns ns 30 ns 30 ns ns L9634 4 CIRCUIT DESCRIPTION OSD is an integrated circuit to be used in air bag systems. Its main functions are deployment of the air bag and diagnostics of the SDM (Sensing Deployment Module). The OSD supports 8 de-ployment loops. The main features of OSD IC are: 8 deployment drivers sized to deliver 1.2A min for 2ms min at 40V max or 1.75A min for 4ms min at 21V max (current and time are internally limited while power supply is externally lim-ited). ● 10% accuracy for deployment current. ● 5% accuracy for deployment time. ● High side and Low side current limits programmable via SPI. ● Low-voltage internal reset ● 5.5MHz SPI Interface ● SPI Message Validation ● 4 discrete logic arming inputs ● High and low-side MOS tests ● Squib resistance measurement with 5% accuracy ● Short to -1V protection on all deployment loops (high and low side). ● Capability to deploy with 1.2A min under 40V load-dump condition and the low side MOS is shorted to -1V. ● Capability to deploy with 1.75A min under 21V condition and the low side MOS is shorted to -1V ● Capability to deploy with 1.75A min, when the high side MOS is shorted to 18V-battery and -1V ground difference. ● Capability to deploy the air bag with 1.2A min @ 6.9V VRES ● Deployment loops short to ground and short to battery detection ● Short between loops detection ● -40°C to +95°C ambient temperature ● Package: 44LD TQFP ● Technology: ST's proprietary BCD4 Process ● ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P 4.1 Power On Reset VDD loss of regulation detection is filtered for tPOR prior to issue an internal reset. This filter is intended to provide protection from short transients on VDD input. When VDD input voltage decreases below VRST for tPOR, OSD undergoes an internal reset. OSD keeps all current sinks and current sources, except the IPD, inactive and all outputs are driven to an inactive state and remains inactive as VDD decays down to 0V. When VDD rises above VRST, the outputs and the internal current sinks and current sources are enabled. When OSD is in reset, none of the outputs are momentarily turned on. e t e ol s b O 4.2 Deployment Drivers The on chip deployment drivers are sized to deliver IDEPLOY. Deployment current and period are programmable via SPI. The high side driver survives deployment condition 1 and 2 as defined here below. SQLx is shorted to ground (-1V) in these two conditions. Table 8. Deployment Survivability Conditions No. Drivers 1. SQHx 2. 3. SQLx Conditions IDEPLOY Voltage RLOAD 1.47A VRESx = 40V; SQLx = -1V 1.7Ω 2.5mS 2.14A VRESx = 21V; SQLx = -1V 1.7Ω 4.5mS 2.14A SQHx = 18V 1.7Ω 4.5mS Duration 11/36 L9634 The Low Side driver survives deployment condition 3 as defined above. Upon receiving a valid deployment condition, the respective SQH and SQL drivers are turned on. Also, SQH and SQL drivers are turned on momentarily during a MOS diagnostic. Otherwise, SQH and SQL are inactive under any normal, fault, or transient conditions. Upon a successful deployment of the respective SQH and SQL drivers, a deploy command success flag is asserted via SPI. Refer to Figure 4, Figure 5, Figure 6, and Figure 7. for the valid deployment condition and the "Deploy Command Success" timing. The following power-up conditions are considered as normal operations in OSD. VRES input can be connected to either a power supply output or an ignition voltage. VDD is connected to the 5V output of power supply. When VRES is connected to the power supply, VDD voltage will reach its regulation voltage before VRES voltage is stabilized. In this condition, OSD has a control of its internal logic and prevents an inadvertent turn-on of the drivers. When VRES is connected to the ignition, VRES voltage will be stabilized before VDD reach its regulation voltage. In this condition, all drivers are inactive. A pulldown on the gates of high side drivers (SQH) is provided to prevent these drivers from momentarily turning-on. ) s ( ct Any fault conditions on OSD does not turn on the SQH and SQL drivers. Only a valid deployment condition turns on the respective SQH and SQL drivers. u d o r P e 4.3 Arming Inputs The arming inputs serve as a fail-safe mechanism to prevent inadvertent deployment. Along with the SPI deployment bit, these inputs provide redundancy. These pins are used either as discrete outputs or as a serial data communication interface with 4-bit shift register. Pulse stretch timer is provided for each channel/loop. Either ARMx signal or SPI deployment bit starts the pulse stretcher. t e l o Figure 8. Arming Serial Mode Diagram ARM23/ARMEN ARM45/ARMCLK ARM01/ARMIN ct ) (s s b O spi.config1reg.d5 SPI Shift Register u d o LSB ARM67/ARMOUT MSB r P e When a valid deployment command is sent through the SPI, the pulse stretcher is initiated immediately following the falling edge of CS. When another valid deployment command is sent before the timer for the first command expired, the timer is refreshed. Sending an idle command terminates the pulse stretch timer operation. ONLY a timer operation started by a valid SPI deployment command is terminated. An idle command does not affect the timer operation started by ARM signal. OSD deploys a channel, ONLY when the respective ARM signal is asserted during a valid pulse stretcher signal. During the deployment, OSD turns on the respective high (SQH) and low side (SQL) drivers for tDEPLOY. Once deployment is initiated it can not be terminated. If one or more channels are deploying, OSD ignores all commands to the respective channels. The rest of the channels resume operation and respond to the SPI commands. Refer to Figure 5 for a deployment diagram initiated by a SPI deployment command. t e l o s b O In a discrete mode, when the ARM signal is asserted (active high), the pulse stretcher signal is asserted after the de-glitch filter time, tGLITCH, expires. The de-glitch filter is used to prevent noise from starting the pulse stretcher. The pulse stretcher timer, tPULSE, is initiated after a de-glitch time of the ARM falling edge. OSD deploys a channel, ONLY when the respective SPI deployment command is sent during a valid pulse stretcher signal. During the deployment, OSD turns on the respective high (SQH) and low side (SQL) drivers for tDEPLOY. When deployment is initiated it can not be stopped. Refer to Figure 4 and Figure 5 for a deployment diagram initiated by an ARM discrete signal. In serial mode, OSD latch the arm state for each channel from the shift register when ARMEN is negated. After the de-glitch filter time, tGLITCH, of the ARMEN falling edge expires, OSD starts the pulse stretch timer for the respective channel. Serial mode is selected by setting bit D5 in the Deployment Configuration Register 1 (see "Deployment Configuration Register 1 table 15"). OSD deploys a channel, ONLY when the respective SPI deployment command is sent during a valid pulse stretcher signal. During the deploy12/36 L9634 ment, OSD turns on the respective high (SQHx) and low side (SQLx) drivers for tDEPLOY. When deployment is initiated it can not be stopped. Refer to Figure 11 and Figure 12 for a deployment diagram initiated by an arming signal in serial mode. Figure 9. Discrete Mode: Deployment Sequence with Pulse Stretch Timer Enabled ARM_CMP De-glitch Pulse Stretch Timer tPULSE tPULSE tPULSE tPULSE tPULSE tPULSE t < tPULSE tPULSE ) s ( ct ARMx Status Flag 1 SPI CS Deploy 1 3 1 2 1 2 ms or 4ms 2 1 u d o 2 ms or 4ms r P e Deploy Status Flag t e l o Deploy Success Flag Valid Deployment Window Valid Deployment Window SPI CS Notes: 1: SPI Deploy Command 3 2: Clear Deploy Success Flag 3: SPI Idle Command ARMEN Notes: bs A: Arming Enable DEPEN input is assumed to be active in this sequence. Valid Deployment Window Valid Deployment Window B: Arming Disable O ) Figure 10. Discrete Mode: Deployment Sequence with Pulse Stretch Timer Disabled s ( t c ARM_CMP u d o De-glitch r P e Pulse Stretch Timer t e l o ARMx Status Flag bs SPI CS O Deploy 1 t < tPULSE 1 3 tPULSE 2 2 ms or 4ms tPULSE t < tPULSE 1 1 3 2 1 2 ms or 4ms Deploy Status Flag Deploy Success Flag Valid Deployment Window Valid Deployment Window Valid Deployment Window Valid Deployment Window SPI CS Notes: 1: SPI Deploy Command 2: Clear Deploy Success Flag 3: SPI Idle Command DEPEN input is assumed to be active in this sequence. 13/36 L9634 Figure 11. Serial Mode: Deployment Sequence with Pulse Stretch Timer Enabled ARMEN A B A B A B A B A B De-glitch Pulse Stretch Timer tPULSE tPULSE tPULSE tPULSE tPULSE tPULSE t < t PULSE tPULSE ARMx Status Flag 1 SPI CS Deploy 1 3 2 1 2 ms or 4ms 1 2 1 3 ) s ( ct 2 ms or 4ms Deploy Status Flag u d o Deploy Success Flag Valid Deployment Window Valid Deployment Window SPI CS Notes: 1: SPI Deploy Command 2: Clear Deploy Success Flag ARMEN Notes: A: Arming Enable 3: SPI Idle Command r P e Valid Deployment Window Valid Deployment Window B: Arming Disable t e l o DEPEN input is assumed to be active in this sequence. Figure 12. Serial Mode: Deployment Sequence with Pulse Stretch Timer Disabled ) (s s b O t c u d e t e ol o r P s b O 4.4 ARM01 / ARMIN In discrete mode, this pin acts as the ARM input channel 0 and channel 1. In serial mode, this pin acts as the input of Arming shift register. The ARMIN input takes data from the processor or another OSD while ARMEN is asserted. The MSB is the first bit of each word received on ARMIN. The LSB is the last bit of each word received on ARMIN. See Figure 8 below for Aming shift register. This pin has a TTL level compatible input voltages allowing proper operation with another devices using a 3.3V to 5.0V supply. 14/36 L9634 Figure 13. Arming Shift Register MSB LSB ARM01 ARM23 ARM45 ARM67 1 2 3 4 4.5 ARM23 / ARMEN In discrete mode, this pin acts as the ARM input channel 2 and channel 3. In serial mode, this pin acts as an active high input to select this device for serial transfers. This pin has a TTL level compatible input voltages allowing proper operation with another devices using a 3.3V to 5.0V supply. ) s ( ct While ARMEN is asserted, arming register data is shifted into the ARMIN pin and shifted-out of the ARMOUT pin on both rising and falling edges of ARMCLK. On the falling edge of ARMEN, OSD latch-in the bits from the shift register, and clear the shift register contents. u d o 4.6 ARM45 / ARMCLK In discrete mode, this pin acts as the ARM input channel 4 and channel 5. In serial mode, this pin acts as a clock input for serial communication. This pin has a TTL level compatible input voltages allowing proper operation with another devices using a 3.3V to 5.0V supply. r P e t e l o When ARMEN is asserted, on the rising or falling edge of ARMCLK the logic level input at the ARMIN pin is shifted into the internal Arming shift register. While MSB in the shift register is shifted-out on the ARMOUT pin. Serial data is shifted in and out of the shift register on each ARMCLK edge. When ARMEN is negated, OSD ignores ARMCLK signal. ) (s s b O A clock edge counter is provided to verify a valid serial arming communication. A valid serial arming communication contains (4n - 1) ARMCLK edges. Otherwise, OSD ignores the serial arming messages. t c u 4.7 ARM67 / ARMOUT In discrete mode, this pin acts as the ARM input channel 6 and channel 7. In serial mode, this pin acts as the output of Arming shift register. This pin has a TTL level compatible input voltages allowing proper operation with another devices using a 3.3V to 5.0V supply. d o r P When ARMEN is negated, ARMOUT pin is pulled down. When ARMEN is asserted, the MSB is the first bit of the nibble shifted onto ARMOUT. The LSB is the last bit shifted onto ARMOUT. e t e ol s b O 4.8 TEST / DEPEN (Deployment Enable) DEPEN is a deployment enable input, which is an active high input. When DEPEN is negated, it inhibits the high-side and the low-side MOSs from turning on. If DEPEN is negated when a valid deployment is received, OSD inhibits the deployment. If DEPEN is negated when a diagnostic command is received, OSD executes the diagnostic sequence. If a MOS diagnostic is executed while DEPEN is negated, OSD returns a low-side MOS fault. SPI remains functional while this pin is pulled low. When this pin is asserted, OSD is able to drive its high and low side drivers upon receiving a valid deployment command or a MOS diagnostic. DEPEN does not initiate a deployment nor terminate a deployment if it is already started. To enter a test mode, this pin has to be pulled higher than VIH_TEST. 4.9 Deployment Driver Diagnostics OSD runs an on-chip self-diagnostics when commanded via SPI. By default, OSD is in the monitor mode (D15 & D14 = %11). The on-chip diagnostic operates according to the flow chart shown in Figure 15. If a fault condition is detected, the state machine asserts a fault bit, which serves as a flag to the processor. Once a fault bit asserted, OSD terminates the diagnostic tests for that particular channel and start diagnostic tests on the next channel. The fault information in OSD is sent out through MISO. For diagnostic 15/36 L9634 mode SPI bit definition. OSD is able to differentiate short to battery, open circuit, and short to ground. A resistance measurement provides the resistance value of a load connected between SQH and SQL. MOS diagnostic verifies the functionality of the high and low side MOS. Refer to Figure 14 for the diagnostic diagram. A detailed operation for each test is described in sections below. Figure 14. Diagnostic Diagram OCth VIGN ISRC Diagnostics CS VBIAS IBIAS VRESx SBth s2 SCLK s1 ) s ( ct SQHx s0 SPI Data registers MISO MOSI ISINK A/D Converter SGth Figure 15. Diagnostic Flow Chart e t e ol s b O No ) (s Run On-chip Diagnostic Monitor Mode ct du Indicate Short to Battery ro P e t e l o s b O Indicate Open Circuit Yes Yes Short to Battery No Yes Open Circuit No Indicate Short to Ground Yes Short to Ground No Resistance Measurement Indicate No Fault No FET Test enabled Yes Indicate LS FET failed Yes LS FET failed Low Side Driver FET Test No Indicate HS FET failed Yes HS FET failed No 16/36 u d o SQLx 8 to 1 Mux High Side Driver FET Test IPD Pr GNDx gnd0 L9634 4.10 Short Between Loops Diagnostic OSD has a loop bias voltage that is multiplexed between the eight deployment loops. The bias voltage is pulled-up to VDIAG_BIAS. Each deployment loop is pulled to ground through a current sink, IPD. If one of these loops is shorted to the one that is biased, a "Short Between Loops" fault bit is asserted and reported via SPI. Refer to Figure 16 for Short Between Loops diagram. Short between loops test is initiated when OSD receives one of the following message: MOSI monitor mode message with bit D12 = '1,' bit D9 = '1,' and bit D8 = '1.' MOSI diagnostic mode message with bit D12 = '1' and bit D9 = '1.' The test terminates when OSD receives one of the following message: ● ● MOSI monitor mode message with bit D12 = '1,' bit D9 = '1,' and bit D8 = '0' ● MOSI diagnostic mode message with bit D12 = '1' and bit D9 = '0.' ● MOSI command mode with bit D7 through bit D0 = '0.' If the test is in progress, OSD will continue the test when any of the following messages is received: ● ● ● MOSI monitor mode, except the one with bit D12 = '1,' bit D9 = '1,' and bit D8 = '0' MOSI register mode t e l o VBIAS IBIAS VRES0 Off u d o r P e Figure 16. Short Between Loops Diagram SBth ) s ( ct s b O SQH0 )- SQL0 IPD s ( t c SGth Diagnostics du ol ete bs o r P Off gnd0 GND0 VRES1-7 SBth Off SQH1-7 SQL1-7 IPD SGth Off gnd0 GND1-7 O After a POR event, short between loop is disabled. Need to receive a SPI command to execute a short between loop diagnostic. 4.11 Short to Battery Diagnostic During a short to battery test, a current source referenced to VDD is connected to the SQHx. When no short to battery condition exists, SQHx and SQLx are equal to VDIAG_BIAS. If the voltage on SQHx is above SBth for tFLT_DLY, OSD will assert the short to battery fault. Refer to Figure 17 for a short to battery test diagram. 17/36 L9634 Figure 17. Short-to-Battery Diagnostic Diagram VBIAS IBIAS SBth VRESx Off SQHx Diagnostics SQLx IPD Off gnd0 ) s ( ct GNDx u d o 4.12 Open Circuit and Short to Ground Diagnostic During an open circuit or a short to ground test, a current source referenced to VDIAG_BIAS is connected to the SQHx. When no open circuit or short to ground condition exists, SQHx and SQLx are equal to VDIAG_BIAS. An open circuit fault is detected when SQHx voltage is at VDIAG_BIAS and the SQLx voltage is at ground potential. A short to ground is detected when SQLx voltage is at ground potential and the SQHx voltage is below the open circuit threshold, OCth. r P e t e l o Figure 18. Open Circuit and Short to Ground Diagnostic Diagram s b O VBIAS IBIAS ) (s OCth t c u Diagnostics d e t e ol o r P VRESx Off SQHx SQLx IPD SGth Off gnd0 GNDx The open circuit and short to ground conditions are summarized in the table below. A fault condition exists for at least tFLT_DLY before OSD sets the respective fault bit. s b O Table 9. Open Circuit / Short to Ground Fault Condition Comparator Output Condition OC SG 0 0 0 1 Short to Ground 1 0 Normal operation 1 1 Open Circuit Invalid State 4.13 Resistance Measurement In a resistance measurement test, OSD provides a current source, ISRC, on SQHx and a current sink, ISINK, on SQLx. The 8-bit ADC is multiplexed between the deployment loops. This ADC converts the voltage across the SQHx and SQLx. The conversion results is stored for SPI retrieval. Figure 19 shows the resistance measurement diagram. 18/36 L9634 Figure 19. Resistance Measurement Diagram VIGN ISRC VRESx Off SQHx to ADC SQLx ISINK IPD Off gnd0 ) s ( ct GNDx The ADC has a resolution of 8 bits and an accuracy of 5%. The ADC is robust to disruption that may occur due to adjacent loops short to 40V or -1V. u d o r P e 4.14 MOS Diagnostic During a MOS test, the IBIAS current source referenced to VBIAS is connected to the SQHx. In case of normal condition, SQHx and SQLx are equal to VBIAS. t e l o DEPEN pin is asserted in order to run a MOS diagnostic. If DEPEN pin is negated, OSD will inhibit the high/low side MOS from turning on. In this case, the MOS diagnostic is terminated after tDETECT is expired and the respective MOS fault bit is set. ) (s s b O 4.15 Low Side MOS Diagnostic Upon detection of the following conditions, OSD turns the low side driver off and terminates the diagnostic within the specified time, tPROP_DLY. t c u VSQL is less than SGth threshold voltage ● (VSQHx - VSQLx) is greater than VI_TH ● VSQH is greater than SBth threshold voltage Any of the above conditions are considered as a normal operation. Upon detection any of these conditions, OSD does not set the low side driver fault bits. ● d e t e ol o r P On a single channel, high-side and low-side MOS diagnostics is completed within tDETECT. A low-side MOS fault bit is only set when tDETECT is expired before any of the above conditions are detected. A fault detection filter, tFLT_DLY, is provided to protect against short-transients on SQH and SQL pins. See Figure 20 for MOS test diagram. s b O Figure 20. MOS Diagnostic Diagram SBth VBIAS IBIAS VRESx HS Gate Drive SQHx Diagnostics SQLx IPD SGth LS Gate Drive GNDx gnd0 19/36 L9634 4.16 High Side MOS Diagnostic Upon detection of the following conditions, OSD turns the high side driver off and terminate the diagnostic within the specified time, tPROP_DLY. VSQH is greater than SBth threshold voltage ● (VSQHx - VSQLx) is greater than VI_TH ● VSQL is less than SGth threshold voltage Any of the above conditions are considered as a normal operation. Upon detection any of these conditions, OSD does not set the high side driver fault bits. ● On a single channel, high-side and low-side MOS diagnostics are completed within tDETECT. A high-side MOS fault bit is only set when tDETECT is expired before any of the above conditions are detected. A fault detection filter, tFLT_DLY, is provided to protect against short-transients on SQH and SQL pins. See Figure 20 for MOS test diagram. ) s ( ct 4.17 Loss of Ground Diagnostic Loss of ground is detected when the power ground of a deployment loop has a high impedance/open connection to the ground. Each channel has a dedicated power ground and a dedicated loss of ground detection. Upon a detection of loss of ground condition, OSD inhibits a diagnostic and a deployment for the respective channel. The rest of the channels are not affected by a loss of ground condition on the other channels. A loss of ground condition does not affect a deployment or a pulse strech timer that is already started. u d o r P e t e l o A ground reference for OSD logic is connected to GND0 pin. When OSD detects a high impedance on this ground reference, OSD will go in reset mode. ) (s s b O 4.18 Serial Peripheral Interface (SPI) The OSD contains a serial peripheral interface consisting of Serial Clock (SCLK), Serial Data Out (MISO), Serial Data In (MOSI), and Chip Select (CS). This device is configured as an SPI slave. Figure 21. SPI Block Diagram e t e ol SCLK s b O t c u d o r P vdd Status Bits cs MISO Output Shift Register vss Input Shift Register MOSI CS 30µA LSB Control Bits MSB 4.19 Chip Select (CS) The CS input selects OSD for serial data transfers. This TTL-compatible input has an internal pull-down to command the de-asserted state should an open circuit condition occur When CS is asserted, the MISO pin is released from tri-state mode, and all status information is latched in the SPI shift register. While CS is asserted, register data is shifted in the MOSI pin and shifted out the MISO pin on each subsequent SCLK. When CS is negated, the MISO pin is tri-stated and the fault register reloaded (latched) with the current filtered status data. To allow sufficient time to reload the fault registers; the CS pin must remain negated for at least tCSN. CS must also be immune to spurious pulses as defined in the SPI Timing table (MISO may come out of tristate, but no status bits can be cleared and no control bits altered). Glitches on the CS line while SCLK is not running will be ignored, although the MISO pin may be enabled. In each valid CS, OSD allows 16-bit 20/36 L9634 SPI transfer. OSD ignores all SPI transfers, which are not a 16-bit transfer and issue a SPI fault response in the next valid CS. 4.20 Serial Clock (SCLK) The SCLK input is the clock signal input for synchronization of serial data transfer. This pin has TTL level compatible input voltages allowing proper operation with microprocessors using a 3.3 to 5.0 volt supply. When CS is asserted, both the SPI master and this device latch input data on the rising edge of SCLK. The SPI master typically shifts data out on the falling edge of SCLK, as does this device. 4.21 Serial Data Output (MISO) The MISO output pin is in a tri-state condition when CS is negated. When CS is asserted, the MSB is the first bit of the word transmitted on MISO and the LSB is the last bit of the word transmitted on MISO. This pin supplies a "rail to rail" output, so if interfaced to a microprocessor that is using a lower VDD supply, the appropriate microprocessor input pin shall not sink more than IOH and shall not clamp the MISO voltage to less than VOH(min) while the MISO pin is in a logic "1" state. ) s ( ct u d o 4.22 Serial Data Input (MOSI) The MOSI input takes data from the master microprocessor while CS is asserted. The MSB is the first bit of each word received on MOSI and the LSB is the last bit of each word received on MOSI. This pin has TTL level compatible input voltages allowing proper operation with micro-processors using a 3.3 to 5.0 volt supply. r P e t e l o s b O 4.23 SPI Transmission The SPI provides access to read/write to the registers internal to OSD. OSD responses to various commands summarized in the below table. OSD response to the previous command is sent in the next valid CS. ) (s Table 10. OSD SPI Response Mode Bits D15 D14 0 0 0 1 1 0 1 1 X X MOSI Command ct u d o Register Mode Mode Bits D15 r P e Command Mode MISO Response D14 0 0 Register Mode 0 1 Command Mode Diagnostic Mode 1 1 Status Response Monitor Mode 1 1 Status Response SPI Transmission Fault 1 0 SPI Fault Response t e l o s b O 4.24 SPI Bit Definition - MOSI Bit Figure 22. MOSI Bit Layout D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 MSB D4 D3 D2 D1 D0 LSB Table 11. MOSI Mode Bits Definition Bit D15 Bit D14 0 0 Description Register Mode 0 1 Command Mode 1 0 Diagnostic Mode 1 1 Monitor Mode 21/36 L9634 4.25 Register Mode Register mode message is defined as shown in table below. Table 12. MOSI Register Mode Message Definition Bit State D15 0 D14 0 D13 0 Description Mode Bits Read Configuration Register 1 Write Configuration Register D12 Address-bit ) s ( ct D11 D10 D9 u d o D8 D7 Data-bit r P e D6 D5 t e l o D4 D3 D2 D1 D0 ) (s s b O When bit D13 is set to '1,' OSD writes the data-bit to its internal register. The address bit desig-nates a specific register in OSD. This address-bit is defined as shown below. t c u When the ADC resistance measurement is addressed, OSD ignores the data-bit. Upon the detection of this ADC resistance measurement on the address-bit, OSD sends the 8-bit resistance measurement value in the register mode response. d o r P A write request contains valid mode bits, bit D13 set to '1,' valid address bits and valid data bits. In the next valid CS, a register mode response contains the valid register content and not the echo from previous command. e t e ol A read request contains valid mode bits, bit D13 set to '0,' and valid address bits. The data bits will be ignored by the OSD. In the next valid CS, a register mode response contains a valid register content. This register is determined by the address bits sent in the previous command. s b O Table 13. Address-bit Definition Bit D12 Bit D11 Bit D10 Bit D9 Bit D8 Description RES ADC DIAG AD1 AD0 Program Other Options 0 0 0 0 0 STATUS.FLT Configuration Register 0 0 0 0 1 Deployment Configuration 1 Register 0 0 0 1 0 Deployment Configuration 2 Register 0 0 0 1 1 Soft Reset RES ADC DIAG AD1 AD0 0 0 1 0 0 0 0 1 0 1 Channel 2 and 3 Register, Table 19 0 0 1 1 0 Channel 4 and 5 Register (see table 20) 22/36 Diagnostic Fault Registers Channel 0 and 1 Register (see table 18) L9634 Table 13. Address-bit Definition (continued) Bit D12 Bit D11 Bit D10 Bit D9 Bit D8 Description 0 0 1 1 1 Channel 6 and 7 Register, Table 21 RES ADC AD2 AD1 AD0 ADC Resistance Measurement Result 0 1 0 0 0 8-bit ADC Measurement Register: Ch 0 0 1 0 0 1 8-bit ADC Measurement Register: Ch 1 0 1 0 1 0 8-bit ADC Measurement Register: Ch 2 0 1 0 1 1 8-bit ADC Measurement Register: Ch 3 0 1 1 0 0 8-bit ADC Measurement Register: Ch 4 0 1 1 0 1 8-bit ADC Measurement Register: Ch 5 0 1 1 1 0 8-bit ADC Measurement Register: Ch 6 0 1 1 1 1 8-bit ADC Measurement Register: Ch 7 ) s ( ct u d o 4.26 STATUS.FLT Configuration Register STATUS.FLT register is defined as shown in the below table. The setting of these registers will influence the diagnostic fault indication flag in the status response. If any of these bits set to '1,' OSD inhibits the faults of the respective channels from affecting bit D13 (diagnostic fault flag) in the MISO Status Response. This STATUS.FLT configuration register does not afftect the operation of diagnostic fault registers. r P e Table 14. STATUS.FLT Configuration Register t e l o s b O Bit Status D7 0 Enable Fault Report on Channel 7 (default) 1 Disable Fault Report on Channel 7 D6 D5 Enable Fault Report on Channel 6 (default) Disable Fault Report on Channel 6 0 0 e t e ol 1 D3 bs D2 O D1 D0 t c u 0 1 1 D4 ) (s Description d Enable Fault Report on Channel 5 (default) o r P Disable Fault Report on Channel 5 Enable Fault Report on Channel 4 (default) Disable Fault Report on Channel 4 0 Enable Fault Report on Channel 3 (default) 1 Disable Fault Report on Channel 3 0 Enable Fault Report on Channel 2 (default) 1 Disable Fault Report on Channel 2 0 Enable Fault Report on Channel 1 (default) 1 Disable Fault Report on Channel 1 0 Enable Fault Report on Channel 0 (default) 1 Disable Fault Report on Channel 0 23/36 L9634 4.27 Deployment Configuration Register 1 The deployment configuration register 1 is defined as shown in the next table. During a deployment event, a write request to this register is inhibited. Table 15. Deployment Configuration Register 1 Bit Status D7 Description Pulse Stretch timer (see table) D6 D5 0 ARM Parallel Mode (default) 1 ARM Serial Mode D4 - Don’t Care D3 0 ARM67 Pulse Stretch Disable (default) 1 ARM67 Pulse Stretch Enable D2 0 ARM45 Pulse Stretch Disable (default) 1 ARM45 Pulse Stretch Enable 0 ARM23 Pulse Stretch Disable (default) 1 ARM23 Pulse Stretch Enable 0 ARM01 Pulse Stretch Disable (default) 1 ARM01 Pulse Stretch Enable D1 D0 ) s ( ct u d o r P e t e l o s b O Bit D3 through bit D0 is used to inhibit the ARMx signal from initiating the pulse stretch timer. When these bits are "0," ARMx signal is prohibited from initiating the timer. Otherwise, a valid ARMx signal starts the timer. If the timer has already initiated by the SPI deployment command, the ARMx signal does not affect the timer. ) (s Bit D7 and bit D6 is used to set the period of pulse stretch timer. OSD has 8 independent timers for each channel. Either a valid ARMx or a SPI deployment command is capable to start the pulse stretch timer. These bits set the timer duration according to table. These values are default to %00 after battery connect. Bit D7 e t e l 0 0 so 1 b O 24/36 1 d o r P Table 16. Pulse Stretch Timer t c u Bit D6 Stretch Period (ms) 0 7.5 1 15 0 30 1 60 L9634 4.28 Deployment Configuration Register 2 The second deployment configuration register contains bits to configure the deployment period and the deployment current for each loop. During a deployment event, a write request to this register is inhibited. The register is defined as shown in herebelow table. Table 17. Deployment Configuration Register 2 Bit Status D7 0 Channel 6/7 2ms Deployment Period (default) 1 Channel 6/7 4ms Deployment Period 0 Channel 6/7 1.2A Deployment Current (default) 1 Channel 6/7 1.75A Deployment Current 0 Channel 4/5 2ms Deployment Period (default) 1 Channel 4/5 4ms Deployment Period 0 Channel 4/5 1.2A Deployment Current (default) 1 Channel 4/5 1.75A Deployment Current 0 Channel 2/3 2ms Deployment Period (default) 1 Channel 2/3 4ms Deployment Period 0 Channel 2/3 1.2A Deployment Current (default) 1 Channel 2/3 1.75A Deployment Current 0 Channel 0/1 2ms Deployment Period (default) 1 Channel 0/1 4ms Deployment Period 0 Channel 0/1 1.2A Deployment Current (default) 1 Channel 0/1 1.75A Deployment Current D6 D5 D4 D3 D2 D1 D0 Description ) (s ) s ( ct u d o r P e t e l o s b O t c u 4.29 Soft Reset The soft reset in OSD is achieved by writing $AA and $55 within two subsequent 16-bit SPI transmissions. If the sequence is broken, the processor will be required to re-transmit the sequence. OSD is not in reset if the sequence is not completed within two subsequent 16-bit SPI transmissions. d e t e ol o r P 4.30 Diagnostic Fault Registers These diagnostic fault registers contain the fault status for each of the channels. Each register is cleared immediately after a SPI reading on that particular register. The diagnostic fault registers is defined as shown here below: s b O Table 18. Diagnostic Fault Register: Channel 0 and 1 Bit State D7 0 No Fault: Channel 1 1 Fault Exists: Channel 1 D6 Channel 1 Diagnostic Fault-bit Refer to Diagnostic Fault-bit Definition table 22 D5 D4 D3 D2 Description 0 No Fault: Channel 0 1 Fault Exists: Channel 0 Channel 0 Diagnostic Fault-bit Refer to Diagnostic Fault-bit Definition table 22 25/36 L9634 Table 19. Diagnostic Fault Register: Channel 2 and 3 Bit State D7 0 No Fault: Channel 3 1 Fault Exists: Channel 3 D6 Description Channel 3 Diagnostic Fault-bit Refer to Diagnostic Fault-bit Definition table 22 D5 D4 D3 0 No Fault: Channel 2 1 Fault Exists: Channel 2 D2 Channel 2 Diagnostic Fault-bit Refer to Diagnostic Fault-bit Definition table 22 ) s ( ct u d o Table 20. Diagnostic Fault Register: Channel 4 and 5 Bit State D7 0 No Fault: Channel 5 1 Fault Exists: Channel 5 D6 Description t e l o Channel 5 Diagnostic Fault-bit Refer to Diagnostic Fault-bit Definition table 22 D5 D4 D3 0 No Fault: Channel 4 1 Fault Exists: Channel 4 D2 ) (s r P e s b O Channel 4 Diagnostic Fault-bit Refer to Diagnostic Fault-bit Definition table 22 t c u Table 21. Diagnostic Fault Register: Channel 2 and 3 Bit State D7 0 D6 ete 1 D5 s b O ol D4 D3 D2 0 1 d o r P Description No Fault: Channel 7 Fault Exists: Channel 7 Channel 7 Diagnostic Fault-bit Refer to Diagnostic Fault-bit Definition table 22 No Fault: Channel 6 Fault Exists: Channel 6 Channel 6 Diagnostic Fault-bit Refer to Diagnostic Fault-bit Definition table 22 Diagnostic fault bit indicates short between loops, short to battery, open circuit, short to ground, high or low side MOS fault. The channel number is determined by the address bit in register mode command. These faults are decoded as shown in Diagnostic Fault-bit Definition table. Bit D7 and bit D3 indicate if a fault condition exists in the respective channels. Loss of ground fault has the highest priority among all fault conditions. 26/36 L9634 Table 22. Diagnostic Fault-bit Definition D6/D2 D5/D1 D4/D0 Description 0 0 0 No Fault 0 0 1 Short Between Loops 0 1 0 Short to Battery 0 1 1 Open Fault 1 0 0 Short to Ground 1 0 1 Low Side MOS Fault 1 1 0 High Side MOS Fault 1 1 1 Loss of Ground Fault ) s ( ct 4.31 Resistance Measurement Registers OSD has 8 independent resistance measurement registers. The resistance measurement registers is defined as shown in the table. u d o r P e Table 23. ADC Resistance Measurement Register Bit Description t e l o D7 D6 D5 D4 8-bit ADC Resistance Measurement Result ) (s D3 D2 s b O t c u D1 D0 d ADC resistance measurement registers contain the measurement results of each of the OSD deployment channels. The channel number is determined by the address bit in diagnostic command (see Address bit definition table 13) e t e ol o r P s b O 27/36 L9634 4.32 Command Mode Command Mode message is defined as shown in next table. Table 24. MOSI Command Mode Message Definition Bit State D15 0 D14 1 D13 Description Mode Bits Odd Parity D12 - Don’t Care D11 - Don’t Care D10 - Don’t Care D9 - Don’t Care D8 - Don’t Care D7 0 Channel 7 Idle 1 Deploy Channel 7 0 Channel 6 Idle 1 Deploy Channel 6 0 Channel 5 Idle 1 Deploy Channel 5 0 Channel 4 Idle 1 Deploy Channel 4 D3 0 Channel 3 Idle 1 Deploy Channel 3 D2 0 Channel 2 Idle 1 Deploy Channel 2 D1 0 Channel 1 Idle D0 0 D6 D5 D4 1 1 e t e ol ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P Deploy Channel 1 Channel 0 Idle Deploy Channel 0 Odd parity check includes all 16 bits. "Don't care" bit is included in the parity check as well. Bit D7 to bit D0 is used to start the deployment or the pulse stretch timer. OSD provides an independent timer for each channel. When any of these bits are set to '1,' OSD starts the deployment of the pulse stretch timer for the respective channels. If any of these bits are set to '0' when the pulse stretch timer is still active, OSD terminates the pulse stretch timer for the respective channels. Once deployment is initiated it will not be terminated. During the deployment, OSD will ignore all commands. s b O When DEPEN is negated, OSD ignores the deploy command. In other words, OSD will not initiate the pulse stretch timer or a deployment in this condition. However, when the pulse stretcher is already started by a deploy command, DEPEN will not terminate the pulse stretch timer. Upon receiving an idle command, OSD will terminates the pulse stretch timer regardless of DEPEN signal. In this case, only a pulse stretch timer that is started by a deploy command that can be terminated by sending an idle command. 28/36 L9634 4.33 Diagnostic Mode Diagnostic Mode message is defined as shown in table. Table 25. MOSI Diagnostic Mode Message Definition Bit State D15 1 D14 0 D13 Description Mode Bits D12 Odd Parity 0 Read Status Response Only 1 Run On-chip Diagnostic D11 - Don’t Care D10 - Don’t Care D9 0 Short Between Loops Test Disable 1 Short Between Loops Test Enable D8 0 MOS Test Disable 1 MOS Test Enable D7 0 Disable Channel 7 Diagnostic 1 Enable Channel 7 Diagnostic D6 0 Disable Channel 6 Diagnostic 1 Enable Channel 6 Diagnostic D5 0 Disable Channel 5 Diagnostic 1 Enable Channel 5 Diagnostic 0 Disable Channel 4 Diagnostic 1 Enable Channel 4 Diagnostic 0 Disable Channel 3 Diagnostic 1 Enable Channel 3 Diagnostic D4 D3 D2 0 1 D1 0 e t e l 1 D0 o s b ) (s ) s ( ct u d o r P e t e l o s b O t c u d o r P Disable Channel 2 Diagnostic Enable Channel 2 Diagnostic Disable Channel 1 Diagnostic Enable Channel 1 Diagnostic 0 Disable Channel 0 Diagnostic 1 Enable Channel 0 Diagnostic Odd parity check includes all 16 bits. "Don't care" bit is included in the parity check as well. O When bit D12 is set to '1,' OSD starts its internal diagnostics on any channels selected in bit D7 through bit D0. When any of bit D7 through bit D0 are set to '1,' OSD performs diagnostics on the respective channels. The diagnostic sequence is shown in Figure 10. When bit D12 is set to '0,' OSD ignores bit D9 through bit D0. Bit D9 and bit D8 are utilized to control the short between loops and MOS tests. If any of these bits are set to '1,' OSD performs the respective tests to any channels as selected in bit D7 thorugh bit D0. OSD executes these tests based on the diagnostic flow chart, shown in Figure 15. 29/36 L9634 4.34 Monitor Mode Monitor Mode message is defined as shown in below: Table 26. MOSI Monitor Mode Message Definition Bit State D15 1 D14 1 D13 Description Mode Bits D12 Odd Parity 0 Read Status Response Only 1 Write Commands D11 - Don’t Care D10 - Don’t Care D9 0 Do not modify Short Between Loops Test 1 Modify Short Between Loops Test D8 0 Disable Short Between Loops Test 1 Enable Short Between Loops Test D7 0 Keep Deploy Success Flag Channel 7 1 Clear Deploy Success Flag Channel 7 D6 0 Keep Deploy Success Flag Channel 6 1 Clear Deploy Success Flag Channel 6 D5 0 Keep Deploy Success Flag Channel 5 1 Clear Deploy Success Flag Channel 5 0 Keep Deploy Success Flag Channel 4 1 Clear Deploy Success Flag Channel 4 0 Keep Deploy Success Flag Channel 3 1 Clear Deploy Success Flag Channel 3 D4 D3 D2 0 1 D1 0 e t e l 1 D0 o s b ) (s ) s ( ct u d o r P e t e l o s b O t c u d o r P Keep Deploy Success Flag Channel 2 Clear Deploy Success Flag Channel 2 Keep Deploy Success Flag Channel 1 Clear Deploy Success Flag Channel 1 0 Keep Deploy Success Flag Channel 0 1 Clear Deploy Success Flag Channel 0 Odd parity check includes all 16 bits. "Don't care" bit is included in the parity check as well. O When bit D12 is set to a '0,' OSD ignores all command bits, specified in bit D9 to bit D0. The monitor mode message is allowed to start or to stop the short between loops test. To start the test, both bit D9 and bit D8 has to be set to '1.' To stop the test, bit D9 is set to '1' and bit D8 is set to '0.' If bit D9 is set to '0,' OSD ignores the state of bit D8. In this condition, OSD does not affect the test. If bit D12 is set to '0,' OSD ignores bit D9 and bit D8. Bit D7 through bit D0 is used to clear/keep the deploy success flag. When these bits are set to '1,' the flag is cleared. Otherwise, OSD does not affect the state of these flags. 30/36 L9634 4.35 MISO Bit Definition Figure 23. MISO Bit Layout D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 MSB D1 D0 LSB Table 27. MISO Mode Bits Definition Bit D15 Bit D14 Description 0 0 Register Mode Response 0 1 Command Mode Response 1 0 SPI Fault Response 1 1 Status Response u d o r P e 4.36 Register Mode Response Register Mode Response is defined as shown in table. Table 28. MISO Register Mode Response Definition Bit State D15 0 D14 0 s b O Mode Bits ) (s Echo of MOSI Read/Write Bit D12 Address Bits Refer to Address-bit Definition table t c u d D10 D9 D8 e t e l D7 D6 t e l o Description D13 D11 ) s ( ct o r P Data Bits o s b D5 D4 O D3 D2 D1 D0 Bit D13 is used to reflect the status of MOSI Read/Write bit (refer to bit D13 in "MOSI Register Mode Message Definition table"). Bit D7 through bit D0 contain data bits. These data bits contain either diagnostic fault register or ADC resistance measurement register depending upon the MOSI request. Both register are defined as shown in "Diagnostic Fault Register Channel 0 and 1 table" and "ADC Resistance Measurement Register table". 31/36 L9634 4.37 Command Mode Response Command Mode Response defined as shown below. Table 29. MISO Command Mode Response Definition Bit State D15 0 D14 1 D13 - Don’t Care D12 0 DEPEN Negated 1 DEPEN Asserted 0 ARM67 Negated 1 ARM67 Asserted 0 ARM45 Negated 1 ARM45 Asserted 0 ARM23 Negated 1 ARM23 Asserted 0 ARM01 Negated 1 ARM01 Asserted D11 D10 D9 D8 Description Mode Bits ) s ( ct u d o r P e D7 Deploy Channel 7 Status D6 Deploy Channel 6 Status D5 Deploy Channel 5 Status D4 Deploy Channel 4 Status D3 Deploy Channel 3 Status D2 Deploy Channel 2 Status D1 Deploy Channel 1 Status D0 Deploy Channel 0 Status ) (s t e l o s b O t c u d o r P DEPEN status flag indicates the state of DEPEN pin. ARMx status flag indicates the state of the respective ARMx signal, including the pulse stretch timer. If the pulse stretch timer is initiated by a deployment command, it does not assert the ARMx status flag. This flag is de/asserted as soon as the de-glitch timer is expired. e t e ol Deploy status flag indicates the SPI deployment status for the respective channel. These flags reflect bit D7 through bit D0 of the most recent SPI command mode message. These bits do not include the status of pulse stretch timer. These bits will be overwritten by the most recent SPI command mode message. When DEPEN is negated, a valid deploy command is ignored and deploy status flag is not set. s b O 4.38 SPI Fault Response This SPI fault response indicates a fault in the last MOSI transmission. OSD uses the parity bit to determine the integrity of the MOSI command transmission.This response is defined as shown in table. Table 30. MISO SPI Fault Response Bit State D15 1 D14 0 D13 – D0 32/36 Description Mode Bits Don’t Care L9634 4.39 Status Response Status Response is the default response to the processor, and is defined as shown in table Table 31. MISO Status Response Definition Bit State D15 1 Description Mode Bits D14 1 D13 0 No Diagnostic Fault 1 Diagnostic Fault Exists 0 Diagnostic not Complete D12 1 Diagnostic Complete / Not Started 0 ARM67 Negated 1 ARM67 Asserted 0 ARM45 Negated 1 ARM45 Asserted 0 ARM23 Negated 1 ARM23 Asserted 0 ARM01 Negated 1 ARM01 Asserted D7 0 No Deployment Event: Channel 7 1 Deploy Command Successful: Channel 7 D6 0 No Deployment Event: Channel 6 1 Deploy Command Successful: Channel 6 D5 0 No Deployment Event: Channel 5 1 Deploy Command Successful: Channel 5 0 No Deployment Event: Channel 4 1 Deploy Command Successful: Channel 4 0 No Deployment Event: Channel 3 D11 D10 D9 D8 D4 D3 1 D2 0 D1 ete 1 D0 b O l o s 0 ) s ( ct u d o ) (s r P e t e l o s b O t c u d o r P Deploy Command Successful: Channel 3 No Deployment Event: Channel 2 Deploy Command Successful: Channel 2 No Deployment Event: Channel 1 1 Deploy Command Successful: Channel 1 0 No Deployment Event: Channel 0 1 Deploy Command Successful: Channel 0 Diagnostic fault indication flag indicates if a fault exists during the on-chip diagnostic. This bit reports the fault status on channel/s enabled in the STATUS.FLT configuration register. Diagnostic completion status flag indicates if the on-chip diagnostic is completed. This flag will be set when all the requested channels finish the diagnostic sequence (see Figure 15). This flag does not include the status of "short between loops" test. ARMx status flag indicates the state of the respective ARMx signal, including the pulse stretch timer. If the pulse stretch timer is initiated by a deployment command, it does not assert the ARMx status flag. This flag is de/asserted as soon as the de-glitch timer is expired. Deploy command success bit indicates if the corresponding channel has finished its deployment sequence. This bit is set when deployment period, 2ms or 4ms, has expired. Once this bit is set, it inhibits the subsequent deployment command until OSD receives a SPI command to clear this deployment success flag. Refer to Figure 9, Figure 10, Figure 11, and Figure 12 for the operation of deployment success flag. 33/36 L9634 Figure 24. TQFP44 (10x10x1.4mm) Mechanical Data & Package Dimensions mm inch DIM. MIN. TYP. MAX. A MIN. TYP. 1.60 A1 0.05 A2 1.35 B 0.30 C 0.09 D 11.80 D1 9.80 D3 0.063 0.15 0.002 1.40 1.45 0.053 0.055 0.057 0.37 0.45 0.012 0.015 0.018 0.20 0.004 12.00 12.20 0.464 0.472 0.480 10.00 10.20 0.386 0.394 0.401 8.00 0.006 0.008 11.80 12.00 12.20 0.464 0.472 0.480 E1 9.80 10.00 10.20 0.386 0.394 0.401 E3 8.00 0.315 e 0.80 0.031 0.45 0.60 L1 0.75 0.018 1.00 k ) s ( ct u d o 0.315 E L OUTLINE AND MECHANICAL DATA MAX. 0.024 t e l o 0.030 0.039 ) (s 0˚(min.), 3.5˚(typ.), 7˚(max.) D r P e s b O TQFP44 (10 x 10 x 1.4mm) t c u d ro D1 let 33 34 so A1 23 22 0.10mm .004 B E E1 Seating Plane B b O P e A A2 12 44 11 1 C L e K TQFP4410 0076922 D 34/36 L9634 Table 32. Revision History Date Revision October 2004 1 Description of Changes First Issue ) s ( ct u d o r P e t e l o ) (s s b O t c u d e t e ol o r P s b O 35/36 L9634 ) s ( ct u d o r P e t e l o ) (s s b O t c u d e t e ol o r P s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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