E-L9823

L9823 Octal low-side driver for bulb, resistive and inductive loads with serial input control, output protection and diagnostic Datasheet - production data  Output status data available on the SPI using 8-bit I/O protocol up to 3.0 MHz  Low standby current with reset = low (typ. 35 µA @ VDD)  Open load detection (outputs off)  Single VDD logic supply  High EMS immunity and low EME (controlled output slopes) '!0'03 SO24  Full functionality of the remaining device at negative voltage drop on outputs (-1.5 V or -3.0 A) Features  Output mode programmable for sustained current limit or shutdown  Outputs current capability up to 0.5 A  Cascadable SPI control for outputs Description  Reset function with reset signal or undervoltage at VDD L9823 is a octal low-side driver circuit, dedicated for automotive applications.  Programmable intrinsic output voltage clamping at typ. 50 V for inductive switching  Overcurrent shutdown with latch-off for every write cycle (SFPD = low)  Independent thermal shutdown of outputs (SOA Protection) Output voltage clamping is provided for flyback current recirculation, when inductive loads are driven. Chip select and cascadable serial 8-bit Interface for outputs control and diagnostic data transfer. Table 1. Device summary Order code Package Packing L9823 SO24 Tube E-L9823 SO24 Tube September 2013 This is information on a product in full production. DocID7791 Rev 7 1/19 www.st.com Contents L9823 Contents 1 2 3 Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Power outputs characteristics for flyback current, outputs short circuit protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Output stages control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 DocID7791 Rev 7 L9823 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Outputs Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Diagnostic for outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DocID7791 Rev 7 3/19 3 List of figures L9823 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. 4/19 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Output control register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Timing of the serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pulse diagram to read the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Structure of the outputs status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Typical application circuit diagram for the L9823 circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SO24 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DocID7791 Rev 7 L9823 Block diagram and pins description 1 Block diagram and pins description 1.1 Block diagram Figure 1. Block diagram $$  3&0$  /54 /,  6$'  )/, 3#,+  3)  /UTPUT,ATCH  3HIFT2EGISTER #3" 30) )NTERFACE  3/ 'ATE #ONTROL 1 1 1 1 1 1 1 1 1  )3#"  /VER 4EMPERATURE $ETECT /4   #( $IA G $IAG 1 $IAG $IAG $IAG 1 $IAG $IA G $IAG $IAG 1 $IAG $IAG $IAG 1 $IAG #( #( #( #(  1 $IAG #( 2ESET 1 $IAG #(  2ESET 2ESET 1 $IAG 5NDERVOL TAGE 2%3%4 #( /54  /54  /54  /54  /54  /54  /54  '.$     1.2 '!0'03 Pins description Figure 2. Pins connection (top view) /54   /54 /54   /54 3#,+   2%3%4 3)   .# '.$   '.$ '.$   '.$ '.$   '.$ '.$   '.$ 3/   6$$ #3"   3&0$ /54   /54 /54   /54 '!0'03 DocID7791 Rev 7 5/19 18 Block diagram and pins description L9823 Table 2. Pins description N# Pin 1 OUT7 Output 7 2 OUT6 Output 6 SCLK The system clock pin (SCLK) clocks the internal shift registers of the L9823. The serial input pin (SI) accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the shift register on the rising edge of the SCLK signal. False clocking of the shift register must be avoided to guarantee validity of data. It is essential that the SCLK pin be in a logic low state whenever chip select bar pin (CSB) makes any transition. For this reason, it is recommended though not necessary, that the SCLK pin be kept in a low logic state as long as the device is not accessed (CSB in logic high state). When CSB is in a logic high state, any signal at the SCLK and SI pin is ignored and SO is tri-stated (high-impedance). 4 SI This pin is for the input of serial instruction data. SI information is read in on the falling edge of SCLK. A logic high state present on this pin when the SCLK signal rises will program a specific output OFF, and in turn, turns OFF the specific output on the rising edge of the CSB signal. Conversely, a logic low state present on the SI pin will program the output ON, and in turn, turns ON the specific output on the rising edge of the CSB signal. To program the eight outputs of the L9823 ON or OFF, an eight bit serial stream of data is required to be entered into the SI pin starting with Output 7, followed by Output 6, Output 5, etc., to Output 0. For each rise of the SCLK signal, with CSB held in a logic low state, a databyte instruction (ON or OFF) is loaded into the shift register per the databyte SI state. The shift register is full after eight bits of information have been entered. To preserve data integrity, care should be taken to not transition SI as SCLK transitions from a low-to-high logic state. 5 GND GND 6 GND GND 7 GND GND 8 GND GND 3 Description SO The serial output (SO) pin is the tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin goes to a logic low state. The SO data reports the drain status, either high or low. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. When an output is OFF and not faulted, the corresponding SO databyte is a high state. When SO an output is ON, and there is no fault, the corresponding databyte on the SO pin will be a low logic state. The SI / SO shifting of data follows a first-in-first-out protocol with both input and output words transferring the Most Significant Bit (MSB) first. The SO pin is not affected by the status of the Reset pin. 10 CSB The system MCU selects the L9823 to be communicated with through the use of the CSB pin. Whenever the pin is in a logic low state, data can be transferred from the MCU to the L9823 and vise versa. Clocked-in data from the MCU is transferred from the L9823 shift register and latched into the power outputs on the rising edge of the CSB signal. On the falling edge of the CSB signal, drain status information is transferred from the power outputs and loaded into the device's shift register. The CSB pin also controls the output driver of the serial output pin. Whenever the CSB pin goes to a logic low state, the SO pin output driver is enabled allowing information to be transferred from the L9823 to the MCU. To avoid any spurious data, it is essential that the high-to-low transition of the CSB signal occur only when SCLK is in a logic low state. 11 OUT5 Output 5 12 OUT4 Output 4 13 OUT3 Output 3 9 6/19 DocID7791 Rev 7 L9823 Block diagram and pins description Table 2. Pins description (continued) N# Pin Description 14 OUT2 Output 2 15 SFPD The Short Fault Protect Disable (SFPD) pin is used to disable the overcurrent latch-OFF. This feature allows control of incandescent loads where in-rush currents exceed the device's analog current limits. Essentially the SFPD pin determines whether the L9823 output(s) will instantly shutdown upon sensing an output short or remain ON in a current limiting mode of operation until the output short is removed or thermal shutdown is reached. If the SFPD pin is tied to VDD the L9823 output(s) will remain ON in a current limited mode of operation upon encountering a load short to supply. If the SFPD pin is grounded, a short circuit will immediately shutdown only the output affected. Other outputs not having a fault condition will operate normally. 16 VDD VDD 17 GND GND 18 GND GND 19 GND GND 20 GND GND 21 N.C. Not Connected The Reset pin is active low and used to clear the SPI shift register and in doing so sets all output switches OFF. With the device in a system with an MCU; upon initial system power up, the MCU holds the Reset pin of the device in a logic low state ensuring all outputs to be OFF until the VDD pin voltages are adequate for predictable operation. After the L9823 is Reset, the MCU is ready to assert system control with all output switches initially OFF. The Reset pin is active low and has an internal pull-down incorporated to ensure operational predictability should the external pull-down of the MCU open circuit. The internal pull-up is to afford safe and easy interfacing to the MCU. The Reset pin of the L9823 should be pulled to a logic low state for a duration of at least 160ns to ensure reliable Reset. 22 RESET 23 OUT1 Output 1 24 OUT0 Output 0 DocID7791 Rev 7 7/19 18 Electrical specifications L9823 2 Electrical specifications 2.1 Absolute maximum ratings For voltages and currents applied externally to the device. Exceeding limits may cause damage to the device. Table 3. Absolute maximum ratings Symbol VDD Parameter Supply voltage Value Unit -0.3 to 7 V Inputs and data lines (CSB, SCLK, SI, Reset, SFPD, SO) VIN VSDO IIN Voltage (CSB, SCLK, SI, Reset, SFPD) Voltage (SO) -0.3 to 7 -0.3 to VDD+0.3 Protection diodes current (1) T  1ms -20 to 20 (1) V mA Outputs (OUT0 to OUT7) VOUT Cont Continuous output voltage -1.5 to 45 V VOUT Cont Continuous output current -3 to IOUT LIM A IOUT PEAK Output current EOUTclamp Output clamp energy IOUT LIM -10 (3) Output current (self limit) (2) to 2 A 50 mJ 2 A 1. All inputs are protected against ESD according to MIL 883C; tested with HBM C = 100 pF, R = 1500  at 2kV. It corresponds to a dissipated energy E  0.2mJ (data available upon request). 2. Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3. 3. Max. output clamp energy at Tj = 150°C, using single non-repetitive pulse of 500 mA 2.2 Thermal data Table 4. Thermal data Symbol Parameter Value Unit 155 (Min.), 180 (Typ.) °C Thermal shutdown TLIM Thermal shutdown threshold Thermal resistance (junction-to-lead) RthjL-one Single output (junction lead) 25 (Max.) °C/W RthjL-all All outputs (junction lead) 20 (Max.) °C/W Storage temperature -55 to 150 °C Tstg 8/19 DocID7791 Rev 7 L9823 2.3 Electrical specifications Electrical characteristics 4.5 V  VDD  5.5 V; -40 °C  TJ  150 °C; unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Supply voltage Standby current leakage current Reset = LOW and / or VDDRES>VDD > 0.5V VDD < 0.5V - 35