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ST72260Gx, ST72262Gx, ST72264Gx 8-BIT MCU WITH FLASH OR ROM MEMORY, ADC, TWO 16-BIT TIMERS, I2C, SPI, SCI INTERFACES ■ ■ ■ ■ ■ Memories – 4 K or 8 Kbytes Program memory: ROM or Single voltage extended Flash (XFlash) with read-out protection write protection and InCircuit Programming and In-Application Programming (ICP and IAP). 10K write/erase cycles guaranteed, data retention: 20 years at 55°C. – 256 bytes RAM Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supply supervisor (LVD) with 3 programmable levels and auxiliary voltage detector (AVD) with interrupt capability for implementing safe power-down procedures – Clock sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock – PLL for 2x frequency multiplication – Clock-out capability – 4 Power Saving Modes: Halt, Active Halt,Wait and Slow Interrupt Management – Nested interrupt controller – 10 interrupt vectors plus TRAP and RESET – 22 external interrupt lines (on 2 vectors) 22 I/O Ports – 22 multifunctional bidirectional I/O lines – 20 alternate function lines – 8 high sink outputs 4 Timers – Main Clock Controller with Real time base and Clock-out capabilities – Configurable watchdog timer ) s t( SDIP32 e t le LFBGA 6x6mm o s b r P e ■ ■ t e l o s b O o r P SO28 – Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and Pulse generator modes 3 Communication Interfaces – SPI synchronous serial interface – I2C multimaster interface (SMBus V1.1 Compliant) – SCI asynchronous serial interface 1 Analog peripheral – 10-bit ADC with 6 input channels Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode detection – 17 main addressing modes – 8 x 8 unsigned multiply instruction Development Tools – Full hardware/software development package O ) ■ s ( t c u d o c u d ■ Device Summary Features Program memory - bytes RAM (stack) - bytes Peripherals Operating Supply CPU Frequency Operating Temperature Packages ST72260G1 4K Watchdog timer, RTC, Two16-bit timers, SPI ST72262G1 ST72262G2 ST72264G1 4K ST72264G2 8K 4K 8K 256 (128) Watchdog timer, RTC, Watchdog timer, RTC, Two 16-bit timers, SPI, ADC Two 16-bit timers, SPI, SCI, I2C, ADC 2.7 V to 5.5 V Up to 8 MHz (with oscillator up to 16 MHz) PLL 4/8 MHz 0° C to +70° C / -40° C to +85° C -40° C to +85° C -40° C to +85° C SO28 / SDIP32 SO28 / SDIP32 LFBGA Rev. 3 June 2005 1/172 1 Table of Contents 1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 ICC INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 MEMORY PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 RELATED DOCUMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 c u d ) s t( 5 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 o r P 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 e t le 6 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1 PHASE LOCKED LOOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 o s b 6.2 MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 SYSTEM INTEGRITY MANAGEMENT (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 O ) 7 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 s ( t c 7.2 MASKING AND PROCESSING FLOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.3 INTERRUPTS AND LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 CONCURRENT & NESTED MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 INTERRUPT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 u d o r P e t e l o 8 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.5 HALT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 s b O 9 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.4 UNUSED I/O PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.5 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.6 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.7 DEVICE-SPECIFIC I/O PORT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 172 I/O PORT REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.8 10 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2/172 2 Table of Contents 10.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.3 MISCELLANEOUS REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 11.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK (MCC/RTC) . . . . . . . . . . . . . 53 11.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ) s t( 11.6 I2C BUS INTERFACE (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 c u d 11.7 10-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 12 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 12.1 CPU ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 o r P 12.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 13 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 e t le o s b 13.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 13.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 13.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 O ) 13.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 13.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 s ( t c 13.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 u d o 13.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 13.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 r P e 13.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 13.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 153 t e l o 13.12 10-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 14 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 14.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 s b O 14.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 14.3 LEAD-FREE PACKAGE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 15 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 162 15.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE . . . . 164 15.3 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16 KNOWN LIMITATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.1 ALL FLASH AND ROM DEVICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 16.2 FLASH DEVICES ONLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 17 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 3/172 3 ST72260Gx, ST72262Gx, ST72264Gx ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet Please note that the list of known limitations can be found at the end of this document on page 168. 4/172 ST72260Gx, ST72262Gx, ST72264Gx 1 INTRODUCTION The ST72260Gx, ST72262Gx and ST72264Gx devices are members of the ST7 microcontroller family. They can be grouped as follows : – ST72264Gx devices are designed for mid-range applications with ADC, I2C and SCI interface capabilities. – ST72262Gx devices target the same range of applications but without I2C interface or SCI. – ST72260Gx devices are for applications that do not need ADC, I2C peripherals or SCI. All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set. The ST72F260G, ST72F262G, and ST72F264G versions feature single-voltage FLASH memory with byte-by-byte In-Circuit Programming (ICP) capabilities. Under software control, all devices can be placed in WAIT, SLOW, Active-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. For easy reference, all parametric data is located in Section 13 on page 126. Related Documentation AN1365: Guidelines for migrating ST72C254 applications to ST72F264 ) s t( c u d e t le Figure 1. General Block Diagram o s b Internal CLOCK OSC1 O ) MULTI OSC OSC2 s ( t c MCC/RTC LVD POWER SUPPLY VSS r P e RESET CONTROL let O o s b 8-BIT CORE ALU PROGRAM MEMORY (4 or 8K Bytes) RAM (256 Bytes) ADDRESS AND DATA BUS u d o VDD o r P I2C* SCI* PORT A PA7:0 (8 bits) ICD SPI PORT B PB7:0 (8 bits) 16-BIT TIMER A PORT C PC5:0 (6 bits) 10-BIT ADC* 16-BIT TIMER B WATCHDOG *Not available on some devices, see device summary on page 1. 5/172 ST72260Gx, ST72262Gx, ST72264Gx 2 PIN DESCRIPTION Figure 2. 28-Pin SO Package Pinout RESET 1 28 VDD OSC1 OSC2 2 27 3 26 VSS ICCSEL SS/PB7 4 25 PA0 (HS)/ICCCLK SCK/PB6 5 24 PA1 (HS)/ICCDATA MISO/PB5 6 23 PA2 (HS) MOSI/PB4 7 22 PA3 (HS) OCMP2_A/PB3 8 ICAP2_A/PB2 9 ei1 ei0 21 PA4 (HS)/SCLI 20 PA5(HS)/RDI3 OCMP1_A/PB1 ICAP1_A/PB0 10 19 11 18 AIN5/EXTCLK_A/PC5 AIN42/OCMP2_B/PC4 12 17 AIN32/ICAP2_B/PC3 14 13 ei0 or ei11 (HS)/SDAI3 PA6 PA7 (HS)/TDO3 16 15 PC2/MCO/AIN22 Configurable by option byte 2 Alternate function not available on ST72260 3 Alternate function not available on ST72260 and ST72262 du RESET ro o s b O (HS) 20mA high sink capability eiX associated external interrupt vector 32 VDD OSC1 OSC2 2 31 VSS 3 30 SS/PB7 4 29 SCK/PB6 5 ICCSEL PA0 (HS)/ICCCLK PA1 (HS)/ICCDATA MISO/PB5 MOSI/PB4 NC 6 27 7 26 8 25 NC OCMP2_A/PB3 ICAP2_A/PB2 9 24 10 23 NC NC PA4 (HS)/SCLI3 22 PA5 (HS)/RDI3 21 18 PA6 (HSI/SDAI3 PA7 (HS)/TDO3 PC0/ICAP1_B/AIN02 PC1/OCMP1_B/AIN12 17 PC2/MCO/AIN22 P e let 1 e t le o s b O ) s ( t c 11 OCMP1_A/PB1 12 ICAP1_A/PB0 13 AIN52/EXTCLK_A/PC5 AIN42/OCMP2_B/PC4 14 AIN32/ICAP2_B/PC3 16 15 ei1 ei1 ei0 ei0 28 20 19 ei0 or ei11 c u d o r P PC0/ICAP1_B/AIN02 PC1/OCMP1_B/AIN12 1 Figure 3. 32-Pin SDIP Package Pinout ) s t( 3 PA2 (HS) PA3 (HS) 1 Configurable by option byte Alternate function not available on ST72260 3 Alternate function not available on ST72260 and ST72262 2 6/172 (HS) 20mA high sink capability eiX associated external interrupt vector ST72260Gx, ST72262Gx, ST72264Gx PIN DESCRIPTION (Cont’d) Figure 4. TFBGA Package Pinout (view through package) 1 2 3 4 5 6 A ) s t( B c u d C D e t le E o r P o s b F O ) s ( t c u d o r P e t e l o s b O 7/172 ST72260Gx, ST72262Gx, ST72264Gx PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to Section 13 "ELECTRICAL CHARACTERISTICS" on page 126. Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: CT= CMOS 0.3 VDD/0.7 VDD with input trigger Output level: HS = 20 mA high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog – Output: OD = open drain 2), PP = push-pull Refer to Section 9 "I/O PORTS" on page 38 for more details on the software configuration of the I/O ports. The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. ) s t( c u d Table 1. Device Pin Description B3 OSC2 3) 4 4 A2 PB7/SS 5 5 A1 PB6/SCK 6 6 7 7 8 9 u d o O Pr BGA so Alternate Function PP 3 OD 3 ) s ( ct I ana C4 OSC1 3) X Main Output Function (after reset) b O - int 2 Input wpu 2 I/O CT e t le Port / Control float A3 RESET Output 1 Pin Name Input 1 Type SO28 Level SDIP32 Pin n° o r P X Top priority non maskable interrupt (active low) External clock input or Resonator oscillator inverter input or resistor input for RC oscillator Resonator oscillator inverter output or capacitor input for RC oscillator I/O CT X ei1 X X Port B7 SPI Slave Select (active low) I/O CT X ei1 X X Port B6 SPI Serial Clock B1 PB5/MISO I/O CT X ei1 X X Port B5 SPI Master In/ Slave Out Data B2 PB4/MOSI I/O CT X ei1 X X Port B4 SPI Master Out / Slave In Data e t e ol s b O C1 NC C2 NC Not Connected D1 NC 10 8 C3 PB3/OCMP2_A I/O CT X ei1 X X Port B3 Timer A Output Compare 2 11 9 D2 PB2/ICAP2_A I/O CT X ei1 X X Port B2 Timer A Input Capture 2 Timer A Output Compare 1 12 10 E1 PB1 /OCMP1_A I/O CT X ei1 X Caution: Negative current X Port B1 injection not allowed on this pin4). Timer A Input Capture 1 13 11 F1 PB0 /ICAP1_A I/O CT X ei1 X 14 12 F2 PC5/EXTCLK_A/AIN5 I/O CT X ei0/ei1 X X 8/172 Caution: Negative current X Port B0 injection not allowed on this pin4). X Port C5 Timer A Input Clock or ADC Analog Input 5 ST72260Gx, ST72262Gx, ST72264Gx Pin n° Port / Control PP X ei0/ei1 X X X Port C4 16 14 F3 PC3/ ICAP2_B/AIN3 I/O CT X ei0/ei1 X X X Port C3 17 15 E3 PC2/MCO/AIN2 I/O CT X ei0/ei1 X X X Port C2 18 16 F4 PC1/OCMP1_B/AIN1 I/O CT X ei0/ei1 X X X Port C1 19 17 D3 PC0/ICAP1_B/AIN0 I/O CT X ei0/ei1 X X X Port C0 20 18 E4 PA7/TDO I/O CT HS X X X Port A7 SCI output 21 19 F5 PA6/SDAI I/O CT HS X Port A6 I2C DATA 22 20 F6 PA5 /RDI I/O CT HS X 23 21 E6 PA4/SCLI I/O CT HS X E5 NC 25 D6 NC Input BGA 24 ei0 ei0 ei0 ei0 ana CT int I/O wpu 13 E2 PC4/OCMP2_B/AIN4 float 15 Pin Name Output OD Main Output Function (after reset) SO28 Input SDIP32 Type Level T X X T Timer B Output Compare 2 or ADC Analog Input 4 Timer B Input Capture 2 or ADC Analog Input 3 Main clock output (fCPU) or ADC Analog Input 2 Timer B Output Compare 1 or ADC Analog Input 1 Timer B Input Capture 1 or ADC Analog Input 0 ) s t( e t le o r P Port A5 SCI input Port A4 I2C CLOCK o s b O ) 26 22 C6 PA3 I/O CT HS X ei0 X X Port A3 27 23 D4 PA2 I/O CT HS X ei0 X X Port A2 s ( t c u d o I/O CT HS X ei0 X X Port A1 In Circuit Communication Data I/O CT HS X ei0 X X Port A0 In Circuit Communication Clock C5 NC Pr Not Connected 28 24 A6 PA1/ICCDATA 29 25 A5 PA0/ICCCLK 30 26 B5 ICCSEL 31 27 A4 VSS S Ground 32 28 B4 VDD S Main power supply e t e ol O bs c u d Not Connected D5 NC B6 NC Alternate Function I CT X ICC mode pin, must be tied low Notes: 1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is a pull-up interrupt input, otherwise the configuration is a floating interrupt input. Port C is mapped to ei0 or ei1 by option byte. 2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 9 "I/O PORTS" on page 38 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, or an external source to the on-chip oscillator see Section 2 "PIN DESCRIPTION" on page 6 and Section 6.2 "MULTI-OSCILLATOR (MO)" on page 21 for more details. 4: For details refer to Section 13.8 on page 144 9/172 ST72260Gx, ST72262Gx, ST72264Gx 3 REGISTER & MEMORY MAP As shown in Figure 5, the MCU is capable of addressing 64K bytes of memories and I/O registers. The available memory locations consist of 128 bytes of register location, 256 bytes of RAM and up to 8 Kbytes of user program memory. The RAM space includes up to 128 bytes for the stack from 0100h to 017Fh. The highest address bytes contain the user reset and interrupt vectors. The Flash memory contains two sectors (see Figure 5) mapped in the upper part of the ST7 ad- dressing space so the reset and interrupt vectors are located in Sector 0 (F000h-FFFFh). The size of Flash Sector 0 and other device options are configurable by Option byte (refer to Section 15.1 on page 162). IMPORTANT: Memory locations marked as “Reserved” must never be accessed. Accessing a reseved area can have unpredictable effects on the device. Related Documentation AN 985: Executing Code in ST7 RAM ) s t( c u d Figure 5. Memory Map 0000h HW Registers (see Table 2) 0080h RAM (256 Bytes) 00FFh 0100h 007Fh 0080h O ) s ( t c Reserved u d o let r P e FFDFh FFE0h o s b FFFFh O 10/172 Program Memory (4K, 8 KBytes) Interrupt & Reset Vectors (see Table 5 on page 32) Short Addressing RAM Zero page (128 Bytes) o s b 017Fh 0180h DFFFh E000h e t le o r P 017Fh E000h EFFFh F000h FFFFh Stack or 16-bit Addressing RAM (128 Bytes) 8K FLASH PROGRAM MEMORY 4 Kbytes SECTOR 1 4 Kbytes SECTOR 0 ST72260Gx, ST72262Gx, ST72264Gx Table 2. Hardware Register Map Address Register Label Block 0000h 0001h 0002h Port C Reset Status PCDR PCDDR PCOR Register Name xx000000h1) R/W 2) 00h R/W 2) R/W 2) 00h Port C Data Register Port C Data Direction Register Port C Option Register 0003h Remarks Reserved (1 Byte) 0004h 0005h 0006h Port B PBDR PBDDR PBOR 00h 1) 00h 00h Port B Data Register Port B Data Direction Register Port B Option Register 0007h R/W R/W R/W. c u d Reserved (1 Byte) 0008h 0009h 000Ah Port A PADR PADDR PAOR 00h 1) 00h 00h Port A Data Register Port A Data Direction Register Port A Option Register 000Bh to 001Bh e t le Reserved (17 Bytes) o s b o r P R/W R/W R/W 001Ch ISPR0 Interrupt software priority register0 FFh R/W 001Dh ISPR1 Interrupt software priority register1 FFh R/W ITC O ) ) s t( ISPR2 Interrupt software priority register2 FFh R/W 001Fh ISPR3 Interrupt software priority register3 FFh R/W 0020h MISCR1 Miscellanous register 1 00h R/W SPI Data I/O Register SPI Control Register SPI Status Register xxh 0xh 00h R/W R/W R/W 7Fh R/W 000x 000x R/W 00h R/W 00h 00h 00h 00h 00h 40h 00h R/W Read Only Read Only R/W R/W R/W R/W 001Eh s ( t c du 0021h 0022h 0023h SPI SPIDR SPICR SPICSR 0024h WATCHDOG WDGCR Watchdog Control Register SICSR System Integrity Control / Status Register MCCSR Main Clock Control / Status Register I2CCR I2CSR1 I2CSR2 I2CCCR I2COAR1 I2COAR2 I2CDR I2C e t e l 0025h so 0026h Ob 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h MCC I2C o r P Reserved (1 Byte) Control Register I2C Status Register 1 I2C Status Register 2 I2C Clock Control Register I2C Own Address Register 1 I2C Own Address Register2 I2C Data Register Reserved (2 Bytes) 11/172 ST72260Gx, ST72262Gx, ST72264Gx Address Register Label Block Reset Status Register Name Remarks TACR2 TACR1 TASCSR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A Control Register 2 Timer A Control Register 1 Timer A Control/Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h c u d 0040h MISCR2 Miscellanous register 2 00h R/W 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh TBCR2 TBCR1 TBSCSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer B Control Register 2 Timer B Control Register 1 Timer B Control/Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register1 SCI Control Register2 SCI Extended Receive Prescaler Register SCI Extended Transmit Prescaler Register C0h xxh 00h x000 0000h 00h 00h 00h Read Only R/W R/W R/W R/W R/W R/W Data Register Low3) Data Register High3) Control/Status Register 00h 00h 00h Read Only Read Only R/W Flash Control Register 00h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h TIMER A TIMER B let r P e o s b SCI 0057h to 006Eh O ) s ( t c ) s t( Reserved (24 Bytes) 006Fh 0070h 0071h ADC 0072h FLASH 12/172 o s b u d o O 0073h to 007Fh e t le o r P R/W R/W R/W Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W ADCDRL ADCDRH ADCCSR FCSR Reserved (13 Bytes) R/W ST72260Gx, ST72262Gx, ST72264Gx Legend: x=Undefined, R/W=Read/Write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 3. For compatibility with the ST72C254, the ADCDRL and ADCDRH data registers are located with the LSB on the lower address (6Fh) and the MSB on the higher address (70h). As this scheme is not little Endian, the ADC data registers cannot be treated by C programs as an integer, but have to be treated as two char registers. ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O 13/172 ST72260Gx, ST72262Gx, ST72264Gx 4 FLASH PROGRAM MEMORY 4.1 Introduction The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Programming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors. ) s t( c u d 4.2 Main Features ■ ■ ■ ■ ■ ICP (In-Circuit Programming) IAP (In-Application Programming) ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM Sector 0 size configurable by option byte Read-out and write protection against piracy 4.3 PROGRAMMING MODES u d o r P e t e l o s b O 14/172 e t le o s b O ) s ( t c The ST7 can be programmed in three different ways: – Insertion in a programming tool. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased. – In-Circuit Programming. In this mode, FLASH sectors 0 and 1 and option byte row can be programmed or erased without removing the device from the application board. – In-Application Programming. In this mode, sector 1 can be programmed or erased without removing the device from the application board and while the application is running. 4.3.1 In-Circuit Programming (ICP) ICP uses a protocol called ICC (In-Circuit Communication) which allows an ST7 plugged on a printed circuit board (PCB) to communicate with an external programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communications). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. – Download ICP Driver code in RAM from the ICCDATA pin – Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (user-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory areas except Sector 0, which is write/erase protected to allow recovery in case errors occur during the programming operation. o r P ST72260Gx, ST72262Gx, ST72264Gx FLASH PROGRAM MEMORY (Cont’d) 4.4 ICC interface ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These pins are: – RESET: device reset – VSS: device power supply ground – ICCCLK: ICC output serial clock pin – ICCDATA: ICC input serial data pin – ICCSEL: ICC selection (not required on devices without ICCSEL pin) – OSC1: main clock input for external source (not required on devices without OSC1/OSC2 pins) – VDD: application board power supply (optional, see Note 3) Notes: 1. If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the application. If they are used as inputs by the application, isolation such as a serial resistor has to be implemented in case another device forces the signal. Refer to the Programming ete ol s b O ) s t( c u d e t le o r P o s b O ) s ( t c Figure 6. Typical ICC Interface Tool documentation for recommended resistor values. 2. During the ICP session, the programming tool must control the RESET pin. This can lead to conflicts between the programming tool and the application reset circuit if it drives more than 5mA at high level (push pull output or pull-up resistor1K or a reset management IC with open drain output and pull-up resistor>1K, no additional components are needed. In all cases the user must ensure that no external reset is generated by the application during the ICC session. 3. The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This pin must be connected when using most ST Programming Tools (it is used to monitor the application power supply). Please refer to the Programming Tool manual. 4. Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the application or if the selected clock option is not programmed in the option byte. ST7 devices with multi-oscillator capability need to have OSC2 grounded in this case. u d o PROGRAMMING TOOL Pr ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE (See Note 3) OPTIONAL (See Note 4) 9 7 5 3 1 10 8 6 4 2 APPLICATION BOARD APPLICATION RESET SOURCE See Note 2 10kΩ CL1 ICCDATA ICCCLK ST7 RESET See Note 1 APPLICATION I/O ICCSEL OSC1 OSC2 VDD CL2 VSS APPLICATION POWER SUPPLY 15/172 ST72260Gx, ST72262Gx, ST72264Gx FLASH PROGRAM MEMORY (Cont’d) 4.5 Memory Protection 4.6 Related Documentation There are two different types of memory protection: Read Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read out Protection Read-out protection, when selected, provides a protection against Program Memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller. In flash devices, this protection is removed by reprogramming the option. In this case the program memory is automatically erased and the device can be reprogrammed. Read-out protection selection depends on the device type: – In Flash devices it is enabled and removed through the FMP_R bit in the option byte. – In ROM devices it is enabled by mask option specified in the Option List. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes it impossible to both overwrite and erase program memory. Its purpose is to provide advanced security to applications and prevent any change being made to the memory content. Warning: Once set, Write/erase protection can never be removed. A write-protected flash device is no longer reprogrammable. Write/erase protection is enabled through the FMP_W bit in the option byte. For details on Flash programming and ICC protocol, refer to the ST7 Flash Programming Reference Manual and to the ST7 ICC Protocol Reference Manual. AN1477: Emulated data EEPROM with XFlash memory AN1576: IAP drivers for ST7 HDFlash or XFlash MCUs AN1575: On Board Programming methods for ST7 HDFlash or XFlash MCUs AN1070: Checksum self checking capability (s) t c u d o r P e t e l o s b O 16/172 ) s t( c u d o r P 4.7 Register Description e t le FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 000 0000 (00h) 1st RASS Key: 0101 0110 (56h) 2nd RASS Key: 1010 1110 (AEh) 7 o s b 0 0 -O 0 0 0 0 OPT LAT PGM Note: This register is reserved for programming using ICP, IAP or other programming methods. It controls the XFlash programming and erasing operations. When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically. ST72260Gx, ST72262Gx, ST72264Gx 5 CENTRAL PROCESSING UNIT 5.1 INTRODUCTION 5.3 CPU REGISTERS This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. The 6 CPU registers shown in Figure 7 are not present in the memory mapping and are accessed by specific instructions. Accumulator (A) The Accumulator is an 8-bit general purpose register used to hold operands and the results of the arithmetic and logic calculations and to manipulate data. Index Registers (X and Y) These 8-bit registers are used to create effective addresses or as temporary storage areas for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to indicate that the following instruction refers to the Y register.) The Y register is not affected by the interrupt automatic procedures. Program Counter (PC) The program counter is a 16-bit register containing the address of the next instruction to be executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is the LSB) and PCH (Program Counter High which is the MSB). 5.2 MAIN FEATURES ■ ■ ■ ■ ■ ■ ■ ■ Enable executing 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes (with indirect addressing mode) Two 8-bit index registers 16-bit stack pointer Low power HALT and WAIT modes Priority maskable hardware interrupts Non-maskable software/hardware interrupts ) s t( c u d e t le o r P o s b O ) s ( t c Figure 7. CPU Registers u d o 7 Pr 0 ACCUMULATOR RESET VALUE = XXh ete l o s Ob 15 7 0 X INDEX REGISTER RESET VALUE = XXh 7 0 Y INDEX REGISTER RESET VALUE = XXh PCH 8 7 PCL 0 PROGRAM COUNTER RESET VALUE = RESET VECTOR @ FFFEh-FFFFh 7 0 1 1 I1 H I0 N Z C CONDITION CODE REGISTER RESET VALUE = 1 1 1 X 1 X X X 15 8 7 0 STACK POINTER RESET VALUE = STACK HIGHER ADDRESS X = Undefined Value 17/172 ST72260Gx, ST72262Gx, ST72264Gx CENTRAL PROCESSING UNIT (Cont’d) Condition Code Register (CC) Read/Write Reset Value: 111x1xxx Bit 1 = Z Zero. 7 0 This bit is set and cleared by hardware. This bit indicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. 1 1 I1 H I0 N C Z This bit is accessed by the JREQ and JRNE test instructions. The 8-bit Condition Code register contains the interrupt masks and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. ) s t( Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and software. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. Arithmetic Management Bits c u d e t le Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instructions. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. u d o r P e t e l o s b O This bit is accessed by the JRMI and JRPL instructions. 18/172 o s b Interrupt Management Bits Bit 5,3 = I1, I0 Interrupt The combination of the I1 and I0 bits gives the current interrupt software priority. O ) s ( t c This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Bit 2 = N Negative. This bit is set and cleared by hardware. It is representative of the result sign of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th bit. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). o r P Interrupt Software Priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) I1 1 0 0 1 I0 0 1 0 1 These two bits are set/cleared by hardware when entering in interrupt. The loaded value is given by the corresponding bits in the interrupt software priority registers (IxSPR). They can be also set/ cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP instructions. See the interrupt management chapter for more details. ST72260Gx, ST72262Gx, ST72264Gx CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 7Fh 15 8 0 0 0 0 0 0 0 7 1 0 SP7 SP6 SP5 SP4 SP3 SP2 ) s t( SP0 SP1 c u d The Stack Pointer is a 16-bit register which is always pointing to the next free location in the stack. It is then decremented after data has been pushed onto the stack and incremented before data is popped from the stack (see Figure 8). Since the stack is 128 bytes deep, the 8 most significant bits are forced by hardware. Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack Pointer contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address. Interrupt Event u d o @ 0100h r P e t e l o s b O o r P o s b O ) PUSH Y POP Y RET or RSP IRET SP SP CC A Y CC A SP CC A X X X PCH PCH PCH PCL PCL PCL PCH PCH PCH PCH PCH PCL PCL PCL PCL PCL SP @ 017Fh e t le s ( t c Figure 8. Stack Manipulation Example CALL Subroutine The least significant byte of the Stack Pointer (called S) can be directly accessed by a LD instruction. Note: When the lower limit is exceeded, the Stack Pointer wraps around to the stack upper limit, without indicating the stack overflow. The previously stored information is then overwritten and therefore lost. The stack also wraps in case of an underflow. The stack is used to save the return address during a subroutine call and the CPU context during an interrupt. The user may also directly manipulate the stack by means of the PUSH and POP instructions. In the case of an interrupt, the PCL is stored at the first location pointed to by the SP. Then the other registers are stored in the next locations as shown in Figure 8 – When an interrupt is received, the SP is decremented and the context is pushed on the stack. – On return from interrupt, the SP is incremented and the context is popped from the stack. A subroutine call occupies two locations and an interrupt five locations in the stack area. SP SP Stack Higher Address = 017Fh Stack Lower Address = 0100h 19/172 ST72260Gx, ST72262Gx, ST72264Gx 6 SUPPLY, RESET AND CLOCK MANAGEMENT 6.1 PHASE LOCKED LOOP The device includes a range of utility features for securing the application in critical situations (for example in case of a power brown-out), and reducing the number of external components. An overview is shown in Figure 10. For more details, refer to dedicated parametric section. If the clock frequency input to the PLL is in the 2 to 4 MHz range, the PLL can be used to multiply the frequency by two to obtain an fOSC2 of 4 to 8 MHz. The PLL is enabled by option byte. If the PLL is disabled, then fOSC2 = fOSC/2. Caution: The PLL is not recommended for applications where timing accuracy is required. See “PLL Characteristics” on page 139. Main Features Optional PLL for multiplying the frequency by 2 (not to be used with internal RC oscillator) ■ Reset Sequence Manager (RSM) ■ Multi-Oscillator Clock Management (MO) – 4 Crystal/Ceramic resonator oscillators – 1 Internal RC oscillator ■ System Integrity Management (SI) – Main supply Low Voltage Detector (LVD) – Auxiliary Voltage Detector (AVD) with interrupt capability for monitoring the main supply ■ PLL x 2 MULTI- OSC2 fOSC OSCILLATOR OSC1 (MO) ol ete Pr RESET SEQUENCE bs RESET O MANAGER (RSM) od PLL (option) /2 c u d o r P fOSC2 1 e t le PLL OPTION BIT o s b O ) t(s MISCR1 Register SLOW MODE SELECTION fOSC2 MAIN CLOCK CONTROLLER WITH REALTIME CLOCK (MCC/RTC) SYSTEM INTEGRITY MANAGEMENT WATCHDOG AVD Interrupt Request SICSR 0 AVD AVD LVD F RF IE 0 0 TIMER (WDG) 0 LOW VOLTAGE VSS DETECTOR VDD (LVD) AUXILIARY VOLTAGE DETECTOR (AVD) 20/172 0 fOSC Figure 10. Clock, Reset and Supply Block Diagram uc ) s t( Figure 9. PLL Block Diagram WDG RF fCPU to CPU and Peripherals ST72260Gx, ST72262Gx, ST72264Gx 6.2 MULTI-OSCILLATOR (MO) ) s ( ct du e t e l O o s b o r P ) s t( c u d Table 3. ST7 Clock Sources o r P External Clock Hardware Configuration e t le ST7 o s b -O Crystal/Ceramic Resonators External Clock Source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Crystal/Ceramic Oscillators This family of oscillators has the advantage of producing a very accurate rate on the main clock of the ST7. The selection within a list of 5 oscillators with different frequency ranges has to be done by option byte in order to reduce consumption (refer to Section 15.1 on page 162 for more details on the frequency ranges). In this mode of the multioscillator, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. These oscillators are not stopped during the RESET phase to avoid losing time in the oscillator start-up phase. Internal RC Oscillator This oscillator allows a low cost solution for the main clock of the ST7 using only an internal resistor and capacitor. Internal RC oscillator mode has the drawback of a lower frequency accuracy and should not be used in applications that require accurate timing. In this mode, the two oscillator pins have to be tied to ground. Related documentation AN1530: Accurate timebase for low cost ST7 applications with internal RC. Internal RC Oscillator The main clock of the ST7 can be generated by four different source types coming from the multioscillator block: ■ an external source ■ 5 crystal or ceramic resonator oscillators ■ an internal high frequency RC oscillator Each oscillator is optimized for a given frequency range in terms of consumption and is selectable through the option byte. The associated hardware configurations are shown in Table 3. Refer to the electrical characteristics section for more details. Caution: The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure Mode and Effects Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left unconnected, the ST7 main oscillator may start and, in this configuration, could generate an fOSC clock frequency in excess of the allowed maximum (>16MHz.), putting the ST7 in an unsafe/undefined state. The product behaviour must therefore be considered undefined when the OSC pins are left unconnected. OSC1 OSC2 EXTERNAL SOURCE ST7 OSC1 CL1 OSC2 LOAD CAPACITORS CL2 ST7 OSC1 OSC2 21/172 ST72260Gx, ST72262Gx, ST72264Gx 6.3 RESET SEQUENCE MANAGER (RSM) 6.3.1 Introduction The reset sequence manager includes three RESET sources as shown in Figure 12: ■ External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic RESET sequence consists of 3 phases as shown in Figure 11: ■ Active Phase depending on the RESET source ■ 4096 CPU clock cycle delay (selected by option byte) ■ RESET vector fetch The 4096 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The shorter or longer clock cycle delay should be selected by option byte to correspond to the stabilization time of the external oscillator used in the application. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. RESET Sequence Phases RESET ) s t( 6.3.2 Asynchronous External RESET pin The RESET pin is both an input and an open-drain output with integrated RON weak pull-up resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It can be pulled low by external circuitry to reset the device. See Electrical Characteristic section for more details. A RESET signal originating from an external source must have a duration of at least th(RSTL)in in order to be recognized (see Figure 13). This detection is asynchronous and therefore the MCU can enter reset state even in HALT mode. c u d e t le o s b O ) r P e s b O 22/172 o r P u d o VDD t e l o FETCH VECTOR s ( t c Figure 12. Reset Block Diagram RESET INTERNAL RESET 4096 CLOCK CYCLES Active Phase RON INTERNAL RESET Filter PULSE GENERATOR WATCHDOG RESET LVD RESET ST72260Gx, ST72262Gx, ST72264Gx RESET SEQUENCE MANAGER (Cont’d) The RESET pin is an asynchronous signal which plays a major role in EMS performance. In a noisy environment, it is recommended to follow the guidelines mentioned in the electrical characteristics section. 6.3.3 External Power-On RESET If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must ensure by means of an external reset circuit that the reset signal is held low until VDD is over the minimum level specified for the selected fOSC frequency. A proper reset signal for a slow rising VDD supply can generally be provided by an external RC network connected to the RESET pin. 6.3.4 Internal Low Voltage Detector (LVD) RESET Two different RESET sequences caused by the internal LVD circuitry can be distinguished: ■ Power-On RESET ■ Voltage Drop RESET The device RESET pin acts as an output that is pulled low when VDD parity bit will be 1 if odd parity is selected (PS bit = 1). Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted but is changed by the parity bit. Reception mode: If the PCE bit is set then the interface checks if the received data byte has an ) s t( c u d e t le r P e t e l o s b O 94/172 o s b O ) s ( t c u d o even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is generated if PIE is set in the SCICR1 register. 11.5.4.8 SCI Clock Tolerance During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th samples is considered as the bit value. For a valid bit detection, all the three samples should have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and 10th samples are 0, 1 and 1 respectively, then the bit value will be “1”, but the Noise Flag bit is be set because the three samples values are not the same. Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples have the desired bit value. This means the clock frequency should not vary more than 6/16 (37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed 3.75%. Note: The internal sampling clock of the microcontroller samples the pin value on every falling edge. Therefore, the internal sampling clock and the time the application expects the sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit length is 64µs), then the 8th, 9th and 10th samples will be at 28µs, 32µs & 36µs respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal clock occurs just before the pin value changes, the samples would then be out of sync by ~4us. This means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs for synchronization with the internal sampling clock). o r P ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.4.9 Clock Deviation Causes The causes which contribute to the total deviation are: – DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the transmitter is transmitting at a different baud rate). – DQUANT: Error due to the baud rate quantisation of the receiver. – DREC: Deviation of the local oscillator of the receiver: This deviation can occur during the reception of one complete SCI message assuming that the deviation has been compensated at the beginning of the message. – DTCL: Deviation due to the transmission line (generally due to the transceivers) All the deviations of the system should be added and compared to the SCI clock tolerance: DTRA + DQUANT + DREC + DTCL < 3.75% 11.5.4.10 Noise Error Causes See also description of Noise error in Section 11.5.4.3. Start bit The noise flag (NF) is set during start bit reception if one of the following conditions occurs: 1. A valid falling edge is not detected. A falling edge is considered to be valid if the 3 consecutive samples before the falling edge occurs are detected as '1' and, after the falling edge occurs, during the sampling of the 16 samples, if one of the samples numbered 3, 5 or 7 is detected as a “1”. 2. During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is detected as a “1”. Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag getting set. Data Bits The noise flag (NF) is set during normal data bit reception if the following condition occurs: – During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not the same. The majority of the 8th, 9th and 10th samples is considered as the bit value. Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the Noise Flag getting set. ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o Figure 56. Bit Sampling in Reception Mode RDI LINE s b O Sample clock sampled values 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6/16 7/16 7/16 One bit time 95/172 ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.5 Low Power Modes Mode Description No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT Enable Exit Event Control from Flag Bit Wait Interrupt Event In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. Transmit Data Register TDRE Empty Transmission ComTC plete Received Data Ready RDRF to be Read Overrun Error Detected OR Idle Line Detected IDLE Parity Error PE 11.5.6 Interrupts The SCI interrupt events are connected to the same interrupt vector. These events generate an interrupt if the corresponding Enable Control Bit is set and the inter- o s b O ) s ( t c r P e t e l o s b O 96/172 TIE Yes No TCIE Yes No Yes No Yes Yes Yes No No No RIE ILIE PIE c u d ) s t( rupt mask in the CC register is reset (RIM instruction). e t le u d o Exit from Halt o r P ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) 11.5.7 Register Description Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line ocSTATUS REGISTER (SCISR) curs). Read Only Reset Value: 1100 0000 (C0h) Bit 3 = OR Overrun error. 7 0 This bit is set by hardware when the word currently being received in the shift register is ready to be TDRE TC RDRF IDLE OR NF FE PE transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the SCICR2 register. It is cleared by a software sequence (an Bit 7 = TDRE Transmit data register empty. access to the SCISR register followed by a read to This bit is set by hardware when the content of the the SCIDR register). TDR register has been transferred into the shift 0: No Overrun error register. An interrupt is generated if the TIE bit=1 1: Overrun error is detected in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register folNote: When this bit is set RDR register content will lowed by a write to the SCIDR register). not be lost but the shift register will be overwritten. 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Bit 2 = NF Noise flag. Note: Data will not be transferred to the shift regThis bit is set by hardware when noise is detected ister unless the TDRE bit is cleared. on a received frame. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). Bit 6 = TC Transmission complete. 0: No noise is detected This bit is set by hardware when transmission of a 1: Noise is detected frame containing Data is complete. An interrupt is generated if TCIE=1 in the SCICR2 register. It is Note: This bit does not generate interrupt as it apcleared by a software sequence (an access to the pears at the same time as the RDRF bit which itSCISR register followed by a write to the SCIDR self generates an interrupt. register). 0: Transmission is not complete 1: Transmission is complete Bit 1 = FE Framing error. This bit is set by hardware when a de-synchronizaNote: TC is not set after the transmission of a Pretion, excessive noise or a break character is deamble or a Break. tected. It is cleared by a software sequence (an access to the SCISR register followed by a read to Bit 5 = RDRF Received data ready flag. the SCIDR register). This bit is set by hardware when the content of the 0: No Framing error is detected RDR register has been transferred to the SCIDR 1: Framing error or break character is detected register. An interrupt is generated if RIE=1 in the Note: This bit does not generate interrupt as it apSCICR2 register. It is cleared by a software sepears at the same time as the RDRF bit which itquence (an access to the SCISR register followed self generates an interrupt. If the word currently by a read to the SCIDR register). being transferred causes both frame error and 0: Data is not received overrun error, it will be transferred and only the OR 1: Received data is ready to be read bit will be set. ) s t( c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is detected. An interrupt is generated if the ILIE=1 in the SCICR2 register. It is cleared by a software sequence (an access to the SCISR register followed by a read to the SCIDR register). 0: No Idle Line is detected 1: Idle Line is detected Bit 0 = PE Parity error. This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by a software sequence (a read to the status register followed by an access to the SCIDR data register). An interrupt is generated if PIE=1 in the SCICR1 register. 0: No parity error 1: Parity error 97/172 ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (SCICR1) Read/Write Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is Reset Value: x000 0000 (x0h) set or cleared by software. 0: Idle Line 7 0 1: Address Mark R8 T8 SCID M WAKE PCE PS PIE Bit 2 = PCE Parity control enable. This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data. This bit is set and cleared by software. Once it is set, PCE is active after the current byte (in reception and in transmission). 0: Parity control disabled 1: Parity control enabled Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. ) s t( c u d Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmitted word when M=1. e t le Bit 5 = SCID Disabled for low power consumption When this bit is set the SCI prescalers and outputs are stopped and the end of the current byte transfer in order to reduce power consumption.This bit is set and cleared by software. 0: SCI enabled 1: SCI prescaler and outputs disabled du e t e ol o r P Note: The M bit must not be modified during a data transfer (both transmission and reception). s b O 98/172 o s b Bit 1 = PS Parity selection. This bit selects the odd or even parity when the parity generation/detection is enabled (PCE bit set). It is set and cleared by software. The parity will be selected after the current byte. 0: Even parity 1: Odd parity O ) s ( t c Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit o r P Bit 0 = PIE Parity interrupt enable. This bit enables the interrupt capability of the hardware parity control when a parity error is detected (PE bit set). It is set and cleared by software. 0: Parity error interrupt disabled 1: Parity error interrupt enabled. ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 2 (SCICR2) Notes: Read/Write – During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle line) Reset Value: 0000 0000 (00h) after the current word. 7 0 – When TE is set there is a 1 bit-time delay before the transmission starts. TIE TCIE RIE ILIE TE RE RWU SBK Caution: The TDO pin is free for general purpose I/O only when the TE and RE bits are both cleared (or if TE is never set). Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: Interrupt is inhibited Bit 2 = RE Receiver enable. 1: An SCI interrupt is generated whenever This bit enables the receiver. It is set and cleared TDRE=1 in the SCISR register by software. 0: Receiver is disabled Bit 6 = TCIE Transmission complete interrupt ena1: Receiver is enabled and begins searching for a ble start bit This bit is set and cleared by software. 0: Interrupt is inhibited Bit 1 = RWU Receiver wake-up. 1: An SCI interrupt is generated whenever TC=1 in This bit determines if the SCI is in mute mode or the SCISR register not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is Bit 5 = RIE Receiver interrupt enable. recognized. This bit is set and cleared by software. 0: Receiver in Active mode 0: Interrupt is inhibited 1: Receiver in Mute mode 1: An SCI interrupt is generated whenever OR=1 Note: Before selecting Mute mode (setting the or RDRF=1 in the SCISR register RWU bit), the SCI must receive some data first, otherwise it cannot function in Mute mode with Bit 4 = ILIE Idle line interrupt enable. wakeup by idle line detection. This bit is set and cleared by software. 0: Interrupt is inhibited Bit 0 = SBK Send break. 1: An SCI interrupt is generated whenever IDLE=1 This bit set is used to send break characters. It is in the SCISR register. set and cleared by software. ) s t( c u d e t le o r P o s b O ) s ( t c u d o let r P e Bit 3 = TE Transmitter enable. This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled O o s b 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word. 99/172 ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data character, depending on whether it is read from or written to. 7 Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in conventional Baud Rate Generator mode. TR dividing factor SCT2 SCT1 SCT0 1 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift register (see Figure 53). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 53). BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h) SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 o r P SCR1 SCR0 Bits 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: e t e ol PR Prescaling factor SCP1 SCP0 1 0 0 3 0 1 4 1 0 13 1 1 bs O 100/172 1 r P e 1 1 0 1 t e l o s b O RR Dividing factor SCR2 SCR1 SCR0 1 0 0 0 2 0 0 1 4 0 1 0 )- 0 od 1 1 uc Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. t(s c u d 7 64 128 ) s t( 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (SCIERPR) Read/Write Reset Value: 0000 0000 (00h) Allows setting of the Extended Prescaler rate division factor for the receive circuit. 7 EXTENDED TRANSMIT PRESCALER DIVISION REGISTER (SCIETPR) Read/Write Reset Value:0000 0000 (00h) Allows setting of the External Prescaler rate division factor for the transmit circuit. 0 7 ERPR ERPR ERPR ERPR ERPR ERPR ERPR ERPR 7 6 5 4 3 2 1 0 ETPR 7 0 ETPR 6 ETPR 5 ETPR 4 ETPR 3 ETPR 2 ETPR ETPR 1 0 ) s t( c u d Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 55) is divided by the binary factor set in the SCIERPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset. Bits 7:0 = ETPR[7:0] 8-bit Extended Transmit Prescaler Register. The extended Baud Rate Generator is activated when a value different from 00h is stored in this register. Therefore the clock frequency issued from the 16 divider (see Figure 55) is divided by the binary factor set in the SCIETPR register (in the range 1 to 255). The extended baud rate generator is not used after a reset. e t le o r P o s b O ) Table 19. Baudrate Selection Conditions Symbol Parameter fCPU t(s Accuracy vs. Standard c u d fTx fRx e t e ol o r P ~0.16% Communication frequency 8MHz s b O ~0.79% Prescaler Conventional Mode TR (or RR)=128, PR=13 TR (or RR)= 32, PR=13 TR (or RR)= 16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 16, PR= 3 TR (or RR)= 2, PR=13 TR (or RR)= 1, PR=13 Extended Mode ETPR (or ERPR) = 35, TR (or RR)= 1, PR=1 Standard Baud Rate Unit 300 ~300.48 1200 ~1201.92 2400 ~2403.84 4800 ~4807.69 9600 ~9615.38 10400 ~10416.67 19200 ~19230.77 38400 ~38461.54 Hz 14400 ~14285.71 101/172 ST72260Gx, ST72262Gx, ST72264Gx SERIAL COMMUNICATIONS INTERFACE (Cont’d) Table 20. SCI Register Map and Reset Values Address Register Name (Hex.) 7 6 5 4 3 2 1 0 50 SCISR Reset Value TDRE 1 TC 1 RDRF 0 IDLE 0 OR 0 NF 0 FE 0 PE 0 51 SCIDR Reset Value DR7 x DR6 x DR5 x DR4 x DR3 x DR2 x DR1 x DR0 x 52 SCIBRR Reset Value SCP1 0 SCP0 0 SCT2 0 SCT1 0 SCT0 0 SCR2 0 SCR1 0 SCR0 0 53 SCICR1 Reset Value R8 x T8 0 SCID 0 M 0 WAKE 0 PCE 0 PS 0 PIE 0 54 SCICR2 Reset Value TIE 0 TCIE 0 RIE 0 ILIE 0 TE 0 RE 0 RWU 0 SBK 0 55 SCIERPR Reset Value ERPR7 0 ERPR6 0 ERPR5 0 ERPR4 0 ERPR3 0 ERPR2 0 ERPR1 0 ERPR0 0 56 SCIETPR Reset Value ETPR7 0 ETPR6 0 ETPR5 0 ETPR4 0 ETPR3 0 ETPR2 0 ETPR1 0 ETPR0 0 O ) o s b s ( t c u d o r P e t e l o s b O 102/172 e t le ) s t( c u d o r P ST72260Gx, ST72262Gx, ST72264Gx 11.6 I2C BUS INTERFACE (I2C) 11.6.1 Introduction The I2C Bus Interface serves as an interface between the microcontroller and the serial I2C bus. It provides both multimaster and slave functions, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports fast I2C mode (400kHz). 11.6.2 Main Features 2 ■ Parallel-bus/I C protocol converter ■ Multi-master capability ■ 7-bit/10-bit Addressing ■ SMBus V1.1 Compliant ■ Transmitter/Receiver flag ■ End-of-byte transmission flag ■ Transfer problem detection I2C Master Features: ■ Clock generation 2 ■ I C bus busy flag ■ Arbitration Lost Flag ■ End of byte transmission flag ■ Transmitter/Receiver Flag ■ Start bit detection flag ■ Start and Stop generation I2C Slave Features: ■ Stop bit detection 2 ■ I C bus busy flag ■ Detection of misplaced start or stop condition 2 ■ Programmable I C Address detection ■ Transfer problem detection ■ End-of-byte transmission flag ■ Transmitter/Receiver flag 11.6.3 General Description In addition to receiving and transmitting data, this interface converts it from serial to parallel format ) s t( c u d e t le r P e t e l o s b O o r P o s b O ) s ( t c u d o and vice versa, using either an interrupt or polled handshake. The interrupts are enabled or disabled by software. The interface is connected to the I2C bus by a data pin (SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a Fast I2C bus. This selection is made by software. Mode Selection The interface can operate in the four following modes: – Slave transmitter/receiver – Master transmitter/receiver By default, it operates in slave mode. The interface automatically switches from slave to master after it generates a START condition and from master to slave in case of arbitration loss or a STOP generation, allowing then Multi-Master capability. Communication Flow In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always begins with a start condition and ends with a stop condition. Both start and stop conditions are generated in master mode by software. In Slave mode, the interface is capable of recognising its own address (7 or 10-bit), and the General Call address. The General Call address detection may be enabled or disabled by software. Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send an acknowledge bit to the transmitter. Refer to Figure 57. Figure 57. I2C BUS Protocol SDA ACK MSB SCL 1 START CONDITION 2 8 9 STOP CONDITION VR02119B 103/172 ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) Acknowledge may be enabled and disabled by software. The I2C interface address and/or general call address can be selected by software. The speed of the I2C interface may be selected between Standard (up to 100KHz) and Fast I2C (up to 400KHz). SDA/SCL Line Control Transmitter mode: the interface holds the clock line low before transmission to wait for the microcontroller to write the byte in the Data Register. Receiver mode: the interface holds the clock line low after reception to wait for the microcontroller to read the byte in the Data Register. The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the I2C bus mode. When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. ) s t( c u d Figure 58. I2C Interface Block Diagram e t le o r P DATA REGISTER (DR) o s b SDA or SDAI DATA CONTROL -O DATA SHIFT REGISTER ) s ( ct u d o s b O e t e ol SCL or SCLI Pr COMPARATOR OWN ADDRESS REGISTER 1 (OAR1) OWN ADDRESS REGISTER 2 (OAR2) CLOCK CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTER (CR) STATUS REGISTER 1 (SR1) CONTROL LOGIC STATUS REGISTER 2 (SR2) INTERRUPT 104/172 ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) 11.6.4 Functional Description Refer to the CR, SR1 and SR2 registers in Section 11.6.7. for the bit definitions. By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a transmit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2 register. 11.6.4.1 Slave Mode As soon as a start condition is detected, the address is received from the SDA line and sent to the shift register; then it is compared with the address of the interface or the General Call address (if selected by software). Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two most significant bits of the address. Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit is set. Address not matched: the interface ignores it and waits for another Start condition. Address matched: the interface generates in sequence: – Acknowledge pulse if the ACK bit is set. – EVF and ADSL bits are set with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register, holding the SCL line low (see Figure 59 Transfer sequencing EV1). Next, in 7-bit mode read the DR register to determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode. In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit mode on receiving a repeated Start condition followed by the header sequence with matching address bits and the least significant bit set (11110xx1). Slave Receiver Following the address reception and after SR1 register has been read, the slave receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: – Acknowledge pulse if the ACK bit is set – EVF and BTF bits are set with an interrupt if the ITE bit is set. ) s t( c u d e t le r P e s b O t e l o o r P o s b O ) s ( t c u d o Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV2). Slave Transmitter Following the address reception and after SR1 register has been read, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV3). When the acknowledge pulse is received: – The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: – EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see Figure 59 Transfer sequencing EV4). Error Cases – BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data, released the lines and waits for another Start condition. If it is a Start then the interface discards the data and waits for the next slave address on the bus. – AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the ITE bit is set. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. Note: In case of errors, SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. While AF=1, the SCL line may be held low due to SB or BTF flags that are set at the same time. It is then necessary to release both lines by software. 105/172 ST72260Gx, ST72262Gx, ST72264Gx I2C INTERFACE (Cont’d) How to release the SDA / SCL lines Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released after the transfer of the current byte. Then the second address byte is sent by the interface. SMBus Compatibility ST7 I2C is compatible with SMBus V1.1 protocol. It supports all SMBus adressing modes, SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave Driver For ST7 I2C Peripheral. After completion of this transfer (and acknowledge from the slave if the ACK bit is set): – The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the CR register (for example set PE bit), holding the SCL line low (see Figure 59 Transfer sequencing EV6). ) s t( c u d 11.6.4.2 Master Mode To switch from default Slave mode to Master mode a Start condition generation is needed. Start condition Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master mode (M/SL bit set) and generates a Start condition. Once the Start condition is sent: – The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register with the Slave address, holding the SCL line low (see Figure 59 Transfer sequencing EV5). Next the master must enter Receiver or Transmitter mode. Note: In 10-bit addressing mode, to switch the master to Receiver mode, software must generate a repeated Start condition and resend the header sequence with the least significant bit set (11110xx1). e t le r P e t e l o Slave address transmission Then the slave address is sent to the SDA line via the internal shift register. In 7-bit addressing mode, one address byte is sent. In 10-bit addressing mode, sending the first byte including the header sequence causes the following event: – The EVF bit is set by hardware with interrupt generation if the ITE bit is set. Then the master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV9). s b O 106/172 Master Receiver Following the address transmission and after SR1 and CR registers have been accessed, the master receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: – Acknowledge pulse if the ACK bit is set – EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV7). To close the communication: before reading the last byte from the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. O ) s ( t c u d o o s b o r P ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) Master Transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, holding the SCL line low (see Figure 59 Transfer sequencing EV8). When the acknowledge bit is received, the interface sets: – EVF and BTF bits with an interrupt if the ITE bit is set. To close the communication: after writing the last byte to the DR register, set the STOP bit to generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Error Cases – BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and BERR bits are set by hardware with an interrupt if ITE is set. Note that BERR will not be set if an error is detected during the first or second pulse of each 9bit transaction: Single Master Mode If a Start or Stop is issued during the first or second pulse of a 9-bit transaction, the BERR flag will not be set and transfer will continue however the BUSY flag will be reset. To work around this, slave devices should issue a NACK when they receive a misplaced Start or Stop. The reception of a NACK or BUSY by the master in the middle ) s t( c u d e t le r P e t e l o o r P o s b O ) s ( t c u d o of communication gives the possibility to reinitiate transmission. Multimaster Mode Normally the BERR bit would be set whenever unauthorized transmission takes place while transfer is already in progress. However, an issue will arise if an external master generates an unauthorized Start or Stop while the I2C master is on the first or second pulse of a 9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C master mode transmission. The resetting of the BUSY bit can then be handled in a similar manner as the BERR flag being set. – AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit. The AF bit is cleared by reading the I2CSR2 register. However, if read before the completion of the transmission, the AF flag will be set again, thus possibly generating a new interrupt. Software must ensure either that the SCL line is back at 0 before reading the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse of a transmitted byte. – ARLO: Detection of an arbitration lost condition. In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and the interface goes automatically back to slave mode (the M/SL bit is cleared). Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to possible «0» bits transmitted last. It is then necessary to release both lines by software. s b O 107/172 ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) Figure 59. Transfer Sequencing 7-bit Slave receiver: S Address A Data1 A Data2 EV1 A EV2 EV2 DataN ..... A P EV2 EV4 7-bit Slave transmitter: S Address A Data1 A EV1 EV3 Data2 A EV3 DataN ..... EV3 NA P EV3-1 7-bit Master receiver: S Address A EV5 Data1 A EV6 Data2 A EV7 DataN ..... EV7 Address A EV5 Data1 A Data2 EV6 EV8 o r P S Header A Address A Data1 A EV1 ) (s ct Sr Header A u d o 10-bit Master transmitter S Header EV5 r P e A Address EV9 t e l o Data1 DataN A EV3 Data1 A EV6 EV8 EV8 A P EV8 P EV2 A EV1 EV3 A DataN l o s Ob ..... EV2 10-bit Slave transmitter: e t e ..... EV8 10-bit Slave receiver: P EV7 A EV8 ) s t( c u d NA 7-bit Master transmitter: S EV4 .... DataN . EV4 A P EV3-1 DataN ..... EV4 A P EV8 10-bit Master receiver: bs O Sr Header EV5 A Data1 EV6 A EV7 ..... DataN A P EV7 Legend: S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge, EVx=Event (with interrupt if ITE=1) EV1: EVF=1, ADSL=1, cleared by reading SR1 register. EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by releasing the lines (STOP=1, STOP=0) or by writing DR register (DR=FFh). Note: If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register. 108/172 ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) 11.6.5 Low Power Modes Mode WAIT HALT Description No effect on I2C interface. I2C interrupts cause the device to exit from WAIT mode. I2C registers are frozen. In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus. The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit from HALT mode” capability. 11.6.6 Interrupts ) s t( Figure 60. Event Flags and Interrupt Generation ADD10 BTF ADSL SB AF STOPF ARLO BERR c u d ITE o r P INTERRUPT e t le * * EVF can also be set by EV6 or an error from the SR2 register. Interrupt Event ) s ( ct 10-bit Address Sent Event (Master mode) End of Byte Transfer Event Address Matched Event (Slave mode) Start Bit Generation Event (Master mode) Acknowledge Failure Event Stop Detection Event (Slave mode) Arbitration Lost Event (Multimaster configuration) Bus Error Event u d o e t e ol Pr -O o s b EVF Event Flag Enable Control Bit ADD10 BTF ADSEL SB AF STOPF ARLO BERR ITE Exit from Wait Yes Yes Yes Yes Yes Yes Yes Yes Exit from Halt No No No No No No No No s b O Note: The I2C interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset (RIM instruction). 109/172 ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) 11.6.7 Register Description I2C CONTROL REGISTER (CR) Read / Write Reset Value: 0000 0000 (00h) – In slave mode: 0: No start generation 1: Start generation when the bus is free 7 Bit 2 = ACK Acknowledge enable. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). 0: No acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received 0 0 0 PE ENGC START ACK STOP ITE ) s t( Bit 7:6 = Reserved. Forced to 0 by hardware. c u d Bit 5 = PE Peripheral enable. This bit is set and cleared by software. 0: Peripheral disabled 1: Master/Slave capability Notes: – When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset. All outputs are released while PE=0 – When PE=1, the corresponding I/O pins are selected by hardware as alternate functions. – To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only activates the interface (only PE is set). e t le u d o r P e t e l o Note: In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can only receive data. It will not transmit data to the master. s b O Bit 3 = START Generation of a Start condition. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0) or when the Start condition is sent (with interrupt generation if ITE=1). – In master mode: 0: No start generation 1: Repeated start generation 110/172 o r P o s b O ) s ( t c Bit 4 = ENGC Enable General Call. This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored). 0: General Call disabled 1: General Call enabled Bit 1 = STOP Generation of a Stop condition. This bit is set and cleared by software. It is also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). – In master mode: 0: No stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent. The STOP bit is cleared by hardware when the Stop condition is sent. – In slave mode: 0: No stop generation 1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode the STOP bit has to be cleared by software. Bit 0 = ITE Interrupt enable. This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE=0). 0: Interrupts disabled 1: Interrupts enabled Refer to Figure 60 for the relationship between the events and the interrupt. SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See Figure 59) is detected. ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) I2C STATUS REGISTER 1 (SR1) Read Only Reset Value: 0000 0000 (00h) 1: Data byte transmitted 7 EVF 0 Bit 4 = BUSY Bus busy. This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs. 0: No communication on the bus 1: Communication ongoing on the bus Note: – The BUSY flag is NOT updated when the interface is disabled (PE=0). This can have consequences when operating in Multimaster mode; i.e. a second active I2C master commencing a transfer with an unset BUSY bit can cause a conflict resulting in lost data. A software workaround consists of checking that the I2C is not busy before enabling the I2C Multimaster cell. ADD10 TRA BUSY BTF ADSL M/SL SB Bit 7 = EVF Event flag. This bit is set by hardware as soon as an event occurs. It is cleared by software reading SR2 register in case of error event or as described in Figure 59. It is also cleared by hardware when the interface is disabled (PE=0). 0: No event 1: One of the following events has occurred: – BTF=1 (Byte received or transmitted) – ADSL=1 (Address matched in Slave mode while ACK=1) – SB=1 (Start condition generated in Master mode) – AF=1 (No acknowledge received after byte transmission) – STOPF=1 (Stop condition detected in Slave mode) – ARLO=1 (Arbitration lost in Master mode) – BERR=1 (Bus error, misplaced Start or Stop condition detected) – ADD10=1 (Master has sent header byte) – Address byte successfully transmitted in Master mode. ) s t( c u d e t le r P e t e l o Bit 6 = ADD10 10-bit addressing in Master mode. This bit is set by hardware when the master has sent the first byte in 10-bit address mode. It is cleared by software reading SR2 register followed by a write in the DR register of the second address byte. It is also cleared by hardware when the peripheral is disabled (PE=0). 0: No ADD10 event occurred. 1: Master has sent first address byte (header) s b O Bit 5 = TRA Transmitter/Receiver. When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically when BTF is cleared. It is also cleared by hardware after detection of Stop condition (STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0). 0: Data byte received (if BTF=1) o s b Bit 3 = BTF Byte transfer finished. This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by a read or write of DR register. It is also cleared by hardware when the interface is disabled (PE=0). – Following a byte transmission, this bit is set after reception of the acknowledge clock pulse. In case an address byte is sent, this bit is set only after the EV6 event (See Figure 59). BTF is cleared by reading SR1 register followed by writing the next byte in DR register. – Following a byte reception, this bit is set after transmission of the acknowledge clock pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte from DR register. The SCL line is held low while BTF=1. 0: Byte transfer not done 1: Byte transfer succeeded O ) s ( t c u d o o r P Bit 2 = ADSL Address matched (Slave mode). This bit is set by hardware as soon as the received slave address matched with the OAR register content or a general call is recognized. An interrupt is generated if ITE=1. It is cleared by software reading SR1 register or by hardware when the interface is disabled (PE=0). The SCL line is held low while ADSL=1. 0: Address mismatched or not received 1: Received address matched 111/172 ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) Bit 1 = M/SL Master/Slave. This bit is set by hardware as soon as the interface is in Master mode (writing START=1). It is cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0). 0: Slave mode 1: Master mode Bit 0 = SB Start bit (Master mode). This bit is set by hardware as soon as the Start condition is generated (following a write START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1 register followed by writing the address byte in DR register. It is also cleared by hardware when the interface is disabled (PE=0). 0: No Start condition 1: Start condition generated The SCL line is not held low while STOPF=1. 0: No Stop condition detected 1: Stop condition detected ) s t( c u d e t le I2C STATUS REGISTER 2 (SR2) Read Only Reset Value: 0000 0000 (00h) 7 0 0 s ( t c AF STOPF ARLO BERR GCAL u d o Bit 7:5 = Reserved. Forced to 0 by hardware. r P e Bit 4 = AF Acknowledge failure. This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time. 0: No acknowledge failure 1: Acknowledge failure Note: – When an AF event occurs, the SCL line is not held low; however, the SDA line can remain low if the last bits transmitted are all 0. It is then necessary to release both lines by software. t e l o s b O Bit 3 = STOPF Stop detection (Slave mode). This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). 112/172 o r P o s b O ) 0 0 Bit 2 = ARLO Arbitration lost. This bit is set by hardware when the interface loses the arbitration of the bus to another master. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). After an ARLO event the interface switches back automatically to Slave mode (M/SL=0). The SCL line is not held low while ARLO=1. 0: No arbitration lost detected 1: Arbitration lost detected Note: – In a Multimaster environment, when the interface is configured in Master Receive mode it does not perform arbitration during the reception of the Acknowledge Bit. Mishandling of the ARLO bit from the I2CSR2 register may occur when a second master simultaneously requests the same data from the same slave and the I2C master does not acknowledge the data. The ARLO bit is then left at 0 instead of being set. Bit 1 = BERR Bus error. This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR=1. 0: No misplaced Start or Stop condition 1: Misplaced Start or Stop condition Note: – If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication Bit 0 = GCAL General Call (Slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the interface is disabled (PE=0). 0: No general call address detected on bus 1: general call address detected on bus ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) I2C CLOCK CONTROL REGISTER (CCR) Read / Write Reset Value: 0000 0000 (00h) 7 I2C DATA REGISTER (DR) Read / Write Reset Value: 0000 0000 (00h) FM/SM CC6 CC5 CC4 CC3 CC2 CC1 0 7 CC0 D7 Bit 7 = FM/SM Fast/Standard I2C mode. This bit is set and cleared by software. It is not cleared when the interface is disabled (PE=0). 0: Standard I2C mode 1: Fast I2C mode 0 D6 D5 D4 D3 D2 D1 D0 ) s t( Bit 7:0 = D[7:0] 8-bit Data Register. These bits contain the byte to be received or transmitted on the bus. – Transmitter mode: Byte transmission start automatically when the software writes in the DR register. – Receiver mode: the first data byte is received automatically in the DR register using the least significant bit of the address. Then, the following data bytes are received one by one after reading the DR register. Bit 6:0 = CC[6:0] 7-bit clock divider. These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not cleared when the interface is disabled (PE=0). Refer to the Electrical Characteristics section for the table of values. Note: The programmed FSCL assumes no load on SCL and SDA lines. c u d e t le o r P o s b O ) s ( t c u d o r P e t e l o s b O 113/172 ST72260Gx, ST72262Gx, ST72264Gx I2C BUS INTERFACE (Cont’d) I2C OWN ADDRESS REGISTER (OAR1) Read / Write Reset Value: 0000 0000 (00h) 7 I2C OWN ADDRESS REGISTER (OAR2) Read / Write Reset Value: 0100 0000 (40h) ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 0 7 ADD0 FR1 7-bit Addressing Mode Bit 7:1 = ADD[7:1] Interface address. These bits define the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). 0 FR0 0 0 0 ADD9 ADD8 0 Bit 7:6 = FR[1:0] Frequency bits. These bits are set by software only when the interface is disabled (PE=0). To configure the interface to I2C specified delays select the value corresponding to the microcontroller frequency FCPU. ) s t( fCPU < 6 MHz 6 to 8 MHz FR1 0 0 o r P c u d FR0 0 1 Bit 0 = ADD0 Address direction bit. This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when the interface is disabled (PE=0). Note: Address 01h is always ignored. Bit 5:3 = Reserved 10-bit Addressing Mode Bit 7:0 = ADD[7:0] Interface address. These are the least significant bits of the I2C bus address of the interface. They are not cleared when the interface is disabled (PE=0). Bit 2:1 = ADD[9:8] Interface address. These are the most significant bits of the I2C bus address of the interface (10-bit mode only). They are not cleared when the interface is disabled (PE=0). e t le O ) s ( t c du e t e ol s b O 114/172 o r P o s b Bit 0 = Reserved. ST72260Gx, ST72262Gx, ST72264Gx I²C BUS INTERFACE (Cont’d) Table 21. I2C Register Map and Reset Values Address (Hex.) Register Label 7 6 5 4 3 2 1 0 0028h I2CCR Reset Value 0 0 PE 0 ENGC 0 START 0 ACK 0 STOP 0 ITE 0 0029h I2CSR1 Reset Value EVF 0 ADD10 0 TRA 0 BUSY 0 BTF 0 ADSL 0 M/SL 0 SB 0 002Ah I2CSR2 Reset Value 0 0 0 AF 0 STOPF 0 ARLO 0 BERR 0 GCAL 0 02Bh I2CCCR Reset Value FM/SM 0 CC6 0 CC5 0 CC4 0 CC3 0 CC2 0 CC1 0 CC0 0 02Ch I2COAR1 Reset Value ADD7 0 ADD6 0 ADD5 0 ADD4 0 ADD3 0 ADD2 0 002Dh I2COAR2 Reset Value FR1 0 FR0 1 0 0 0 002Eh I2CDR Reset Value MSB 0 0 0 0 ) s ( ct b O - l o s e t e 0 ADD9 0 0 ) s t( o r P c u d ADD1 0 ADD0 0 ADD8 0 0 0 LSB 0 u d o r P e t e l o s b O 115/172 ST72260Gx, ST72262Gx, ST72264Gx 11.7 10-BIT A/D CONVERTER (ADC) 11.7.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has 6 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from 6 different sources. The result of the conversion is stored in a 10-bit Data Register. The A/D converter is controlled through a Control/Status Register. Data register (DR) which contains the results Conversion complete status flag ■ On/off bit (to reduce consumption) The block diagram is shown in Figure 61. ■ ■ 11.7.3 Functional Description 11.7.3.1 Analog Power Supply VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to device pin out description) they are internally connected to the VDD and VSS pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. ) s t( c u d 11.7.2 Main Features ■ 10-bit conversion ■ 6 channels with multiplexed input ■ Linear successive approximation e t le Figure 61. ADC Block Diagram fCPU O ) s ( t c EOC SPEED ADON SLOW o s b fADC fCPU, fCPU/2, fCPU/4 0 CH2 CH1 CH0 ADCCSR u d o 3 r P e AIN0 t e l o AIN1 s b O o r P ANALOG TO DIGITAL ANALOG MUX CONVERTER AINx ADCDRH D9 D8 ADCDRL 116/172 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 D0 ST72260Gx, ST72262Gx, ST72264Gx 10-BIT A/D CONVERTER (ADC) (Cont’d) 11.7.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the result never decreases if the analog input does not and never increases if the analog input does not. If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without overflow indication). If the input voltage (VAIN) is lower than VSSA (lowlevel voltage reference) then the conversion result in the ADCDRH and ADCDRL registers is 00 00h. The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH and ADCDRL registers. The accuracy of the conversion is described in the Electrical Characteristics Section. RAIN is the maximum recommended impedance for an analog input signal. If the impedance is too high, this will result in a loss of accuracy due to leakage and sampling not being completed in the alloted time. 11.7.3.3 A/D Conversion The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the «I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. In the ADCCSR register: – Select the CH[2:0] bits to assign the analog channel to convert. When a conversion is complete: – The EOC bit is set by hardware. – The result is in the ADCDR registers. A read to the ADCDRH or a write to any bit of the ADCCSR resets the EOC bit. To read the 10 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRL. This locks the ADCDRH until it is read. 3. Read ADCDRH. This clears EOC automatically. ) s t( c u d e t le r P e ADC Conversion mode In the ADCCSR register: - Set the SPEED or the SLOW bits – Set the ADON bit to enable the A/D converter and to start the conversion. From this time on, the ADC performs a continuous conversion of the selected channel. let O o s b o s b 11.7.4 Low Power Modes Note: The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced power consumption when no conversion is needed and between single shot conversions. O ) s ( t c u d o o r P To read only 8 bits, perform the following steps: 1. Poll EOC bit 2. Read ADCDRH. This clears EOC automatically. Mode WAIT HALT Description No effect on A/D Converter A/D Converter disabled. After wakeup from Halt mode, the A/D Converter requires a stabilization time tSTAB (see Electrical Characteristics) before accurate conversions can be performed. 11.7.5 Interrupts None. 117/172 ST72260Gx, ST72262Gx, ST72264Gx 10-BIT A/D CONVERTER (ADC) (Cont’d) 11.7.6 Register Description CONTROL/STATUS REGISTER (ADCCSR) Read/Write (Except bit 7 read only) Reset Value: 0000 0000 (00h) Bit 2:0 = CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. 7 Channel Pin CH2 CH1 CH0 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 EOC SPEED ADON SLOW 0 CH2 CH1 CH0 Bit 7 = EOC End of Conversion This bit is set by hardware. It is cleared by software reading the ADCDRH register or writing to any bit of the ADCCSR register. 0: Conversion is not complete 1: Conversion complete Bit 6 = SPEED A/D clock selection This bit is set and cleared by software. D9 SLOW fCPU (See Note 2) 0 1 0 1 fCPU/2 fCPU/4 SPEED ) s ( ct u d o 1)The 1 1 0 0 SPEED and SLOW bits must be updated before setting the ADON bit. r P e Use this setting only if fCPU ≤ 4 MHz 2) let Bit 5 = ADON A/D Converter on This bit is set and cleared by software. 0: Disable ADC and stop conversion 1: Enable ADC and start conversion so Ob Bit 4 = SLOW A/D Clock Selection This bit is set and cleared by software. It works together with the SPEED bit. Refer to Table 22. 118/172 D8 b O - so D7 D6 c u d o r P e t le 7 Table 22. A/D Clock Selection (See Note 1) fADC Frequency DATA REGISTER (ADCDRH) Read Only Reset Value: 0000 0000 (00h) ) s t( 0 D5 D4 D3 D2 Bit 7:0 = D[9:2] MSB of Analog Converted Value DATA REGISTER (ADCDRL) Read Only Reset Value: 0000 0000 (00h) 7 0 0 0 0 0 0 0 D1 D0 Bit 7:2 = Reserved. Forced by hardware to 0. Bit 1:0 = D[1:0] LSB of Analog Converted Value ST72260Gx, ST72262Gx, ST72264Gx 10-BIT A/D CONVERTER (ADC) (Cont’d) Table 23. ADC Register Map and Reset Values Address Register Label 7 6 5 4 3 2 1 0 006Fh ADCDRL Reset Value 0 0 0 0 0 0 D1 0 D0 0 0070h ADCDRH Reset Value D9 0 D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 0071h ADCCSR Reset Value EOC 0 SPEED 0 ADON 0 SLOW 0 0 CH2 0 CH1 0 CH0 0 (Hex.) e t le ) s t( c u d o r P o s b O ) s ( t c u d o r P e t e l o s b O 119/172 ST72260Gx, ST72262Gx, ST72264Gx 12 INSTRUCTION SET 12.1 CPU ADDRESSING MODES so, most of the addressing modes may be subdivided in two sub-modes called long and short: – Long addressing mode is more powerful because it can use the full 64 Kbyte address space, however it uses more bytes and more CPU cycles. – Short addressing mode is less powerful because it can generally only access page zero (0000h 00FFh range), but the instruction size is more compact, and faster. All memory to memory instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP) The ST7 Assembler optimizes the use of long and short addressing modes. The CPU features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld A,($55,X) Indirect ld A,([$55],X) Relative jrne loop Bit operation bset ) s t( c u d byte,#5 The CPU Instruction set is designed to minimize the number of bytes required per instruction: To do e t le Table 24. CPU Addressing Mode Overview Mode Syntax Inherent nop Immediate ld A,#$55 Direct ld A,$10 Long Direct ld A,$1000 No Offset Direct Short Direct Long Direct Long Ob Short Pointer Size (Hex.) Length (Bytes) +0 +1 00..FF +1 0000..FFFF +2 ld A,(X) 00..FF +0 ld A,($10,X) 00..1FE +1 ld A,($1000,X) 0000..FFFF +2 Indirect ld A,[$10] 00..FF 00..FF byte +2 Indirect ld A,[$10.w] 0000..FFFF 00..FF word +2 d o r Indexed P e let so Short O ) Pointer Address (Hex.) t(s uc Short o s b Destination o r P Indexed Indexed Indirect Indexed ld A,([$10],X) 00..1FE 00..FF byte +2 Long Indirect Indexed ld A,([$10.w],X) 0000..FFFF 00..FF word +2 Relative Direct jrne loop PC+/-127 Relative Indirect jrne [$10] PC+/-127 Bit Direct bset $10,#7 00..FF Bit Indirect bset [$10],#7 00..FF Bit Direct Relative btjt $10,#7,skip 00..FF Bit Indirect Relative btjt [$10],#7,skip 00..FF 120/172 +1 00..FF byte +2 +1 00..FF byte +2 +2 00..FF byte +3 ST72260Gx, ST72262Gx, ST72264Gx INSTRUCTION SET OVERVIEW (Cont’d) 12.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required information for the CPU to process the operation. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask (level 3) RIM Reset Interrupt Mask (level 0) SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles t e l o 12.1.2 Immediate Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. s b O Immediate Instruction Function Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations c u d o r P 12.1.4 Indexed (No Offset, Short, Long) In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte after the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. e t le O ) s ( t c u d o r P e ) s t( o s b CLR LD 12.1.3 Direct In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two submodes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF addressing space. Direct (long) The address is a word, thus allowing 64 Kbyte addressing space, but requires 2 bytes after the opcode. 12.1.5 Indirect (Short, Long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. 121/172 ST72260Gx, ST72262Gx, ST72264Gx INSTRUCTION SET OVERVIEW (Cont’d) 12.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the unsigned addition of an index register value (X or Y) with a pointer value located in memory. The pointer address follows the opcode. The indirect indexed addressing mode consists of two sub-modes: Indirect Indexed (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing space, and requires 1 byte after the opcode. 12.1.7 Relative mode (Direct, Indirect) This addressing mode is used to modify the PC register value, by adding an 8-bit signed offset to it. Available Relative Direct/Indirect Instructions LD Load CP Compare AND, OR, XOR Logical Operations r P e ADC, ADD, SUB, SBC BCP t e l o s b O Bit Compare Short Instructions Only CLR u d o Function Clear INC, DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement BSET, BRES Bit Operations BTJT, BTJF Bit Test and Jump Operations SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles CALL, JP Call or Jump subroutine 122/172 Call Relative e t le o s b O ) s ( t c Arithmetic Additions/Substractions operations Conditional Jump CALLR ) s t( c u d Table 25. Instructions Supporting Direct, Indexed, Indirect and Indirect Indexed Addressing Modes Function JRxx The relative addressing mode consists of two submodes: Relative (Direct) The offset is following the opcode. Relative (Indirect) The offset is defined in memory, which address follows the opcode. Indirect Indexed (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Long and Short Instructions Function o r P ST72260Gx, ST72262Gx, ST72264Gx INSTRUCTION SET OVERVIEW (Cont’d) 12.2 INSTRUCTION GROUPS The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Load and Transfer LD CLR Stack operation PUSH POP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP Conditional Branch JRxx Interruption management TRAP WFI HALT Condition Code Flag modification SIM RIM SCF Using a pre-byte The instructions are described with one to four opcodes. In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three different prebyte opcodes are defined. These prebytes modify the meaning of the instruction they precede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address RSP r P e t e l o s b O These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: ) s t( NEG c u d e t le o r P RET o s b O ) s ( t c u d o CPL IRET RCF PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, direct bit, or direct relative addressing mode to an instruction using the corresponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruction using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. 12.2.1 Illegal Opcode Reset In order to provide enhanced robustness to the device against unexpected behaviour, a system of illegal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, combined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid opcode forming an unauthorized combination does not generate a reset. 123/172 ST72260Gx, ST72262Gx, ST72264Gx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description Function/Example Dst Src I1 H I0 N Z C ADC Add with Carry A=A+M+C A M H N Z C ADD Addition A=A+M A M H N Z C AND Logical And A=A.M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M CALL Call subroutine CALLR Call subroutine relative CLR Clear CP Arithmetic Compare tst(Reg - M) reg CPL One Complement A = FFH-A reg, M DEC Decrement dec Y reg, M HALT Halt IRET Interrupt routine return Pop CC, A, X, PC INC Increment inc X JP Absolute Jump jp [TBL.w] JRA Jump relative always JRT Jump relative JRF Never jump JRIH Jump if ext. INT pin = 1 JRIL Jump if ext. INT pin = 0 (ext. INT pin low) JRH Jump if H = 1 H=1? d o r P e et t e l o s b O s ( t c u d o r P e M jrf * (ext. INT pin high) Jump if H = 0 H=0? JRM Jump if I1:0 = 11 I1:0 = 11 ? JRNM Jump if I1:0 11 I1:0 11 ? JRMI Jump if N = 1 (minus) N=1? JRPL Jump if N = 0 (plus) N=0? JREQ Jump if Z = 1 (equal) Z=1? JRNE Jump if Z = 0 (not equal) Z=0? JRC Jump if C = 1 C=1? JRNC Jump if C = 0 C=0? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned > l o s Ob reg, M JRNH 124/172 uc reg, M )- ) s t( C 1 I1 C 0 1 N Z C N Z 1 N Z N Z N Z 0 H I0 C ST72260Gx, ST72262Gx, ST72264Gx INSTRUCTION SET OVERVIEW (Cont’d) Mnemo Description Dst Src JRULE Jump if (C + Z = 1) Unsigned