L4993

L4993 Low drop voltage regulator Features Max DC supply voltage Max output voltage tolerance Max dropout voltage Output current Quiescent current 1. Typical value with watchdog disabled. ■ ■ ■ ■ ■ ■ ■ ■ VS ∆V0 Vdp I0 Iqn 40V +/-2% 400 mV 150 mA 79 µA(1) SO-8 SO-20 Operating DC supply voltage range 5.6V to 31V Reset circuit sensing the output voltage down to 1V Programmable reset pulse delay with external capacitor Watchdog Programmable watchdog timer with external capacitor Enable input for enabling/disabling the watchdog functionality Thermal shutdown and short circuit protection Wide temperature range (Tj = -40°C to 150°C) Description The L4993 is a monolithic integrated 5V Voltage regulator with a low drop voltage at currents up to 150mA.The output voltage regulating element consists in a p-channel MOS and the regulation is performed regardless of input voltage transients up to 40V. The high precision of the output voltage is obtained with a pre-trimmed reference voltage. The L4993 is protected against short circuit and an over-temperature protection switches off the device in case of extremely high power dissipation. The L4993 watchdog is active when the Enable is high. State of the art features like reset and watchdog make this device particularly suitable to supply microprocessor systems in automotive applications. Table 1. Device summary Order codes Package Tube SO-8 SO-20 (16+2+2) L4993D L4993MD Tape & reel L4993DTR L4993MDTR April 2008 Rev 6 1/30 www.st.com 30 Contents L4993 Contents 1 2 Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.1 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 3.2 3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 4.2 SO-8 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SO-20 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1 5.2 5.3 5.4 5.5 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-8 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO-20 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/30 L4993 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Watchdog Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SO-8 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SO-20 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO-20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3/30 List of figures L4993 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output voltage vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output voltage vs. Vs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Drop Voltage vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current consumption vs. Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current consumption vs. Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current limitation vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current limitation vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Short Circuit Current vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Short Circuit Current vs. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VWEn_high vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VWEN_LOW vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Vrhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Vrlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Vwhth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Vwlth vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Icr & Icwc vs. Tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Idr & Icwd vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Twop vs. Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 L4993 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Behavior of output current versus regulated voltage Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SO-8 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 18 SO-8 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Thermal fitting model of Vreg in SO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SO-20 PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 21 SO-20 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . . . . . . . 22 Thermal fitting model of Vreg in SO-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO-20 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO-8 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO-8 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SO-20 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SO-20 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4/30 L4993 Block diagram and pins description 1 Block diagram and pins description Figure 1. Block diagram 5V, 150 mA IS IO VS ICW Iwi VWi VCW Thermal protection + Watchdog Voltage reference IRes VO IWEn VWEn Icr Vcr Reset VRes Gnd 5/30 Block diagram and pins description Table 2. Pin name WEn Gnd Gnd L4993 Pins description SO-8 (D) SO-20 (MD) Function Watchdog Enable input If high watchdog functionality is active Ground reference Ground Connected these pins to a heat spreader ground Reset output. It is pulled down when output voltage goes below Vo_th or frequency at Wi is too low. Leave floating if not used. Reset timing adjust. A capacitor between Vcr pin and gnd, sets the reset delay time (trd) Watchdog timer adjust A capacitor between Vcw pin and gnd, sets the time response of the watchdog monitor. Watchdog input. If the frequency at this input pin is too low, the Reset output is activated. Connect to ground if not used Voltage regulator output Block to ground with a capacitor >100nF (needed for regulator stability) Supply voltage Block to ground directly at IC pin with a capacitor Not connected 1 2 1 4 5, 6, 15, 16 Res 3 7 Vcr 4 10 Vcw 5 11 Wi 6 14 Vos 7 17 Vs N.C. 8 20 2, 3, 8, 9, 12, 13, 18, 19 Figure 2. Pins configuration WEn N.C. N.C. GND GND GND Res N.C. N.C. Vcr 1 2 3 4 5 6 7 8 9 10 20 Vs N.C. N.C. Vos GND GND Wi N.C. N.C. Vcw WEn GND Res Vcr 1 2 3 4 8 SO-8 7 6 5 Vs Vos Wi Vcw SO-20 19 18 17 16 15 14 13 12 11 6/30 L4993 Electrical specifications 2 2.1 Electrical specifications Absolute maximum ratings Stressing the device above the rating listed in the “Absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Symbol VVsdc IVsdc VVo IVo VWi Vod Iod Vcr Vcw VWEn Tj VESD VESD DC supply voltage Input current DC output voltage DC output current Watchdog input voltage Open drain output voltage Open drain output current Reset delay voltage Watchdog delay voltage Watchdog Enable input voltage Junction temperature ESD voltage level (HBM-MIL STD 883C) ESD voltage level (CDM AEC-Q100-011) Absolute maximum ratings Parameter Value -0.3 to 40 Internally limited -0.3 to 6 Internally limited -0.3 to VVo + 0.3 -0.3 to VVo + 0.3 Internally limited -0.3 to VVo + 0.3 -0.3 to VVo + 0.3 -0.3 to VVo +0.3 -40 to 150 ±2 750 V V V °C kV V V V V Unit V Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause permanent damage to the integrated circuit. 2.2 Thermal data For details, please refer to Section 4.1: SO-8 thermal data and Section 4.2: SO-20 thermal data. Table 4. Symbol Thermal data(1) Parameter Thermal resistance Junction to Ambient: SO-8 SO-20 Value Unit Rth-jamb 130 51 °C/W °C/W 1. The values quoted are for PCB FR4 area= 58mm x 58mm, PCB thickness = 2mm, Cu thickness = 35µm , Copper areas: SO-8= 2 cm2, SO-20= 6 cm2. 7/30 Electrical specifications L4993 2.3 Electrical characteristics Values specified in this section are for Vs =5.6V to 31V, Tj= -40°C to +150°C unless otherwise stated. Table 5. Pin Vo Vo Vo Vs, Vo Vo Vs, Vo Vs, Vo Vs, Vo General Symbol Vo_ref Ishort Ilim(2) Vline Vload Vdp(3) SVR Iqn_150 Parameter Output voltage Short circuit current Output current limitation Line regulation voltage Load regulation voltage Drop voltage Ripple rejection Quiescent current Test condition Vs = 6 to 31V Io = 1 to 150mA Vs = 13.5V(1) Vs = 13.5V (1) Min. 4.9 150 150 Typ. 5.0 280 320 Max. Unit 5.1 400 500 25 25 V mA mA mV mV mV dB Vs = 6 to 31V Io = 1 to 150mA Io = 1 to 150mA Io = 150mA fr = 100 Hz (4) Vs=13.5V, Io=150mA, WEn = high Vs=13.5V, Io= 50mA, WEn = high Vs=13.5V, Io< 1mA, WEn = high Vs=13.5V, Io< 1mA, WEn = low 150 10 55 1.25 200 400 2 mA Vs, Vo Iqn_50 Quiescent current 470 1000 µA Vs, Vo Iqn_1 Quiescent current 100 180 µA Vs, Vo Iqs Quiescent current with watchdog regulator disabled Thermal protection temperature Thermal protection temperature hysteresis 79 125 µA Tw Tw_hy 1. See Figure 25. 190 °C °C 2. Measured output current when the output voltage has dropped 100mV from its nominal value obtained at Vs=13.5V and Io= 75mA. 3. Vs-Vo measured when the output voltage has dropped 100mV from its nominal value obtained at Vs=13.5V and Io= 75mA. 4. Guaranteed by design. 8/30 L4993 Table 6. Pin Res Res Res Res Vcr Vcr Vcr Vcr Res Res Electrical specifications Reset Symbol Vres_l IRes_h R_p_u Vo_th Vrlth Vrhth Icr Idr Trr_2 Trd Parameter Reset output low voltage Test condition Rext = 5kΩ to Vo, Vo > 1V Min. Typ. Max. 0.4 1 12 6% 10% 44% 8 8 100 65 25 8% 13% 47% 17.6 17.6 275 50 10% 16% 50% 30 30 1000 150 Unit V µA kΩ Below Vo_ref Vo_ref Vo_ref µA µA µs ms Reset output high leakage VRes = 5V current Pull up internal resistance Vo out of regulation threshold Reset delay circuit low threshold Reset delay circuit high threshold Charge current Discharge current Reset reaction time(1) Reset delay time With respect to Vo Vs = 6 to 31V, Io = 1 to 150mA Vs = 13.5V Vs =13.5V Vs = 13.5V Vs = 13.5V Vo = Vo_th -100mV Vs = 13.5V, Ctr = 1nF 1. When Vo becomes lower than 4V, the reset reaction time decreases down to 2µs assuring a faster reset condition in this particular case. Table 7. Pin Wi Wi Wi Wi Vcw Vcw Vcw Watchdog Symbol Vih Vil Vih_hyst Ii Vwhth Vwlth Icwc Parameter Input high voltage Input low voltage Input hysteresis Pull down current High threshold Low threshold Charge current Test condition Vs = 13.5V Vs = 13.5V Vs = 13.5V Vs = 13.5V Vs = 13.5V Vs = 13.5V Vs = 13.5V, Vcw = 0.1V 44% 10% 4 500 10 47% 13% 8 20 50% 16% 14 Min. 3.5 1.5 Typ. Max. Unit V V mV µA Vo_ref Vo_ref µA 9/30 Electrical specifications Table 7. Pin Vcw Vcw Res L4993 Watchdog (continued) Symbol Icwd Twop twol Parameter Discharge current Watchdog period Watchdog output low time Test condition Vs = 13.5V, Vcw = 2.5V Vs = 13.5V, Ctw = 47nF Vs = 13.5V, Ctw = 47nF Min. 1.0 25 6 Typ. Max. 2.13 50 10.5 4.5 90 22 Unit µA ms ms Table 8. Pin WEn WEn WEn WEn Watchdog Enable Symbol WEn_low WEn_high WEn_hyst Ileak Parameter Enable input low voltage Enable input high voltage Enable input hysteresis Pull down current WEn = 5V 3 500 2 800 8 1100 20 Test condition Min. Typ. Max. 1 Unit V V mV µA 10/30 L4993 Electrical specifications 2.4 Figure 3. Vo_ref (V) 5,5 5,4 5,3 5,2 5,1 5 4,9 4,8 4,7 4,6 4,5 -50 Electrical characteristics curves Output voltage vs. Tj Figure 4. Output voltage vs. Vs Vo_ref (V) 10 Vs= 13.5V I0 = 75mA 9 8 7 6 5 4 3 2 1 0 I0 = 75 mA Tj = 25 °C -25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 Tj(°C ) Vs (V ) Figure 5. Drop Voltage vs. Output Current Figure 6. Current consumption vs. Output Current Vdp (V) 0,3 Iqn (µA) 1500 0,25 1200 0,2 Tj= 125 °C 900 Vs= 13.5 V Tj= 25 °C En= High 0,15 600 0,1 Tj= 25 °C 0,05 300 0 -50 0 50 100 150 200 0 -50 0 50 100 150 200 Io (mA) Io (mA) Figure 7. Current consumption vs. Input Voltage Figure 8. Current limitation vs. Tj Iqn(µA ) 1200 1100 1000 900 800 700 600 500 400 300 200 Tj = 25 °C En = High Ilim (mA) 600 500 Io= 100mA 400 Vs= 13.5V 300 Io =50mA 200 100 Io = 1mA 100 0 0 5 10 15 20 25 30 35 0 -50 -25 0 25 50 75 100 125 150 Vs (V ) Tj(°C ) 11/30 Electrical specifications L4993 Figure 9. Ilim (mA) 350 Current limitation vs. Input Voltage Figure 10. Short Circuit Current vs. Tj Ishort (mA) 600 325 Tj = 25 °C 500 300 400 Vs= 13.5V 275 300 Tj = 125 °C 250 200 225 100 200 0 5 10 15 20 25 30 35 0 -50 -25 0 25 50 75 100 125 150 Vs (V ) Tj(°C ) Figure 11. Short Circuit Current vs. Input Voltage Ishort (mA ) 350 Figure 12. VWEn_high vs. Tj Vwen_high (V) 4 3,5 300 Tj = 25 °C Vs= 5.6V to 31V 3 250 2,5 Tj = 150 °C 2 200 1,5 150 0 5 10 15 20 25 30 35 1 -50 -25 0 25 50 75 100 125 150 Vs (V ) Tj(°C ) Figure 13. VWEN_LOW vs. Tj Vwen_low (V) 2 Figure 14. Vrhth vs. Tj Vrhth (% Vo_ref ) 60 1,9 55 1,8 Vs= 5.6V to 31V 50 Vs= 5.6V to 31V 1,7 45 1,6 40 1,5 35 1,4 -50 -25 0 25 50 75 100 125 150 30 -50 -25 0 25 50 75 100 125 150 Tj(°C ) Tj(°C ) 12/30 L4993 Electrical specifications Figure 15. Vrlth vs. Tj Vrlth (% Vo_ref) 50 Figure 16. Vwhth vs. Tj Vwhth (% Vo_ref ) 60 40 Vs= 5.6V to 31V 55 50 30 45 20 40 10 Vs= 5.6V to 31V 35 0 -50 -25 0 25 50 75 100 125 150 30 -50 -25 0 25 50 75 100 125 150 Tj(°C ) Tj(°C ) Figure 17. Vwlth vs. Tj Vwlth (% Vo_ref) 50 Figure 18. Icr & Icwc vs. Tj Icr & Icwc (µA) 30 Vs= 5.6V to 31V 40 Vs= 5.6V to 31V 25 20 30 15 20 10 10 Icr Icwc 5 0 -50 -25 0 25 50 75 100 125 150 0 -50 -25 0 25 50 75 100 125 150 Tj(°C ) Tj(°C ) Figure 19. Idr & Icwd vs. Tj Idr & Icwd (µA) 30 Figure 20. Twop vs. Tj Twop (ms) 80 25 Vs= 5.6V to 31V 70 20 60 Vs= 5.6V to 31V Ctw= 47nF Idr 15 50 10 40 5 30 Icwd 0 -50 -25 0 25 50 75 100 125 150 20 -50 -25 0 25 50 75 100 125 150 Tj(°C ) Tj(°C ) 13/30 Electrical specifications L4993 Figure 21. PSRR C0 = 4.7µF PSRR [dB] 80 70 60 50 40 30 20 10 0 10000 0,1 1 10 100 1000 FREQUENCY [KHz] 2.5 2.5.1 Test circuit and waveforms plot Load regulation Figure 22. Load regulation test circuit 10 Figure 23. Maximum load variation response V0 [1V / div] I0 [50mA / div] 0,00E+00 5,00E-05 1,00E-04 1,50E-04 2,00E-04 2,50E-04 3,00E-04 3,50E-04 4,00E-04 Time [s] 14/30 L4993 Application information 3 Application information Figure 24. L4993 application schematic Vi Vs Vo Cs Thermal protection C01 C02 + Vcw Ctw Wi Watchdog Voltage reference WEn Res Vcr Ctr Gnd Reset Note: The input capacitor Cs > 200nF is necessary for the smoothing of line disturbances. The output capacitor C01 > 100nF is necessary for the stability of the regulation loop. In order to damp output voltage oscillations during high load current surges, it is recommended put an additional electrolytic capacitor C02 > 10µF at the output pin. 3.1 Voltage regulator Voltage regulator uses a p-channel transistor as a regulating element. With this structure, very low dropout voltage at current up to 500mA is obtained. The output voltage is regulated up to transient input supply voltage of 40V. No functional interruption due to over-voltage pulses is generated. A short circuit protection to GND is provided. The voltage regulator watchdog functionality can be disabled by putting WEn low. Figure 25. Behavior of output current versus regulated voltage Vo Vo Vo_ref Ishort Ilim Iout 15/30 Application information L4993 3.2 Reset The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with the in-ternal reference voltage and a resistor output divider. If the output voltage becomes lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is guaranteed for an output voltage Vo greater than 1V. When the output voltage becomes higher than Vo_th then Res goes high with a delay trd. This delay is obtained by an internal oscillator. The oscillator period is given by: Tosc = [(Vrhth-Vrlth) x Ctr] / Icr + [(Vrhth-Vrlth) x Ctr] / Idr where: Icr: Idr: Vrhth, Vrlth: Ctr: trd is given by: trd = 512 x Tosc Reset is active when En is high. Figure 26. Reset timing diagram Wi Vo Vcr Vout_th trr Tosc Vrhth Vrlth is an internally generated charge current is an internally generated discharge current are two voltages defined with the output voltage and a resistor output divider is an external capacitance. < trr trd = 512 Tosc Res 16/30 L4993 Application information 3.3 Watchdog A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing, the Reset output pin is set to low. The pulse sequence time can be set within a wide range with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is generated. To prevent this the microcontroller must generate a positive edge during the discharge of the capacitor before the voltage has reached the threshold Vwlth. In order to calculate the minimum time t, during which the micro-controller must output the positive edge, the following equation can be used: (Vwhth-Vwlth) x Ctw = Icwd x t Every Wi positive edge switches the current source from discharging to charging. The same happens when the lower threshold is reached. When the voltage reaches the upper threshold, Vwhth, the current switches from charging to discharging. The result is a saw-tooth voltage at the watchdog timer capacitor Ctw. Figure 27. Watchdog timing diagram Wi twop Vcw Vwhth Vwlth Vwlth twol Res 17/30 Package and PCB thermal data L4993 4 4.1 Package and PCB thermal data SO-8 thermal data Figure 28. SO-8 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness = 2mm, Cu thickness = 35µm , Copper areas: from minimum pad lay-out to 2cm2). Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition 170 160 RTHj_amb(°C/W) 150 140 130 120 110 0 0,5 1 1,5 PCB Cu heatsink area (cm^2) 2 2,5 18/30 L4993 Package and PCB thermal data Figure 30. SO-8 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 Footprint 100 2 cm2 10 1 0,0001 0,001 0,01 0,1 1 Time (s) 10 100 1000 Equation 1: pulse calculation formula Z TH δ =R TH ⋅ δ+Z THtp ( 1 – δ) where δ = tP/T Figure 31. Thermal fitting model of Vreg in SO-8 19/30 Package and PCB thermal data Table 9. SO-8 thermal parameter Area/island (cm2) R1 (°C/W) R2 (°C/W) R3 (°C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) Footprint 4.21 2.11 2 41 40 58 0.00029 0.0024 0.03 0.04 0.1 1.05 2 40 2 L4993 20/30 L4993 Package and PCB thermal data 4.2 SO-20 thermal data Figure 32. SO-20 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm,PCB thickness = 2mm, Cu thickness=35µm , Copper areas: from minimum pad lay-out to 6cm2). Figure 33. Rthj-amb Vs. PCB copper area in open box free air condition 70 68 66 RTHj_amb(°C/W) 64 62 60 58 56 54 52 50 0 1 2 3 4 5 PCB Cu heatsink area (cm^2) 6 7 21/30 Package and PCB thermal data Figure 34. SO-20 thermal impedance junction ambient single pulse L4993 ZTH (°C/W) 100 Footprint 6 cm2 10 1 0,0001 0,001 0,01 0,1 1 Time (s) 10 100 1000 Equation 2: pulse calculation formula Z =R ⋅ δ+Z ( 1 – δ) TH δ TH THtp where δ = tP/T Figure 35. Thermal fitting model of Vreg in SO-20 22/30 L4993 Table 10. SO-20 thermal parameter Area/island (cm2) R1 (°C/W) R2 (°C/W) R3 (°C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) Package and PCB thermal data Footprint 4.21 2.11 2.2 10 15 35 0.00029 0.0024 0.015 0.15 1.5 4 2 18 7 23/30 Package and packing information L4993 5 5.1 Package and packing information ECOPACK® packages In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.2 SO-8 package information Figure 36. SO-8 package dimensions 24/30 L4993 Table 11. SO-8 mechanical data Package and packing information Millimeters Symbol Min. A A1 A2 b c D(1) E E1(2) e h L L1 k ccc 0° 0.25 0.40 1.04 8° 0.10 0.10 1.25 0.28 0.17 4.80 5.80 3.80 4.90 6.00 3.90 1.27 0.50 1.27 0.48 0.23 5.00 6.20 4.00 Typ. Max. 1.75 0.25 1. Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm in total (both side). 2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 25/30 Package and packing information L4993 5.3 SO-20 package information Figure 37. SO-20 package dimensions Table 12. SO-20 mechanical data Millimeters Symbol Min. A A1 B C D(1) E e H h L k ddd 10.0 0.25 0.40 0° 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 8° 0.10 Typ. Max. 2.65 0.30 0.51 0.32 13.00 7.60 1. “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. 26/30 L4993 Package and packing information 5.4 SO-8 packing information Figure 38. SO-8 tube shipment (no suffix) B C A Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) All dimensions are in mm. 100 2000 532 3.2 6 0.6 Figure 39. SO-8 tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (+ 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 All dimensions are in mm. End Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components 27/30 Package and packing information L4993 5.5 SO-20 packing information Figure 40. SO-20 tube shipment (no suffix) Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) 40 800 532 3.5 13.8 0.6 C B A Figure 41. SO-20 tape and reel shipment (suffix “TR”) Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) D G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 60 30.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (+ 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 24 4 12 1.5 1.5 11.5 6.5 2 All dimensions are in mm. End Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components 28/30 L4993 Revision history 6 Revision history Table 13. Date June-2004 18-Jan-2007 01-Jun-2007 22-Aug-2007 29-Aug-2007 Document revision history Revision 1 2 3 4 5 Initial release. Updated Table 5., 6, 7 and 8. Document put in corporate technical literature template. Updated Table 4. Table 5: General: updated Ishort, Ilim, Iq, Trr2, Vih_hist parameters. Added list of tables and figures. Added Section 4: Package and PCB thermal data. Document restructured. Changed Figure 1: Block diagram. Updated Table 5: General: – changed Ishort max value from 4000 mA to 400 mA – changed Iqn_150 typ. value from 1.45 mA to 1.25 mA – changed Iqn_50 typ. value from 538 µA to 470 µA – changed Iqn_1 typ. value from 120 µA to 100 µA. Updated Table 6: Reset: – corrected trd formula. Updated Table 7: Watchdog: – changed Vwlth values in Vo_ref percentages – changed Vwhth values in Vo_ref percentages. Added Figure 24: L4993 application schematic. Added Section 2.4: Electrical characteristics curves. Added Section 2.5: Test circuit and waveforms plot. Changes 08-Apr-2008 6 29/30 L4993 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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