L4995
Automotive 5V, 500mA low drop voltage regulator
Datasheet - production data
Wide temperature range (Tj = -40 °C to 150 °C)
Enable input for enabling/disabling the voltage
regulator
PowerSSO-12
PowerSSO-24
Description
L4995 is a family of monolithic integrated 5 V
voltage regulators with a low drop voltage at
currents of up to 500 mA, available in both 12 and
24 pin packages.
Features
Max DC supply voltage
VS
40V
Max output voltage tolerance
Vo
+/-2%
Max dropout voltage
Vdp
500mV
Output current
Io
500mA
Quiescent current
Iqn
3µA(1)
1. Typical value with regulator disabled
AEC-Q100 qualified
Operating DC supply voltage
range 5.6 V to 31 V
Low dropout voltage
Low quiescent current consumption
Reset circuit sensing of output voltage down to
1V
Programmable reset pulse delay with external
capacitor
Programmable watchdog timer with external
capacitor
The output voltage regulating element consists of
a p-channel MOS and regulation is performed
regardless of input voltage transients of up to 40V.
The high precision of the output voltage is
obtained using a pre-trimmed reference voltage.
The L4995 family is protected against short circuit
and overtemperature protection switches off the
devices in the case of extremely high power
dissipation. The L4995 integrates the watchdog,
enable and externally programmable reset
circuits. The L4995A features the externally
programmable reset and enable. Finally the
L4995R features the externally programmable
reset.
The combination of such features makes this
device particularly flexible and suitable to supply
microprocessor systems in automotive
applications.
Thermal shutdown and short circuit protection
Table 1. Device summary
Order codes
Package
Tube
Tape and reel
PowerSSO-12 (exposed pad)
L4995J - L4995AJ - L4995RJ
L4995JTR - L4995AJTR - L4995RJTR
PowerSSO-24 (exposed pad)
L4995K - L4995AK - L4995RK
L4995KTR - L4995AKTR - L4995RKTR
P/N
Watchdog
Reset
Enable
L4995J - L4995K
X
X
X
L4995AJ - L4995AK
-
X
X
L4995RJ - L4995RK
-
X
-
September 2018
This is information on a product in full production.
DS5053 Rev 15
1/37
www.st.com
Contents
L4995
Contents
1
Block diagrams and pins descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5
Test circuit and waveforms plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5.1
3
4
5
6
2/37
Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1
ECOPACK®
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2
PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3
PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.4
PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DS5053 Rev 15
L4995
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pins descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PowerSSO-12 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-24 thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-24 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
DS5053 Rev 15
3/37
3
List of figures
L4995
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
4/37
Block diagram of L4995 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram of L4995A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram of L4995R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pins configurations (L4995) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output voltage vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output voltage vs VS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Drop voltage vs output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current consumption vs output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current consumption vs input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current limitation vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current limitation vs input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Short circuit current vs input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output voltage vs enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VEn_high vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VEN_LOW vsTj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VRhth vsTj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VRlth vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Vwhth vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Vwlth vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Icr and Icwc vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Idr and Icwd vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Twop vs Tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PSRR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Load regulation test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Maximum load variation response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
L4995 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Stability region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Behavior of output current versus regulated voltage Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Reset timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 22
PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 23
Thermal fitting model of Vreg in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . . 25
PowerSSO-24 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 26
Thermal fitting model of Vreg in PowerSSO-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
PowerSS0-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DS5053 Rev 15
Block diagrams and pins descriptions
1
L4995
Block diagrams and pins descriptions
Figure 1. Block diagram of L4995
9R
9V
,V
,R
9RV
9
6WDUWXS
6
,
9
(Q
9ROWDJH
5HIHUHQFH
(Q
9(Q
,FZ
9R
P9
B
9FZ
9FZ
5HV
:L
ZDWFKGRJ
9ZL
9FU
9FU
/RZ9ROWDJH
5HVHW
*1'
9
5HV
("1(.4
Figure 2. Block diagram of L4995A
,V
9R
9V
,R
9RV
9
6WDUWXS
6
,
9
(Q
9ROWDJH
5HIHUHQFH
(Q
9(Q
9R
P9
B
5HV
9FU
9FU
*1'
9
/RZ9ROWDJH
5HVHW
*$3*06
6/37
DS5053 Rev 15
5HV
L4995
Block diagrams and pins descriptions
Figure 3. Block diagram of L4995R
,V
9R
9V
,R
9RV
9
6WDUWXS
6
9
9ROWDJH
5HIHUHQFH
9(Q
9R
P9
B
5HV
9FU
9FU
*1'
/RZ9ROWDJH
5HVHW
9
5HV
*$3*06
Table 2. Pins descriptions
Pin
name
PowerSSO-12 PowerSSO-24
pin #
Function
pin #
Enable input (L4995 and L4996A only, otherwise not
connected).
If high regulator, watchdog and reset are operating. If
low regulator, watchdog and reset are shutdown.
Connect to Vs if not used.
En
1
13, 14, 15
NC
2, 4, 8
3, 5, 6, 9, 11
GND
3
16, 17, 18
Ground reference.
-
TAB
TAB, 1, 12
Substrate of the chip: connect the pins or the TAB to
GND.
Res
5
19, 20, 21
Reset output.
It is pulled down when output voltage goes below Vo_th
or frequency at Wi is too low. Leave floating if not used.
Vcr
6
22, 23, 24
Reset timing adjust.
A capacitor between Vcr pin and GND. Sets the reset
delay time (trd). Leave floating if Reset is not used.
2
Watchdog timer adjust (L4995 only, otherwise not
connected).
A capacitor between Vcw pin and GND. Sets the time
response of the watchdog monitor.
Vcw
7
Not connected.
DS5053 Rev 15
7/37
36
Block diagrams and pins descriptions
L4995
Table 2. Pins descriptions (continued)
Pin
PowerSSO-12 PowerSSO-24
Function
name
pin #
pin #
Wi
9
4
Watchdog input (L4995 only, otherwise not connected).
If the frequency at this input pin is too low, the Reset
output is activated.
Vos
10
7
Regulator voltage output sensing.
Vo
11
8
5 voltage regulator output.
Block to ground with a capacitor >100nF (needed for
regulator stability).
VS
12
10
Supply voltage.
Block to ground directly at VS pin with a ceramic
capacitor (e.g. 200nF).
Figure 4. Pins configurations (L4995)
VXEVWUDWH
7$% VXEVWUDWH
VXEVWUDWH
7$% VXEVWUDWH
*$3*06
8/37
DS5053 Rev 15
L4995
Electrical specifications
2
Electrical specifications
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 3. Absolute maximum ratings
Symbol
Parameter
Value
Unit
- 0.3 to 40
V
VVsdc
DC supply voltage
IVsdc
Input current
VVo(1)
DC output voltage
- 0.3 to 6
IVo
DC output current
Internally limited
VWi
Watchdog input voltage
-0.3 to VVo + 0.3
V
Vod
Res output voltage
-0.3 to VVo + 0.3
V
Iod
Res output current
Internally limited
Vcr
Vcr voltage
- 0.3 to VVo + 0.3
V
Vcw
Watchdog delay voltage
- 0.3 to VVo + 0.3
V
VEn
Enable input
- 0.3 to VVsdc +0.3
V
- 40 to 150
C
Tj
Internally limited
Junction temperature
V
VESD
ESD voltage level (HBM-MIL STD 883C)
±2
kV
VESD
ESD voltage level (CDM AEC-Q100-011)
750
V
1. Using the typical application schematic with Cout= 10 µF and Iout=0 A, when the regulator is switched-on,
an overshoot exceeding 6 V could occur.This behavior does not impact the reliability of the regulator.
DS5053 Rev 15
9/37
36
Electrical specifications
2.2
L4995
Thermal data
For details, please refer to Section 4.1: PowerSSO-12 thermal data and Section 4.2:
PowerSSO-24 thermal data.
Table 4. Thermal data(1)
mm
Symbol
Parameter
Value
Unit
Rthj-case
Thermal resistance Junction to Case:
PowerSSO-12
PowerSSO-24
5
4
°K/W
°K/W
Rthj-amb
Thermal resistance Junction to Ambient:
PowerSSO-12
PowerSSO-24
52
38
°K/W
°K/W
1. The values quoted are for PCB 77mm x 86mm x 1.6mm, FR4, double layer; Copper thickness 0.070mm
Copper area 3cm2 Thermal Vias, Thermal vias separation 1.2 mm, Thermal via diameter 0.3 mm +/- 0.08
mm, Cu thickness on vias 0.025 mm.
2.3
Electrical characteristics
Values specified in this section are for Vs = 5.6V to 31V, Tj = -40 °C to +150 °C unless
otherwise stated.
Table 5. General
10/37
Pin
Symbol
Parameter
Test condition
Vo
Vo_ref
Output voltage
VS = 5.6 to 31V
Io = 0 to 500mA
4.9
5.00
5.1
V
Vo
Ishort
Short circuit current
VS = 13.5V (1)
550
800
1050
mA
Vo
Ilim(2)
Output current limitation
VS = 13.5V (1)
600
900
1250
mA
VS, Vo
Vline
Line regulation voltage
VS = 5.6 to 31V
Io = 0 to 500mA
25
mV
Vo
Vload
Load regulation voltage
Io = 0 to 500mA
25
mV
VS, Vo
Vdp(3)
Drop voltage
Io = 400mA
500
mV
VS, Vo
SVR
Ripple rejection
fr = 100 Hz (4)
VS, Vo
Iqs
Current consumption with
regulator disabled
VS = 13.5V,
En = low
3
10
µA
VS, Vo
Iqn_1
Current consumption
with regulator enabled
VS = 13.5V,
Io < 1mA,
90
160
µA
VS, Vo
Iqn_50
Current consumption
with regulator enabled
VS = 13.5V,
Io = 50mA,
290
400
µA
DS5053 Rev 15
Min.
Typ. Max.
270
55
Unit
dB
L4995
Electrical specifications
Table 5. General (continued)
Pin
Symbol
VS, Vo
Iqn_150
Current consumption
with regulator enabled
VS = 13.5V,
Io = 150mA,
740
1000
µA
VS, Vo
Iqn_250
Current consumption
with regulator enabled
VS= 13.5V,
Io= 250mA,
1
1.4
mA
VS, Vo
Iqn_500
Current consumption
with regulator enabled
VS= 13.5V,
Io= 500mA,
2.1
2.7
mA
190
°C
Tw
Tw_hy
Parameter
Test condition
Thermal protection
temperature
Min.
Typ. Max.
150
Thermal protection
temperature hysteresis
10
Unit
°C
1. See Figure 28.
2. Measured output current when the output voltage has dropped 100mV from its nominal value obtained at
Vs=13.5V and Io= 250mA.
3. Vs-Vo measured when the output voltage has dropped 100mV from its nominal value obtained at Vs=13.5V
and Io= 250mA.
4. Guaranteed by design.
Table 6. Reset
Pin
Symbol
Parameter
Res
Vres_l
Res
IRes_lkg
Res
RRes
Pull up internal resistance
(versus Vo)
Res
Vo_th
Vo out of regulation
threshold
Vcr
VRlth
Vcr
VRhth
Vcr
Reset output low voltage
Test condition
Min.
Typ. Max.
Rext = 5k to Vo,
Vo > 1V
Reset output high leakage
VRes = 5V
current
Unit
0.4
V
1
µA
10
20
40
k
VS = 5.6 to 31V
Io = 1 to 500mA
6%
8%
10%
below
Vo_ref
Reset delay circuit low
threshold
VS = 13.5V
10%
13%
16%
Vo_ref
Reset delay circuit high
threshold
VS =13.5V
44%
47%
50%
Vo_ref
Icr
Charge current
VS = 13.5V
8
15
30
µA
Vcr
Idr
Discharge current
VS = 13.5V
8
15
30
µA
Res
Trr
Reset reaction time(1)
Vo = Vo_th -100mV
100
250
700
µs
Res
Trd
Reset delay time
VS = 13.5V,
Ctr = 47nF
12
33
73
ms
1. When Vo becomes lower than 4V, the reset reaction time decreases down to 2µs assuring a faster reset
condition in this particular case.
DS5053 Rev 15
11/37
36
Electrical specifications
L4995
Table 7. Watchdog
Pin
Symbol
Parameter
Test condition
Min.
Typ. Max.
Wi
Vih
Input high voltage
VS = 13.5V
Wi
Vil
Input low voltage
VS = 13.5V
Wi
Vih
Input hysteresis
VS = 13.5V
500
Wi
Iwi
Pull down current
VS = 13.5V
Vwi = 3.5V
6
10
µA
Vcw
Vwlth
Low threshold
VS = 13.5V
10%
13%
16%
Vo_ref
Vcw
Vwhth
High threshold
VS = 13.5V
44%
47%
50%
Vo_ref
Vcw
Icwc
Charge current
VS = 13.5V,
Vcw = 0.1V
5
10
20
µA
Vcw
Icwd
Discharge current
VS = 13.5V,
Vcw = 2.5V
1.25
2.5
5
µA
Vcw
Twop
Watchdog period
VS = 13.5V,
Ctw = 47nF
20
40
80
ms
Res
twol
Watchdog output low time
VS = 13.5V,
Ctw = 47nF
4
8
16
ms
3.5
Unit
V
1.5
V
mV
Table 8. Enable
12/37
Pin
Symbol
Parameter
En
VEn_low
En input low voltage
En
VEn_high
En input high voltage
En
VEn_hyst
En input hysteresis
En
IEn
Pull down current
Test condition
Min.
Typ. Max.
1
3
DS5053 Rev 15
V
V
830
VS = 13.5V
Unit
10
mV
18
µA
L4995
Electrical specifications
2.4
Electrical characteristics curves
Figure 5. Output voltage vs Tj
Figure 6. Output voltage vs VS
Figure 7. Drop voltage vs output current
Figure 8. Current consumption vs
output current
Figure 9. Current consumption vs input voltage
Figure 10. Current limitation vs Tj
DS5053 Rev 15
13/37
36
Electrical specifications
L4995
Figure 11. Current limitation vs input voltage
Figure 12. Short circuit current vs input voltage
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Figure 13. Output voltage vs enable voltage
Figure 14. VEn_high vs Tj
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Figure 15. VEN_LOW vsTj
Figure 16. VRhth vsTj
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9V 9WR9
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14/37
7M &
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DS5053 Rev 15
L4995
Electrical specifications
Figure 17. VRlth vs Tj
Figure 18. Vwhth vs Tj
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Figure 19. Vwlth vs Tj
Figure 20. Icr and Icwc vs Tj
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Figure 21. Idr and Icwd vs Tj
Figure 22. Twop vs Tj
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DS5053 Rev 15
*$3*06
15/37
36
Electrical specifications
L4995
Figure 23. PSRR
C0= 4.7 µF
PSRR [dB]
80,00
70,00
60,00
50,00
40,00
30,00
20,00
10,00
0,00
0,10
1,00
10,00
100,00
1000,00
FREQUENCY [KHz]
10000
00,00
GAPGMS00073
2.5
Test circuit and waveforms plot
2.5.1
Load regulation
Figure 24. Load regulation test circuit
*$3*06
16/37
DS5053 Rev 15
L4995
Electrical specifications
Figure 25. Maximum load variation response
V0
I0
0,00E+00
[ 1 V / div]
[ 2 0 0 mA / div ]
5,00E-05
1,00E-04
1,50E-04
2,00E-04
Time [s]
DS5053 Rev 15
2,50E-04
3,00E-04
3,50E-04
4,00E-04
GAPGMS00081
17/37
36
Application information
3
L4995
Application information
Figure 26. L4995 application schematic
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The input capacitor Cs > 200nF is necessary for the smoothing of line disturbances. The
output capacitor Co1> 100nF is necessary for the stability of the regulation loop. In order to
dampen output voltage oscillations during high load current surges, it is recommended an
additional electrolytic capacitor Co2 > 10µF to be placed at the output pin.
Figure 27. Stability region
100
Unstable region
ESR (Ohm)
10
1
Stability region
ESR min
ESR max
0.1
0.01
Undefined region
0.001
0.5
5
10
15
20
25
30
Co (uF)
18/37
DS5053 Rev 15
35
40
45
50
L4995
Application information
Note:
The curve which describes the minimum ESR is derived from characterization data on the
regulator with connected ceramic capacitors which feature low ESR values (at 100 kHz).
Any capacitor with further lower ESR than the given plot value must be evaluated in each
and every case.
3.1
Voltage regulator
Voltage regulator uses a p-channel transistor as a regulating element. With this structure,
very low dropout voltage at current up to 500mA is obtained. The output voltage is regulated
up to transient input supply voltage of 40V. No functional interruption due to over-voltage
pulses is generated. A short circuit protection to GND is provided.
The voltage regulator is active when En is high.
Figure 28. Behavior of output current versus regulated voltage Vo
Vo
Vo_ref
Ishort Ilim
3.2
Iout
Reset
The reset circuit supervises the output voltage Vo. The Vo_th reset threshold is defined with
the in-ternal reference voltage and a resistor output divider. If the output voltage becomes
lower than Vo_th then Res goes low with a reaction time trr. The reset low signal is
guaranteed for an output voltage Vo greater than 1V.
When the output voltage becomes higher than Vo_th then Res goes high with a delay trd.
This delay is obtained by an internal oscillator.
The oscillator period is given by:
Equation 1
Tosc = [(VRhth-VRlth) x Ctr] / Icr + [(VRhth-VRlth) x Ctr] / Idr
DS5053 Rev 15
19/37
36
Application information
L4995
where:
Icr:is an internally generated charge current
Idr:is an internally generated discharge current
VRhth, VRlth:are two voltages defined with the output voltage and a resistor output
divider
Ctr:is an external capacitance.
trd is given by:
Equation 2
trd = (VRhth x Ctr)/Icr + 3 x Tosc
Reset is active when En is high.
Figure 29. Reset timing diagram
Wi
Vo
Vout_th
< trr
Vcr
Tosc
Vrhth
trr
Vrlth
trd
Res
GAPGMS00077
3.3
Watchdog
A connected microcontroller is monitored by the watchdog input Wi. If pulses are missing,
the Reset output pin is set to low. The pulse sequence time can be set within a wide range
with the external capacitor, Ctw. The watchdog circuit discharges the capacitor Ctw, with the
constant current Icwd. If the lower threshold Vwlth is reached, a watchdog reset is generated.
To prevent this the microcontroller must generate a positive edge during the discharge of the
capacitor before the voltage has reached the threshold Vwlth. In order to calculate the
minimum time t, during which the micro-controller must output the positive edge, the
following equation can be used:
Equation 3
(Vwhth-Vwlth) x Ctw = Icwd x t
Every Wi positive edge switches the current source from discharging to charging. The same
happens when the lower threshold is reached. When the voltage reaches the upper
threshold, Vwhth, the current switches from charging to discharging. The result is a
saw-tooth voltage at the watchdog timer capacitor Ctw.
20/37
DS5053 Rev 15
L4995
Application information
Figure 30. Watchdog timing diagram
:L
7ZRS
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*$3*06
DS5053 Rev 15
21/37
36
Package and PCB thermal data
L4995
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 31. PowerSSO-12 PC board
("1($'5
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70m (front and back side)
Thermal vias separation 1.2 mm, Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness
on vias 0.025 mm, Footprint dimension 4.1 mm x 6.5 mm).
Figure 32. Rthj-amb vs PCB copper area in open box free air condition
RTHj _a
_amb( ° C/ W)
70
65
60
55
50
45
40
0
2
4
6
eat sink area
ea ( cm^ 2)
PCB Cu hea
22/37
DS5053 Rev 15
8
10
GAPGMS00082
L4995
Package and PCB thermal data
Figure 33. PowerSSO-12 thermal impedance junction ambient single pulse
ZTH ( ° C/ W)
100
Footprint
2 cm2
8 cm2
10
1
0,1
0,0001
0,001
0,01
0,1
1
Time ( s)
10
100
1000
Equation 4: pulse calculation formula
Z
TH
= R
TH
+Z
THtp
1 –
where = tP/T
Figure 34. Thermal fitting model of Vreg in PowerSSO-12
*$3*06
DS5053 Rev 15
23/37
36
Package and PCB thermal data
L4995
Table 9. PowerSSO-12 thermal parameter
2
24/37
Area/island (cm )
Footprint
2
8
R1 (°C/W)
0.45
R2 (°C/W)
1.79
R3 (°C/W)
7
R4 (°C/W)
10
10
9
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1 (W.s/°C)
0.001
C2 (W.s/°C)
0.0022
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
DS5053 Rev 15
L4995
4.2
Package and PCB thermal data
PowerSSO-24 thermal data
Figure 35. PowerSSO-24 PC board
GAPGCFT00418
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70m (front and back side)
Thermal vias separation 1.2 mm, Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness
on vias 0.025 mm, Footprint dimension 4.1 mm x 6.5 mm).
Figure 36. Rthj-amb vs PCB copper area in open box free air condition
57+M BDPE & :
3&%&XKHDWVLQNDUHD FPA
*$3*06
DS5053 Rev 15
25/37
36
Package and PCB thermal data
L4995
Figure 37. PowerSSO-24 thermal impedance junction ambient single pulse
ZTH ( ° C/ W)
100
Footprint
2 cm2
8 cm2
10
1
0,1
0,0001
0,001
0,01
0,1
1
Time ( s)
10
100
1000
Equation 5: pulse calculation formula
Z
TH
= R
TH
+Z
THtp
1 –
where = tP/T
Figure 38. Thermal fitting model of Vreg in PowerSSO-24
*$3*06
26/37
DS5053 Rev 15
L4995
Package and PCB thermal data
Table 10. PowerSSO-24 thermal parameter
Area/island (cm2)
Footprint
R1 (°C/W)
0.45
R2 (°C/W)
1.79
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
2
8
9
9
8
R6 (°C/W)
28
17
10
C1 (W.s/°C)
0.001
C2 (W.s/°C)
0.0022
C3 (W.s/°C)
0.025
C4 (W.s/°C)
0.75
C5 (W.s/°C)
1
4
9
C6 (W.s/°C)
2.2
5
17
DS5053 Rev 15
27/37
36
Package and packing information
L4995
5
Package and packing information
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 39. PowerSSO-12 package dimensions
28/37
DS5053 Rev 15
L4995
Package and packing information
Table 11. PowerSSO-12 mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
A
1.250
1.620
A1
0.000
0.100
A2
1.100
1.650
B
0.230
0.410
C
0.190
0.250
D
4.800
5.000
E
3.800
4.000
e
0.800
H
5.800
6.200
h
0.250
0.500
L
0.400
1.270
k
0º
8º
X
2.200
2.800
Y
2.900
3.500
ddd
0.100
DS5053 Rev 15
29/37
36
Package and packing information
5.2
L4995
PowerSSO-24 mechanical data
Figure 40. PowerSSO-24 package dimensions
("1($'5
30/37
DS5053 Rev 15
L4995
Package and packing information
Table 12. PowerSSO-24 mechanical data(1)(2)
Millimeters
Symbol
Min.
Typ.
A
Max.
2.45
A2
2.15
2.35
a1
0
0.10
b
0.33
0.51
c
0.23
0.32
D(3)
10.10
10.50
E(3)
7.40
7.60
e
0.8
e3
8.8
F
2.3
G
0.1
G1
0.06
H
10.1
10.5
h
0.4
k
0°
8°
L
0.55
0.85
O
1.2
Q
0.8
S
2.9
T
3.65
U
1
N
10º
X
4.1
4.7
Y
6.5
4.9(4)
7.1
5.5(4)
1. No intrusion allowed inwards the leads.
2. Flash or bleeds on exposed die pad shall not exceed 0.4 mm per side
3. “D and E” do not include mold Flash or protusions.
Mold Flash or protusions shall not exceed 0.15 mm.
4. Variations for small window leadframe option.
DS5053 Rev 15
31/37
36
Package and packing information
5.3
L4995
PowerSSO-12 packing information
Figure 41. PowerSSO-12 tube shipment (no suffix)
B
Base q.ty
Bulk q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 42. PowerSSO-12 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base q.ty
Bulk q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape hole spacing
Component spacing
Hole diameter
Hole diameter
Hole position
Compartment depth
Hole spacing
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
All dimensions are in mm.
End
Start
Top
cover
tape
No components
Components
Empty components pockets
saled with cover tape.
User direction of feed
32/37
DS5053 Rev 15
No components
500mm min
500mm min
L4995
5.4
Package and packing information
PowerSSO-24 packing information
Figure 43. PowerSS0-24 tube shipment (no suffix)
C
B
A
GAPGCFT00002
Figure 44. PowerSSO-24 tape and reel shipment (suffix “TR”)
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DS5053 Rev 15
33/37
36
Revision history
6
L4995
Revision history
Table 13. Document revision history
34/37
Date
Revision
Changes
26-May-2006
1
Initial release.
05-Jan-2007
2
L4995A and L4995R versions added:
Features section updated and table added.
Table 1 updated.
Table 5: General, Watchdog Iwi entry updated.
Figure 2: Block diagram of L4995A and Figure 3: Block diagram of
L4995R added.
Table 2: Pins descriptions updated.
Table 4: Thermal data updated.
List of tables and List of figures added.
Packaging information provided in new format.
Table 11: PowerSSO-12 mechanical data X and Y values updated.
Some sections reformatted for clarity.
New disclaimer added.
18-May-2007
3
Updated Table 2: Pins descriptions.
Updated Figure 4: Pins configurations (L4995).
Table 1: Device summary changed title.
09-Jul-2007
4
Updated Table 2: Pins descriptions.
09-Aug-2007
5
Updated Table 2: Pins descriptions.
Updated Table 12: PowerSSO-24 mechanical data.
DS5053 Rev 15
L4995
Revision history
Table 13. Document revision history (continued)
Date
Revision
Changes
6
Updated Section 2.2: Thermal data:
– corrected note changing single layer with double layer.
Updated Table 5: General:
– changed Ishort typ. value from 750 to 800 mA
– added Ishort max. value
– changed Ilim typ. value from 820 to 900 mA
– added Ilim max. value
– added Ilim note
– added Vdp note
– changed Iqn_1 typ. value from 110 to 90 µA
– added Iqn_1 max. value
– added Iqn_50 max. value
– added Iqn_150 max. value
– changed Iqn_250 typ. value from 1.2 to 1 mA
– added Iqn_250 max. value
– changed Iqn_500 typ. value from 2.4 to 2.1 mA
– added Iqn_500 max. value
Updated Table 6: Reset:
– changed VRlth parameter definition from “Reset timing low” to
“Reset delay circuit low threshold”
– changed VRhth parameter definition from “Reset timing high” to
“Reset delay circuit high threshold”
– added Trd min. and max. values
Updated Table 7: Watchdog:
– added Iwi max value
Updated Table 8: Enable:
– changed Pull down current symbol from REn to IEn
– changed IEn typ. value from 2.5 to 10 µA
– added IEn max. value
Added Section 2.4: Electrical characteristics curves.
Added Section 2.5: Test circuit and waveforms plot.
Added Section 4: Package and PCB thermal data
03-Oct-2008
7
Updated PowerSSO-24 information:
– changed Figure 40: PowerSSO-24 package dimensions
– changed Table 12: PowerSSO-24 mechanical data.
19-Mar-2009
8
Updated Table 4: Thermal data
9
Updated Table 2: Pins descriptions.
Updated Figure 4: Pins configurations (L4995)
– Changed GND to substrate
07-Dec-2007
19-May-2009
DS5053 Rev 15
35/37
36
Revision history
L4995
Table 13. Document revision history (continued)
Date
36/37
Revision
Changes
24-Jun-2009
10
Table 12: PowerSSO-24 mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.50 to 2.45
– Changed A2 (max) value from 2.40 to 2.35
– Updated K row
– Changed L (min) value from 0.6 to 0.55
– Changed L (max) value from 1 to 0.85
12-Jul-2010
11
Added Figure 27: Stability region.
09-Mar-2012
12
Added footnote in Table 3: Absolute maximum ratings.
17-Oct-2012
13
Table 6: Reset:
– Trd: updated min, typ and max values
20-Sep-2013
14
Updated disclaimer.
17-Sep-2018
15
Updated title and Features.
Minor text changes.
DS5053 Rev 15
L4995
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS5053 Rev 15
37/37
37
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