L5963D-EHX

L5963 Automotive dual monolithic switching regulator with LDO and HSD Datasheet - production data '!0'03 '!0'03 PowerSSO-36 (exposed pad) PowerSSO-36 (slug-up) *$3*36 VQFPN-48  Independent current limit on all regulators  Extremely low quiescent current in standby conditions  Power good / adjustable voltage detector outputs to realize customized power up/down sequences Featuress Description  AEC-Q100 qualified  Two step-down synchronous switching voltage regulators with internal power switches: – Wide input voltage range (from 3.5 V to 26 V) – Internal high-side/ low-side NDMOS – 1 V minimum output – 3.0 A load current – 250 kHz free-run frequency – 250 kHz < f < 2 MHz synchronization range – Integrated soft-start – Independent hardware enable pins – Independent power supply – 180° PWM output phase shift – Programmable switching frequency divider by 1, 2, 4 or 8 between the two DC/DC regulators – Power good function  One standby / linear regulator – Output voltage programmable with external resistor divider – 250 mA maximum current capability – Backup function – Power good function  One high side driver – 0.5 V max drop @ 0.5 A – Protected against short to ground and battery, loss of ground and battery, unsupplied short to battery  Programmable under voltage battery detector – Under voltage threshold adjustable through dedicated pin (VDIN)  Load dump protection  Independent thermal protection on all regulators L5963 is a dual step-down switching regulator with internal power switches, high side driver and a low drop-out linear regulator that can operate as standby regulator or normal LDO. June 2017 This is information on a product in full production. All the regulators can be connected directly to the vehicle battery. In addition to an adjustable voltage detector, voltage supervisors are available. The two DC-DC converters can work in free-run condition or synchronize themselves to an external clock. DC/DCs' PWM outputs have a 180° phase shift. The high operating frequency allowed by the synchronization input helps to reduce AM and FM interferences and grants the use of small and low cost inductors and capacitors. This IC finds application in the automotive segment, where load dump protection and wide input voltage range are mandatory. A slug-up package option is available for applications which require heatsink use. In standby condition the device guarantees extremely low quiescent current (25 μA typical @ -40 °C < T < 85 °C) Table 1. Device summary Order code Package Packing L5963DN-EHX L5963DN-EHT L5963U-KBX L5963U-KBT L5963Q-V0Y L5963Q-V0T PowerSSO36 (exposed pad) Tube Tape & Reel Tube Tape & Reel Tray Tape & Reel DocID028553 Rev 3 PowerSSO36 (slug-up) VQFPN-48 1/49 www.st.com Contents L5963 Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 7 2/49 5.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 Operative modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 Blocks functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2.1 Unregulated supply input voltage (VINLDO) . . . . . . . . . . . . . . . . . . . . . 19 6.2.2 Low voltage warning monitor (related pins: VDIN, VDOUT, VDDLY) . . . 19 6.2.3 Power-good reset (related pins: LDOOK, LDOOKDLY) . . . . . . . . . . . . . 20 6.2.4 Power-good function of DC/DC1 (related pins: SW1OK, SW1OKDLY) . 20 6.2.5 Over voltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2.6 Power ground (PGND1 and PGND2) . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.7 Signal ground (SGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.8 PWM signal ground (SWGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.9 TAB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.10 Linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.11 High-side driver (HSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2.12 Switching regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 Output inductor (Lo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.2 Output capacitors (COUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.3 Input capacitors (CIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.4 Bootstrap capacitor (CBOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DocID028553 Rev 3 L5963 Contents 7.5 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 Thermal design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 9.1 Package variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.2 PowerSSO-36 (exposed pad) package information . . . . . . . . . . . . . . . . . 40 9.3 PowerSSO-36 (slug-up) package information . . . . . . . . . . . . . . . . . . . . . 43 9.4 VFQFPN-48 (7x7x1.0 - opt. D) package information . . . . . . . . . . . . . . . . 45 9.5 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID028553 Rev 3 3/49 3 List of tables L5963 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. 4/49 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PowerSSO-36 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VQFPN-48 pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal data (PowerSSO-36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Thermal data (VQFPN-48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Components value for different output voltage cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum suggested power for L5963 in PSSO36 slug-down package . . . . . . . . . . . . . . . 37 Maximum suggested power for L5963 in QFN48 package. . . . . . . . . . . . . . . . . . . . . . . . . 37 PowerSSO-36 exposed pad package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PowerSSO-36 slug-up package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 VFQFPN-48 (7x7x1.0 - opt. D) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 46 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID028553 Rev 3 L5963 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Example of a typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Example of usage of two regulators in the same application . . . . . . . . . . . . . . . . . . . . . . . . 9 PowerSSO-36 pinout configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VQFPN-48 pinout configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 PSRR LDO 50 mA load vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Efficiency vs. output current (VIN = 14 V, fsw = 2 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Efficiency vs. output current (VIN = 14 V, fsw = 250 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 18 Low voltage warning monitor & delay schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Linear regulator diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Enable timing for standby regulator (ENLDO pin connect to supply directly) . . . . . . . . . . . 22 Enable timing for linear regulator (pin ENLDO isn't connected to VINLDO) . . . . . . . . . . . . 23 Switching regulators diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Closed loop system with TYPE III network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TYPE III compensated network diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PowerSSO-36 (exposed pad) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 PowerSSO-36 (slug-up) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 VFQFPN-48 (7x7x1.0 - opt. D) package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PowerSSO-36 (exp. pad) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PowerSSO-36 (slug up) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 VFQFPN-48 (7x7x1.0) marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DocID028553 Rev 3 5/49 5 Overview 1 L5963 Overview The L5963 integrates two switching mode synchronous step down converters, a linearly regulated power supply, a protected high side driver and voltage detectors. To guarantee a robust operation, all the outputs have independent thermal protection and current limitation. The two switching mode synchronous step-down converters employ voltage mode control and feed forward functions to provide good load regulation and line regulation. Each converter has its own enable. The users can adjust the output voltage of the two converters by an external resistor divider. If the converters need to work with a frequency different from the free running frequency, in order to consider EMC performance in system level, they can be synchronized to an external clock by applying it on the SYNCIN pin. The frequency should be higher than half of the free running frequency. If there are more than one L5963 in the system they can work in Master-Slave configuration, to make sure all L5963 have the same operating frequency of the Master device. This Master-Slave function is implemented by a dedicated pin SYNCOUT which always gives the operating frequency of DC/DC1. A dedicated voltage detector is integrated in the first switching converter to monitor DC/DC1 output. When the output voltage of DC/DC1 goes above the threshold, SW1OK is released and goes back to high with configurable delay set by a capacitor on the SW1OKDLY pin. The linear regulator can work as standby regulator with low Iq or as a non-standby regulator. Connecting its enable ENLDO to its supply VINLDO the regulator works as a standby regulator, while connecting ENLDO to a voltage lower than 5 V the regulator works as nonstandby regulator, with higher load capability but also higher quiescent current. In standby state, i.e. only the linear regulator is powered and works as a standby regulator, with a load below 100 μA the device has a quiescent current of just 25 μA. The small drop-out voltage of the linear regulator allows its use with low operating supply voltage. In many cases, the linear regulator has to provide voltages to devices which need the reset function, like a MCU: this is provided by the LDOOK output, that is pulled low when VOUTLDO goes below a threshold. Once VOUTLDO returns above that threshold, with a specified hysteresis, LDOOK goes back to high with a configurable delay set by a capacitor on pin LDOOKDLY. The high side driver is enabled by a dedicated pin and has a very low drop-out voltage. Protection circuits, like independent thermal protection, OCP, OVP and some special protections (loss of GND, SPU, short to supply and so on), are implemented to make it very robust. L5963 also embeds a voltage monitor (VDOUT), adjustable by means of an external resistor divider, that can be used to sense the battery or other voltages in the system. Sensing voltage is fed to pin VDIN. For instance, VDOUT might be used to monitor the output of DC/DC2, realizing in this way the Power Good function for that block. VDOUT is pulled low when voltage on VDIN goes below the specified threshold. Once VDIN returns above that threshold, with a specified hysteresis, VDOUT goes back to high with a configurable delay set by a capacitor on pin LDOOKDLY Two different packages are available. The PowerSSO-36 slug-down allows to dissipate the heat on the board and reduce the application size. The slug has to be connected to the ground plane. This is the package suggested for standard applications. When this is not enough, because the L5963 is used as pre-regulator for high consuming applications and both the 2 DC-DC are working at high currents, the PSSO36 slug-up allows the use of a heat-sink to make easier power dissipation. 6/49 DocID028553 Rev 3 L5963 2 Block diagram Block diagram Figure 1. Block diagram 6).37 6).,$/ "3 )NTERNALREGULATOR 07- #,+ 2EF?6 2EF?6 3WITCHING2EGULATOR  "ANDGAP 2EF #/-0 39.#/54 6BG &"37 &",$/ 2EF?6 ,INEARREGULATOR 6/54,$/ ,$//+ 37/+ 2ESET$ELAY 0OWER'OOD $ELAY07-  ,$//+$,9 37/+$,9 6$). 6$/54 6OLTAGESUPERVISORY WITH0/2DELAY 6$$,9 %.37 ,OGIC #ONTROL %.37 6).37 %.,$/ "3 %.(3$ 07- 2EF?6 #,+ 3WITCHING2EGULATOR  &"37 )NTERNALREGULATOR 6"!4 #/-0 /SCILLATOR #,+ 3YNC,OGIC 39.#). 6).(3$ #,/#+ #,+ &REQ,OGIC 6BG (IGH3IDEDRIVER (3$ &2$)6 '.$ 4!" 3'.$ 37'.$ 0'.$ 0'.$ DocID028553 Rev 3 '!0'03 7/49 48 Application diagrams 3 L5963 Application diagrams Figure 2. Example of a typical application diagram 9%DWW  & & Q)9 X)9 5   9,1B/'2 (1B/'2  /'2B9287B2.   & 7$% 8 / 7$% & X)9 ' 9%$7 9%DWW   733 9,1/'2 9287/'2  287B/'2 (1/'2 5 )%/'2 /'22. . & & X9 Q & &  5 /'22.'/< . Q &203  9,1B6:  & & X)9 X)9 &  (1B6: Q)9 6:B9287B2.   &  6,1.B&/.B287 5  S )%6: (16:   (1B6: 3:0 3*1' 6