L6208Q
DMOS driver for bipolar stepper motor
Datasheet - production data
Description
9)4)31
[ PP
Features
Operating supply voltage from 8 to 52 V
5.6 A output peak current
RDS(on) 0.3 typ. value at Tj = 25 °C
The L6208Q device is a DMOS fully integrated
stepper motor driver with non-dissipative
overcurrent protection, realized in BCDmultipower
technology, which combines isolated DMOS
power transistors with CMOS and bipolar circuits
on the same chip. The device includes all the
circuitry needed to drive a two-phase bipolar
stepper motor including: a dual DMOS full bridge,
the constant OFF time PWM current controller
that performs the chopping regulation, and the
phase sequence generator that generates the
stepping sequence. Available in a VFQFPN48
7 x 7 mm package, the L6208Q features a nondissipative overcurrent protection on the high-side
Power MOSFETs and thermal shutdown.
Operating frequency up to 100 kHz
Non-dissipative overcurrent protection
Dual independent constant tOFF PWM current
controllers
Fast/slow decay synchronous rectification
Fast decay quasi-synchronous rectification
Decoding logic for stepper motor full and half
step drive
Cross conduction protection
Thermal shutdown
Undervoltage lockout
Integrated fast freewheeling diodes
Application
Bipolar stepper motor
March 2017
This is information on a product in full production.
DocID018710 Rev 4
1/34
www.st.com
Contents
L6208Q
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3
PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4
Decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5
Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.6
Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.7
Normal drive mode (full step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 19
5.8
Wave drive mode (full step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . 19
5.9
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 20
5.10
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Output current capability and IC power dissipation . . . . . . . . . . . . . . 26
8
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10.1
2/34
VFQFPN48 (7 x 7 x 1.0 mm) package information . . . . . . . . . . . . . . . . . 30
DocID018710 Rev 4
L6208Q
Contents
11
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DocID018710 Rev 4
3/34
34
Block diagram
1
L6208Q
Block diagram
Figure 1. Block diagram
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L6208Q
Electrical data
2
Electrical data
2.1
Absolute maximum ratings
Table 1. Absolute maximum ratings
Symbol
VS
Test condition
Value
Unit
Supply voltage
VSA = VSB = VS
60
V
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS = 60 V;
VSENSEA = VSENSEB =
GND
60
V
VBOOT
Bootstrap peak voltage
VSA = VSB = VS
VS + 10
V
VIN,VEN
Input and enable voltage range
-
-0.3 to +7
V
VREFA,
VREFB
Voltage range at pins VREFA and VREFB -
-0.3 to +7
V
VRCA,
VRCB
Voltage range at pins RCA and RCB
-
-0.3 to +7
V
VSENSEA,
VSENSEB
Voltage range at pins SENSEA and
SENSEB
-
-1 to +4
V
IS(peak)
Pulsed supply current (for each VS
pin), internally limited by the
overcurrent protection
VSA = VSB = VS;
tPULSE < 1 ms
7.1
A
RMS supply current (for each VS pin)
VSA = VSB = VS
2.5
A
Storage and operating temperature
range
-
-40 to 150
°C
VOD
IS
Tstg, TOP
2.2
Parameter
Recommended operating conditions
Table 2. Recommended operating conditions
Symbol
Parameter
Test condition
Min.
Max. Unit
Supply voltage
VSA = VSB = VS
8
52
V
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
-
52
V
-0.1
5
V
Pulsed tW < trr
-6
6
V
DC
-1
1
V
RMS output current
-
-
2.5
A
Tj
Operating junction temperature
-
-25
+125
°C
fsw
Switching frequency
-
-a
100
kHz
VS
VOD
VREFA,
VREFB
Voltage range at pins VREFA and VREFB -
VSENSEA, Voltage range at pins SENSEA and
VSENSEB SENSEB
IOUT
DocID018710 Rev 4
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34
Pin connection
3
L6208Q
Pin connection
CLOCK
VREFA
RESET
41
OUT2A
CW/CCW
42
NC
SENSEA
43
VCP
SENSEA
44
OUT2A
NC
45
40
39
38
37
36
NC
35
VSA
3
34
VSA
NC
4
33
NC
NC
5
32
NC
GND
6
31
GND
NC
7
30
NC
NC
8
29
NC
NC
9
28
NC
OUT1B
10
27
VSB
OUT1B
11
26
VSB
NC
12
25
NC
13
14
15
16
17
18
19
20
21
22
23
24
VREFB
HALF/FULL
CONTROL
EN
VBOOT
OUT2B
OUT2B
NC
EPAD
SENSEB
OUT1A
46
NC
2
47
SENSEB
1
48
RCB
NC
OUT1A
RCA
Figure 2.Pin connection (top view)
AM02556v1
Note:
The exposed PAD must be connected to GND pin.
Table 3. Pin description
6/34
Pin
Name
Type
Function
43
CLOCK
Logic input
Step clock input. The state machine makes one step on each
rising edge.
Selects the direction of the rotation. HIGH logic level sets
clockwise direction, whereas low logic level sets
counterclockwise direction. If not used, it must be connected to
GND or +5 V.
44
CW/CCW
Logic input
45, 46
SENSEA
Power supply
48
RCA
RC pin
2, 3
OUT1A
6, 31
GND
10, 11
OUT1B
13
RCB
Bridge A source pin. This pin must be connected to power
ground through a sensing power resistor.
RC network pin. A parallel RC network connected between this
pin and ground sets the current controller OFF time of bridge A.
Power output Bridge A output 1.
GND
Ground terminals. In PowerDIP24 and SO24 packages, these
pins are also used for heat dissipation towards the PCB. On
PowerSO36 package the slug is connected to these pins.
Power output Bridge B output 1.
RC pin
RC network pin. A parallel RC network connected between this
pin and ground sets the current controller OFF time of bridge B.
DocID018710 Rev 4
L6208Q
Pin connection
Table 3. Pin description (continued)
Pin
Name
Type
Function
15, 16
SENSEB
Power supply
Bridge B source pin. This pin must be connected to power
ground through a sensing power resistor.
17
VREFB
Analog input
Bridge B current controller reference voltage. Do not leave this
pin open or connected to GND.
18
HALF/
FULL
Logic input
Step mode selector. High logic level sets half step mode, low
logic level sets full step mode. If not used, it must be connected
to GND or +5 V.
19
CONTROL
Logic input
Decay mode selector. High logic level sets slow decay mode.
Low logic level sets fast decay mode. If not used, it must be
connected to GND or +5 V.
Chip enable. Low logic level switches off all power MOSFETs
of both bridge A and bridge B. This pin is also connected to the
collector of the overcurrent and thermal protection to
(1)
Logic input
implement overcurrent protection. If not used, it must be
connected to +5 V through
a resistor.
20
EN
21
VBOOT
22, 23
OUT2B
34, 35
VSA
Power supply
Bridge A power supply voltage. It must be connected to the
supply voltage together with pin VSB.
26, 27
VSB
Power supply
Bridge B power supply voltage. It must be connected to the
supply voltage together with pin VSA.
38, 39
OUT2A
40
VCP
Output
41
RESET
Logic input
Reset pin. Low logic level restores the home state (state 1) on
the phase sequence generator state machine. If not used, it
must be connected to +5 V.
42
VREFA
Analog input
Bridge A current controller reference voltage. Do not leave this
pin open or connected to GND.
Supply
voltage
Bootstrap voltage needed for driving the upper power
MOSFETs of both bridge A and bridge B.
Power output Bridge B output 2.
Power output Bridge A output 2.
Charge pump oscillator output.
1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it must
be driven putting in series a resistor with a value in the range of 2.2 k - 180 k, recommended 100 k.
DocID018710 Rev 4
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34
Electrical characteristics
4
L6208Q
Electrical characteristics
VS = 48 V, TA = 25 °C, unless otherwise specified.
Table 4. Electrical characteristics
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VSth(ON)
Turn-on threshold
-
6.6
7
7.4
V
VSth(OFF)
Turn-off threshold
-
5.6
6
6.4
V
Quiescent supply current
All bridges OFF; Tj = -25 °C to
125 °C(1)
-
5
10
mA
Thermal shutdown temperature
-
-
165
-
°C
Tj = 25 °C
-
0.34
0.4
Tj = 125 °C(1)
-
0.53
0.59
Tj = 25 °C
-
0.28
0.34
Tj = 125 °C(1)
-
0.47
0.53
EN = low; OUT = VS
-
-
2
mA
EN = low; OUT = GND
-0.15
-
-
mA
Forward ON voltage
ISD = 2.5 A, EN = low
-
1.15
1.3
V
trr
Reverse recovery time
If = 2.5 A
-
300
-
ns
tfr
Forward recovery time
-
-
200
-
ns
IS
Tj(OFF)
Output DMOS transistors
High-side switch ON resistance
RDS(ON)
Low-side switch ON resistance
IDSS
Leakage current
Source drain diodes
VSD
Logic input (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
VIL
Low level logic input voltage
-
-0.3
-
0.8
V
VIH
High level logic input voltage
-
2
-
7
V
IIL
Low level logic input current
GND logic input voltage
-10
-
IIH
High level logic input current
7 V logic input voltage
-
-
10
µA
Vth(ON)
Turn-on input threshold
-
-
1.8
2.0
V
Vth(OFF)
Turn-off input threshold
-
0.8
1.3
-
V
Vth(HYS)
Input threshold hysteresis
-
0.25
0.5
-
V
ILOAD = 2.5 A, resistive load
100
250
400
ns
ILOAD = 2.5 A, resistive load
300
550
800
ns
ILOAD = 2.5 A, resistive load
40
-
250
ns
ILOAD = 2.5 A, resistive load
40
-
250
ns
ILOAD = 2.5 A, resistive load
-
2
-
µs
µA
Switching characteristics
tD(on)EN
tD(off)EN
tRISE
tFALL
tDCLK
8/34
Enable to out turn ON delay time(2)
Enable to out turn OFF delay
Output rise time(2)
Output fall
time(2)
Clock to output delay
time(3)
time(2)
DocID018710 Rev 4
L6208Q
Electrical characteristics
Table 4. Electrical characteristics (continued)
Symbol
Parameter
Min.
Typ.
Max.
Unit
-
-
-
1
µs
Minimum clock time(4)
-
-
-
1
µs
Clock frequency
-
-
-
100
kHz
-
-
-
1
µs
-
-
-
1
µs
-
-
-
1
µs
-
-
-
1
µs
0.5
1
-
µs
-
0.6
1
MHz
0.5
1
-
µs
tCLK(min)L
Minimum clock time
(4)
tCLK(min) H
fCLK
tS(MIN)
Test condition
(5)
Minimum setup time
(5)
tH(MIN)
Minimum hold time
tR(MIN)
Minimum reset time(5)
(5)
tRCLK(MIN ) Minimum reset to clock delay time
tDT
Deadtime protection
°C(7)
fCP
Charge pump frequency
Tj = -25 °C to 125
tDT
Deadtime protection
-
fCP
Charge pump frequency
-25 °C < Tj < 125 °C
-
0.6
1
MHz
Source current at pins RCA and
RCB
VRCA = VRCB = 2.5 V
3.5
5.5
-
mA
Voffset
Offset voltage on sense comparator
VREFA, VREFB = 0.5 V
-
±5
-
mV
tPROP
Turn OFF propagation delay(6)
-
-
500
-
ns
tBLANK
Internal blanking time on SENSE
pins
-
-
1
-
µs
tON(MIN)
Minimum ON time
-
-
1.5
2
µs
ROFF = 20 k; COFF = 1 nF
-
13
-
µs
ROFF = 100 k; COFF = 1 nF
-
61
-
µs
-
-
10
µA
PWM comparator and monostable
IRCA, IRCB
tOFF
PWM recirculation time
IBIAS
Input bias current at pins VREFA and
VREFB
Overcurrent detection
Isover
ROPDR
tOCD(ON)
tOCD(OFF)
Input supply overcurrent detection
threshold
-25 °C < Tj < 125 °C
4
5.6
7.1
A
Open drain ON resistance
I = 4 mA
-
40
60
OCD turn-on delay time
(7)
I = 4 mA; CEN < 100 pF
-
200
-
ns
OCD turn-off delay time
(7)
I = 4 mA; CEN < 100 pF
-
100
-
ns
1. Tested at 25 °C in a restricted range and guaranteed by characterization.
2. See Figure 3.
3. See Figure 4.
4. See Figure 5.
5. See Figure 6.
6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
7. See Figure 7.
DocID018710 Rev 4
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34
Electrical characteristics
L6208Q
Figure 3. Switching characteristic definition
EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tFALL
tD(OFF)EN
tRISE
tD(ON)EN
AM02557v1
Figure 4. Clock to output delay time
CLOCK
Vth(ON)
t
IOUT
t
D01IN1317
tDCLK
Figure 5. Minimum timing definition; clock input
CLOCK
Vth(OFF)
Vth(ON)
tCLK(MIN)L
10/34
DocID018710 Rev 4
Vth(OFF)
tCLK(MIN)H
D01IN1318
L6208Q
Electrical characteristics
Figure 6. Minimum timing definition; logic inputs
CLOCK
Vth(ON)
LOGIC INPUTS
tS(MIN)
RESET
Vth(OFF)
tH(MIN)
Vth(ON)
tR(MIN)
tRCLK(MIN)
D01IN1319
Figure 7. Overcurrent detection timing definition
IOUT
ISOVER
ON
BRIDGE
OFF
VEN
90%
10%
tOCD(ON)
tOCD(OFF)
AM02558v1
DocID018710 Rev 4
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Circuit description
L6208Q
5
Circuit description
5.1
Power stages and charge pump
The L6208Q device integrates two independent power MOSFET full bridges, each power
MOSFET has an RDS(ON) = 0.3 (typical value at 25 °C) with intrinsic fast freewheeling
diode. Cross conduction protection is implemented by using a deadtime (tDT = 1 µs typical
value) set by internal timing circuit between the turn-off and turn-on of two power MOSFETs
in one leg of a bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using an N-channel power MOSFET for the upper transistors in the bridge requires a gate
drive voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and a few external components to realize a charge pump
circuit, as shown in Figure 8. The oscillator output (pin VCP) is a square wave at 600 kHz
(typically) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table 5.
Table 5. Charge pump external component values
Component
Value
CBOOT
220 nF
CP
10 nF
RP
100
D1
1N4148
D2
1N4148
Figure 8. Charge pump circuit
VS
D1
CBOOT
D2
RP
CP
VCP
VBOOT
VSA VSB
AM02559v1
12/34
DocID018710 Rev 4
L6208Q
5.2
Circuit description
Logic inputs
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and µC
compatible logic inputs. The internal structure is shown in Figure 9. Typical values for turnon and turn-off thresholds are respectively Vth(ON) = 1.8 V and Vth(OFF) = 1.3 V.
Pin EN (Enable) has identical input structure with the exception that the drain of the
overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection, some care must be taken in driving this pin. The EN input may be driven in one
of two configurations, as shown in Figure 10 or 11. If driven by an open drain (collector)
structure, a pull-up resistor REN and a capacitor CEN are connected, as shown in Figure 10.
If the driver is a standard push-pull structure, the resistor REN and the capacitor CEN are
connected, as shown in Figure 11. The resistor REN should be chosen in the range from 2.2
k to 180 k. Recommended values for REN and CEN are respectively 100 k and 5.6 nF.
More information on selecting the values is found in Section 5.9.
Figure 9. Logic inputs internal structure
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13/34
34
Circuit description
5.3
L6208Q
PWM current control
The L6208Q device includes a constant OFF time PWM current controller for each of the
two bridges. The current control circuit senses the bridge current by sensing the voltage
drop across an external sense resistor connected between the source of the two lower
power MOSFET transistors and ground, as shown in Figure 12. As the current in the load
builds up, the voltage across the sense resistor increases proportionally. When the voltage
drop across the sense resistor becomes greater than the voltage at the reference input
(VREFA or VREFB), the sense comparator triggers the monostable switching the low-side
MOSFET off. The low-side MOSFET remains off for the time set by the monostable and the
motor current recirculates in the upper path. When the monostable times out, the bridge
again turns on. As the internal deadtime, used to prevent cross conduction in the bridge,
delays the turn-on of the power MOSFET, the effective OFF time is the sum of the
monostable time plus the deadtime.
Figure 12. PWM current controller simplified schematic
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Figure 13 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the RC pin voltage and the status of the bridge. More details
regarding the Synchronous Rectification and the output stage configuration are included in
Section 5.4.
Immediately after the low-side Power MOSFET turns on, a high peak current flows through
the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6208Q
device provides a 1 s blanking time tBLANK that inhibits the comparator output so that this
current spike cannot prematurely re-trigger the monostable.
14/34
DocID018710 Rev 4
L6208Q
Circuit description
Figure 13. Output current regulation waveforms
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Thermal management
8
L6208Q
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it must
be considered very carefully. Besides the available space on the PCB, the right package
should be chosen considering the power dissipation. Heat sinking can be achieved using
copper on the PCB with proper area and thickness.
Table 7. Thermal data
Symbol
RthJA
Parameter
Thermal resistance junction-ambient
Package
Typ.
Unit
VFQFPN48(1)
17
°C/W
1. VFQFPN48 mounted on the EVAL6208Q rev 1 board (see EVAL6208Q databrief): four-layer FR4 PCB with
a dissipating copper surface of about 45 cm2 on each layer and 25 via holes below the IC.
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Electrical characteristic curves
9
Electrical characteristic curves
Figure 30. Typical quiescent current vs. supply
voltage
Figure 31. Typical high-side RDS(on) vs. supply
voltage
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7M &
7M &
7M &
7M &
9 6>9@
96>9@
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Figure 32. Normalized typical quiescent current
vs. switching frequency
,T ,TDWN+]
Figure 33. Normalized RDS(on) vs.junction
temperature (typical value)
5 '6 21 5' 6 21 D W &
7M>&@
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Figure 34. Typical low-side RDS(on) vs. supply
voltage
Figure 35. Typical drain-source diode forward
ON characteristic
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7M &
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Package information
10
L6208Q
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
10.1
VFQFPN48 (7 x 7 x 1.0 mm) package information
Figure 36. VFQFPN48 (7 x 7 x 1.0 mm) package outline
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Package information
Table 8. VFQFPN48 (7 x 7 x 1.0 mm) package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
-
0.02
0.05
A2
-
0.65
1.00
A3
-
0.25
-
b
0.18
0.23
0.30
D
6.85
7.00
7.15
D2
4.95
5.10
5.25
E
6.85
7.00
7.15
E2
4.95
5.10
5.25
e
0.45
0.50
0.55
L
0.30
0.40
0.50
ddd
-
0.08
-
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Order codes
11
L6208Q
Order codes
Table 9. Ordering information
Order codes
L6208Q
L6208QTR
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Package
VFQFPN48 7 x 7 x 1.0 mm
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Packaging
Tray
Tape and reel
L6208Q
12
Revision history
Revision history
Table 10. Document revision history
Date
Revision
Changes
29-Jul-2011
1
First release
28-Nov-2011
2
Document moved from preliminary to final datasheet
12-Jun-2013
3
Unified package name to “VFQFPN48” in the whole document.
Figure 1 moved to page 3, added Section 1: Block diagram.
Corrected headings in Table 1 and Table 2 (replaced “Parameter” by
“Test condition”).
Corrected unit in Table 6 (row C1).
Added titles to Equation 1 to Equation 4 and cross-references in
Section 5.3: PWM current control.
Added Table 7: Thermal data in Section 8: Thermal management.
Updated Section 10: Package information (modified titles, reversed
order of Figure 36 and Table 8).
Unified “CEN”, “tDT”, “tON”,“tOFF”, “COFF”, “ROFF”, “Vth(ON)”,
“Vth(OFF)”(subscript, lower/upper case) in the whole document.
Minor corrections throughout document.
13-Mar-2017
4
Updated Figure 1 on page 4 (replaced by new figure).
Minor modifications throughout document.
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L6208Q
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
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