L6213

L6213 SOLENOID DRIVER + SWITCH MODE POWER SUPPLY ADVANCE DATA OPERATING SUPPLY VOLTAGE UP TO 46V 1A POWER SUPPLY (5V) 5A SOLENOID DRIVER PRECISE ON CHIP REFERENCE VOLTAGE DISCONTINUOUS MODE - FREQUENCY VARIABLE VERY HIGH EFFICIENCY 1Ω OUTPUT DMOS (SMPS) INTERNAL CURRENT LIMIT (SMPS SECTION) EXTERNALLY PROGRAMMABLE SOLENOID CURRENT RISING SLOPE EXTERNALLY PROGRAMMABLE FIXED HYSTERESIS CONTROL OPTIMIZED DMOS RDS ON FOR HIGH SIDE CHOPPING DESCRIPTION The L6213 is an IC containing a S.M.P.S. delivering 1A at a voltage of 5V and a section designed to drive a solenoid with a current up to 5A. The device is realized in BCD mixed technology, which combines isolated DMOS power transistor with CMOS and Bipolar circuits on the same chip. The SMPS section can deliver 1A DC with an outAPPLICATION CIRCUIT MULTIPOWER BCD TECHNOLOGY Powerdip 16+2+2 put voltage of 5V, including current limiting, reset and power fail for microprocessor and thermal protection. The solenoid driver section is designed for high current applications like hammer driver in electronic typewriter. The solenoid output section contains a high side and a low side DMOS, which RDS ON are optimized for high side chopping. The current rising slope is externally programmable through an external capacitor. The level of hysteresis of the current can be changed through an external resistor. The device is supplied in Powerdip 16+2+2, and use the four center pins to conduct heat to the printed circuit. November 1991 1/9 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L6213 BLOCK DIAGRAM 2/9 L6213 ABSOLUTE MAXIMUM RATINGS Symbol VS VD VOUT-DOWN VOUT-UP PFP VO, Enable PIM Reset, PF CD, ISTP Out-Up Out-Down Tstg Supply Voltage Output Negative Voltage peak at t = 0.1µs f = 100KHz Output Positive Voltage DC Output Positive Voltage peak at t = 0.1µs f = 25KHz Output Negative Voltage peak at t = 0.1µs f = 25KHz Input Voltage Input Voltage Output Voltage Input Voltage Output Current DC = 10% TON = 3.5ms Storage Temperature Parameter Value 52 -1.3 -5V VS + 1.3 VS + 5 -5 25 7 20 5.5 5.5 -50 to 150 Unit V V V V V V V V V V A °C VD; VOUT-UP Output Negative Voltage DC THERMAL DATA Symbol R th j-pins R th j-amb Description Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Max. Max. Value 14 60 Unit °C/W °C/W PIN CONNECTION (Top view) 3/9 L6213 PIN DESCRIPTION Nr. 1 2 3 4 5, 6 7 Name Out-Up BSE ENABLE +VS1 GND PF Solenoid section upper DMOS output. Solenoid section upper DMOS bootstrap. A capacitor connected between pin 2 and pin 1 ensures the efficient driving of the solenoid section upper DMOS. Solenoid control input - TTL compatible. Unregulated voltage input - Solenoid section. Ground. Power fail output, the saturation of PF is guaranteed if VPS exceed 3V. PF is at logic 1 a time T1 after RESET reached the high level. PF came back to logic 0 when VPS goes down under 18V. (see fig. 1) Power fail programming. A resistor divider connected to VPS changes the Power fail threshold levels. Capacitor delay. A capacitor connected to this pin determines the Reset signal delay time td. Unregulated voltage input - SMPS sections. Regulator output and diode voltage control. SMPS section DMOS bootstrap. A capacitor connected between pin 12 and pin 11 ensures efficient driving of SMPS DMOS. Reset output. The saturation of Reset is guaranteed if VPS exceeds 3V. The Reset output reaches the logic level 1 a time delay (set by capacitor CD) after VPS has reached a rising threshold voltage. Reset reaches 0 level when VPS goes down below folling threshold. Feed back input of the regulation loop. Ground. Connection for solenoid sensing resistor. Programming of solenoid current rising edge. An RC network connected to this pin determines the slope of the solenoid current rising edge. Programming of solenoid current histeresys. Solenoid section lower DMOS output. Description 8 9 10 11 12 13 PFP CD VS2 VD BSA RESET 14 15, 16 17 18 19 20 Vout GND R sense PIM ISTP Out-Down ELECTRICAL CHARACTERISTICS (Refer to the application circuit, TJ =25°C, Iout Power Supply = 50mA, VPS from 12V to 46V; unless otherwise specified. Pin Symbol Parameter Test Condition Min. Typ. Max. Unit STEP-DOWN SECTION 10, 4 14 10 10 10 11 2, 10 2, 10 11 Vi Vo R DS on th on th off IB Ilim Ii Ii tdp toff Supply Voltage Output Voltage On State Drain Resistance Turn-on Threshold Turn-off Threshold Input Bias Current Static Current Limiting Total Input Current Total Input Current Protection Current Maximum Delay Time Minimum Power off State VPS = 46V IO = 50mA 4.2 ENABLE = 1, VPS = 46V, Iload = 0 ENABLE = 1, VPS = 15V, Iload = 0 2.2 IO = 0.05 to 1A TJ = 25°C; VPS = 15 to 46V VPS Rising Fig. 1 VPS Falling Fig. 1 10 10 14 4.85 0.56 46 5.2 0.7 12 12 15 3.4 13 18 1 7.8 V V Ω V V mA A mA mA µs µs 4/9 L6213 ELECTRICAL CHARACTERISTICS (continued) Pin Symbol Parameter Test Condition Min. Typ. Max. Unit POWER FAIL 10 10 10 8 8 8 8 7 7 7 7 VthR VthF ∆Vth IPFI Vth-PFP Vth-PFP ∆Vth -PFP Vsat Ileak t1 t2 Rising Threshold Voltage Falling Threshold Voltage Threshold Hysteresis Divided Internal Current Rising Threshold Voltage Falling Threshold Voltage Threshold Hysteresis Output PF Saturation Output Leakage Current Delay to Reset Noise Immunity VPS = 24V VPS = 24V VPS = 24V PF current = 2.5mA VPS = 3 to 46V VPS = 46V VPF = 20V RESET High to PF high Delay Time (fig. 1) When VPS drops to 8V for a time from 0 to t2, PF must be at 1 logic level (fig. 2) When VPS drops to 17V for a time greater than t3, PF must be at 0 logic level (fig. 2) 0 0 1.1 0.98 30 0.4 50 1 1 1.21 1.06 PFP open PFP open PFP open Fig. 1 Fig. 1 Fig. 1 19.5 16.6 0.5 130 1.29 1.13 20 18.1 23 19.5 V V V µA V V mV V µA µs µs µs 7 t3 Noise Immunity 4 RESET 9 9 13 13 13 Id Id Vsat Ileak t4 Delay Source Current Delay Sink Current Output RESET Saturation Output Leakage Current Noise Immunity VD = 0 to 4.1V VD = 4.3 to 2V RESET Current = 2.5mA VPS = 3 to 46V VPS = 46V RD = 4 to 5V VRESET = 20V When VPS drops to 10V for a time greater than t4 RESET must be at 0 logic level (fig. 1) 4 70 10 0.4 50 140 µA mA V µA µs SOLENOID CONTROL SECTION 18 18 18 17 17 17 Vsense Vsat Ileak Vclamp Saturation Voltage Leakage Current Clamp Voltage Minimum Offset Threshold MAximum Offset Voltage Static Voltage Limiting Threshold PIM = GND Vsens = 10mV ENABLE = 0 PIM = GND Vse ns = 50mV ENABLE = 0 Vsens going from 0 to 0.6V PIM = 3V, the EMH DMOS goes to high resistance state when Vsens is within: (see Block Diagram) ENABLE = 1 I PIM = 5mA PIM = 0.2 to 2.5V ENABLE = 0 1.9 2 0.2 +100 2.1 V µA V lower MOS must be in conduction lower MOS must be open 0.475 0.5 0.525 V 17 tp EMH Ron EML Ron 17 Vsense Maximum Delay Time Protection Time OnStateDrain toSource Resistance OnStateDrain to SourceResistance Vsense Hysteresis Tj = 25°C, VPS 15 to 46V Tj = 25°C, VPS 15 to 46V IST = Open IST = 0.75V IST = 3V 35 15 80 2 0.35 0.28 50 25 100 1 4 0.45 0.4 65 35 120 µs µs Ω Ω mV mV mV 5/9 L6213 Figure 1: Power Fail and Reset Static Operation. (PFP open) 6/9 L6213 Figure 2: Power Fail and Reset Noise Immunity and Dynamic Operation. 7/9 L6213 POWERDIP20 PACKAGE MECHANICAL DATA DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.30 1.27 8.80 2.54 22.86 7.10 5.10 0.130 0.050 0.38 0.51 0.85 0.50 0.50 24.80 0.346 0.100 0.900 0.280 0.201 0.015 1.40 mm TYP. MAX. MIN. 0.020 0.033 0.020 0.020 0.976 0.055 inch TYP. MAX. 8/9 L6213 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 9/9