L6228N

L6228 DMOS driver for bipolar stepper motor Datasheet - production data  Decoding logic for stepper motor full and half step drive  Cross conduction protection  Thermal shutdown  Undervoltage lockout  Integrated fast freewheeling diodes Application 3RZHU62 Bipolar stepper motor Description The L6228 device is a DMOS fully integrated stepper motor driver with non-dissipative overcurrent protection, realized in BCD technology, which combines isolated DMOS power transistors with CMOS and bipolar circuits on the same chip. The device includes all the circuitry needed to drive a two phase bipolar stepper motor including: a dual DMOS full bridge, the constant off time PWM current controller that performs the chopping regulation and the phase sequence generator, that generates the stepping sequence. Available in PowerSO36 and SO24 (20 + 2 + 2) packages, the L6228 device features a non-dissipative overcurrent protection on the high-side power MOSFETs and thermal shutdown. 62  2UGHULQJQXPEHUV /13RZHU',3 /3'3RZHU62 /'62 Features  Operating supply voltage from 8 to 52 V  2.8 A output peak current (1.4 A RMS)  RDS(ON) 0.73  typ. value at Tj = 25 °C  Operating frequency up to 100 KHz  Non-dissipative overcurrent protection  Dual independent constant tOFF PWM current controllers  Fast/slow decay mode selection  Fast decay quasi-synchronous rectification October 2018 This is information on a product in full production. DocID9454 Rev 3 1/34 www.st.com Contents L6228 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 9 10 2/34 7.1 Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.2 Half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.3 Normal drive mode (full step two phase on) . . . . . . . . . . . . . . . . . . . . . . . 20 7.4 Wave drive mode (full step one phase on) . . . . . . . . . . . . . . . . . . . . . . . . 20 7.5 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.6 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1 Output current capability and IC power dissipation . . . . . . . . . . . . . . . . . 26 8.2 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.1 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.2 SO24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 DocID9454 Rev 3 L6228 Block diagram 1 Block diagram Figure 1. Block diagram 9%227 9%227 9%227 9&3 2&'$ 2&'% 29(5 &855(17 '(7(&7,21 (1 287$ 9 7+(50$/ 3527(&7,21 6(16($ 3:0 +$/))8// 5(6(7 287$ 9 *$7( /2*,& &21752/ &/2&. 96$ 9%227 &+$5*( 3803 67(33,1* 6(48(1&( *(1(5$7,21 21(6+27 021267$%/( &:&&: 0$6.,1* 7,0(   6(16( &203$5$725 %5,'*($ 92/7$*( 5(*8/$725 9 9 95()$ 5&$ 96% 29(5 &855(17 '(7(&7,21 287% 287% 6(16(% *$7( /2*,& 95()% %5,'*(% 5&% ',19 DocID9454 Rev 3 3/34 34 Maximum ratings 2 L6228 Maximum ratings Table 1. Absolute maximum ratings Symbol Test conditions Value Unit VSA = VSB = VS 60 V VSA = VSB = VS = 60 V; VSENSEA = VSENSEB = GND 60 V VSA = VSB = VS VS + 10 V Input and enable voltage range - -0.3 to +7 V VREFA, VREFB Voltage range at pins VREFA and VREFB - -0.3 to +7 V VRCA, VRCB Voltage range at pins RCA and RCB - -0.3 to +7 V - -1 to +4 V Pulsed supply current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1ms 3.55 A RMS supply current (for each VS pin) VSA = VSB = VS 1.4 A - -40 to 150 C VS VOD VBOOT VIN, VEN Parameter Supply voltage Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Bootstrap peak voltage VSENSEA, Voltage range at pins SENSEA and SENSEB VSENSEB IS(peak) IS Tstg, TOP Storage and operating temperature range Table 2. Recommended operating conditions Symbol VS VOD VREFA, VREFB Parameter Supply voltage Differential voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB Voltage range at pins VREFA and VREFB VSENSEA, Voltage range at pins SENSEA and SENSEB VSENSEB Test conditions Min. Max. Unit VSA = VSB = VS 8 52 V VSA = VSB = VS; VSENSEA = VSENSEB - 52 V - -0.1 5 V (pulsed tW < trr) (DC) -6 -1 6 1 V V IOUT RMS output current - - 1.4 A fsw Switching frequency - - 100 KHz 4/34 DocID9454 Rev 3 L6228 Maximum ratings Table 3. Thermal data Symbol Description Rth-j-pins Maximum thermal resistance junction pins Rth-j-case Maximum thermal resistance junction case (1) SO24 PowerSO36 Unit 15 - C/W - 2 C/W 55 - C/W Rth-j-amb1 Maximum thermal resistance junction ambient Rth-j-amb1 Maximum thermal resistance junction ambient(2) - 36 C/W Rth-j-amb1 Maximum thermal resistance junction ambient (3) - 16 C/W Maximum thermal resistance junction ambient (4) 78 63 C/W Rth-j-amb2 1. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 µm). 2. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm). 3. Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 µm), 16 via holes and a ground layer. 4. Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board. DocID9454 Rev 3 5/34 34 Pin connections 3 L6228 Pin connections Figure 2. Pin connections (top view) CLOCK 1 24 VREFA CW/CCW 2 23 RESET SENSEA 3 22 VCP GND 1 36 GND N.C. 2 35 N.C. N.C. 3 34 N.C. VSA 4 33 VSB OUT2A 5 32 OUT2B N.C. RCA 4 21 OUT2A N.C. 6 31 OUT1A 5 20 VSA VCP 7 30 VBOOT GND 6 19 GND RESET 8 29 EN GND 7 18 GND OUT1B 8 17 VSB RCB 9 16 OUT2B SENSEB 10 15 VBOOT VREFB 11 14 EN HALF/FULL 12 13 CONTROL VREFA 9 28 CONTROL CLOCK 10 27 HALF/FULL CW/CCW 11 26 VREFB SENSEA 12 25 SENSEB RCB D99IN1083 RCA 13 24 N.C. 14 23 N.C. OUT1A 15 22 OUT1B N.C. 16 21 N.C. N.C. 17 20 N.C. GND 18 19 GND D99IN1084 PowerSO36(1) SO24 1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins). Table 4. Pin description Package SO24 PowerSO36 Pin no. Pin no. 1 10 6/34 Name Type Function CLOCK Logic input Step clock input. The state machine makes one step on each rising edge. 2 11 CW/CCW Logic input Selects the direction of the rotation. HIGH logic level sets clockwise direction, whereas LOW logic level sets counterclockwise direction. If not used, it has to be connected to GND or +5 V. 3 12 SENSEA Power supply Bridge A source pin. This pin must be connected to power ground through a sensing power resistor. 4 13 RCA RC pin RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time of the bridge A. 5 15 OUT1A Power output Bridge A output 1. DocID9454 Rev 3 L6228 Pin connections Table 4. Pin description (continued) Package SO24 PowerSO36 Pin no. Pin no. Name Type Function 6, 7, 18, 19 1, 18, 19, 36 GND GND Ground terminals. In SO24 package, these pins are also used for heat dissipation toward the PCB. On PowerSO36 package the slug is connected to these pins. 8 22 OUT1B Power output Bridge B output 1. 9 24 RCB RC pin RC network pin. A parallel RC network connected between this pin and ground sets the current controller OFF-time of the bridge B. 10 25 SENSEB Power supply Bridge B source pin. This pin must be connected to power ground through a sensing power resistor. 11 26 VREFB Analog input Bridge B current controller reference voltage. Do not leave this pin open or connected to GND. 12 27 HALF/FULL Logic input Step mode selector. HIGH logic level sets HALF STEP mode, LOW logic level sets FULL STEP mode. If not used, it has to be connected to GND or +5 V. Logic input Decay mode selector. HIGH logic level sets SLOW DECAY mode. LOW logic level sets FAST DECAY mode. If not used, it has to be connected to GND or +5 V. 13 28 CONTROL Chip enable. LOW logic level switches OFF all power MOSFETs of both bridge A and bridge B. This pin is also connected to the collector of the overcurrent and Logic input(1) thermal protection to implement overcurrent protection. If not used, it has to be connected to +5 V through a resistor. 14 29 EN 15 30 VBOOT Supply voltage Bootstrap voltage needed for driving the upper power MOSFETs of both bridge A and bridge B. 16 32 OUT2B Power output Bridge B output 2. 17 33 VSB Power supply Bridge B power supply voltage. It must be connected to the supply voltage together with pin VSA. 20 4 VSA Power supply Bridge A power supply voltage. It must be connected to the supply voltage together with pin VSB. 21 5 OUT2A Power output Bridge A output 2. 22 7 VCP Output Charge pump oscillator output. DocID9454 Rev 3 7/34 34 Pin connections L6228 Table 4. Pin description (continued) Package SO24 PowerSO36 Pin no. Pin no. Name Type Function 23 8 RESET Logic input Reset pin. LOW logic level restores the Home state (state 1) on the phase sequence generator state machine. If not used, it has to be connected to +5 V. 24 9 VREFA Analog input Bridge A current controller reference voltage. Do not leave this pin open or connected to GND. 1. Also connected at the output drain of the overcurrent and thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2 K - 180 K, recommended 100 K 8/34 DocID9454 Rev 3 L6228 4 Electrical characteristics Electrical characteristics Table 5. Electrical characteristics (Tamb = 25 °C, Vs = 48 V, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit VSth(ON) Turn-on threshold - 5.8 6.3 6.8 V VSth(OFF) Turn-off threshold - 5 5.5 6 V All bridges OFF; Tj = -25 °C to 125 °C(1) - 5 10 mA - - 165 - C - 1.47 1.69 W - 2.35 2.70 W EN = low; OUT = VS - - 2 mA EN = low; OUT = GND -0.3 - - mA ISD = 1.4 A, EN = LOW - 1.15 1.3 V IS Tj(OFF) Quiescent supply current Thermal shutdown temperature Output DMOS transistors RDS(ON) IDSS High-side + low-side switch ON resistance Leakage current Tj = 25 °C Tj = 125 °C(1) Source drain diodes VSD Forward ON voltage trr Reverse recovery time If = 1.4 A - 300 - ns tfr Forward recovery time - - 200 - ns Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW) VIL Low level logic input voltage - -0.3 - 0.8 V VIH High level logic input voltage - 2 - 7 V IIL Low level logic input current GND logic input voltage -10 - - µA IIH High level logic input current 7 V logic input voltage - - 10 µA Vth(ON) Turn-on input threshold - - 1.8 2.0 V Vth(OFF) Turn-off input threshold - 0.8 1.3 - V Vth(HYS) Input threshold hysteresis - 0.25 0.5 - V Enable to output turn-on delay time(2) ILOAD = 1.4 A, resistive load 500 650 800 ns time(2) ILOAD = 1.4 A, resistive load 500 800 1000 ns ILOAD = 1.4 A, resistive load 40 - 250 ns ILOAD = 1.4 A, resistive load 40 - 250 ns Switching characteristics tD(ON)EN tD(OFF)EN Enable to output turn-off delay tRISE tFALL Output rise time(2) (2) Output fall time ILOAD = 1.4 A, resistive load - 2 - µs time(4) - - - 1 µs tCLK(min)H Minimum clock time(4) - - - 1 µs - - - 100 KHz tDCLK Clock to output delay time(3) tCLK(min)L Minimum clock fCLK Clock frequency DocID9454 Rev 3 9/34 34 Electrical characteristics L6228 Table 5. Electrical characteristics (Tamb = 25 °C, Vs = 48 V, unless otherwise specified) (continued) Symbol Parameter Test conditions Min. Typ. tS(MIN) Minimum set-up time (5) - - - 1 µs tH(MIN) Minimum hold time(5) - - - 1 µs - - - 1 µs - - - 1 µs - 0.5 1 - µs Tj = -25 °C to 125 °C(1) - 0.6 1 MHz VRCA = VRCB = 2.5 V 3.5 5.5 - mA VREFA, VREFB = 0.5 V - ±5 - mV tR(MIN) (5) Minimum reset time (5) tRCLK(MIN) Minimum reset to clock delay time tDT Deadtime protection fCP Charge pump frequency Max. Unit PWM comparator and monostable IRCA, IRCB Source current at pins RCA and RCB Voffset Offset voltage on sense comparator tPROP Turn OFF propagation delay(6) - - 500 - ns tBLANK Internal blanking time on SENSE pins - - 1 - µs tON(MIN) Minimum On time - 2.5 3 µs ROFF = 20 KCOFF = 1 nF - 13 - µs ROFF = 100 KCOFF = 1 nF - 61 - µs - - - 10 µA Tj = -25 °C to 125 °C(1) 2 2.8 3.55 A tOFF PWM recirculation time IBIAS Input bias current at pins VREFA and VREFB Overcurrent protection ISOVER Input supply overcurrent protection threshold ROPDR Open drain ON resistance I = 4 mA - 40 60 W OCD turn-on delay time(7) I = 4 mA; CEN < 100 pF - 200 - ns tOCD(OFF) OCD turn-off delay time(7) I = 4 mA; CEN < 100 pF - 100 - ns tOCD(ON) 1. Tested at 25 °C in a restricted range and guaranteed by characterization. 2. See Figure 3: Switching characteristic definition. 3. See Figure 4: Clock to output delay time. 4. See Figure 5: Minimum timing definition; clock input. 5. See Figure 6: Minimum timing definition; logic inputs. 6. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF. 7. See Figure 7: Overcurrent detection timing definition. 10/34 DocID9454 Rev 3 L6228 Electrical characteristics Figure 3. Switching characteristic definition EN Vth(ON) Vth(OFF) t IOUT 90% 10% t D01IN1316 tRISE tFALL tD(OFF)EN tD(ON)EN Figure 4. Clock to output delay time CLOCK Vth(ON) t IOUT t D01IN1317 tDCLK Figure 5. Minimum timing definition; clock input CLOCK Vth(OFF) Vth(ON) tCLK(MIN)L DocID9454 Rev 3 Vth(OFF) tCLK(MIN)H D01IN1318 11/34 34 Electrical characteristics L6228 Figure 6. Minimum timing definition; logic inputs CLOCK Vth(ON) LOGIC INPUTS tS(MIN) RESET Vth(OFF) tH(MIN) Vth(ON) tR(MIN) tRCLK(MIN) D01IN1319 Figure 7. Overcurrent detection timing definition IOUT ISOVER ON BRIDGE OFF VEN 90% 10% tOCD(ON) 12/34 DocID9454 Rev 3 tOCD(OFF) D02IN1399 L6228 Circuit description 5 Circuit description 5.1 Power stages and charge pump The L6228device integrates two independent power MOS full bridges. Each power MOS has an RDS(ON) = 0.73  (typical value at 25 °C), with intrinsic fast freewheeling diode. Switching patterns are generated by the PWM current controller and the phase sequence generator (see Section 6). Cross conduction protection is achieved using a deadtime (tDT = 1 s typical value) between the switch off and switch on of two power MOSFETs in one leg of a bridge. Pins VSA and VSB MUST be connected together to the supply voltage VS. The device operates with a supply voltage in the range from 8 V to 52 V. It has to be noticed that the RDS(ON) increases of some percents when the supply voltage is in the range from 8 V to 12 V. Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The bootstrapped supply voltage VBOOT is obtained through an internal oscillator and few external components to realize a charge pump circuit as shown in Figure 8. The oscillator output (VCP) is a square wave at 600 KHz (typical) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table 6. Table 6. Charge pump external components values Component Value CBOOT 220 nF CP 10 nF RP 100  D1 1N4148 D2 1N4148 Figure 8. Charge pump circuit 74 % $#005 % 31 $1 7$1 7#005 74" 74# DocID9454 Rev 3 %*/ 13/34 34 Circuit description 5.2 L6228 Logic inputs Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS compatible logic inputs. The internal structure is shown in Figure 9. Typical value for turn-on and turn-off thresholds are respectively Vth(ON) = 1.8 V and Vth(OFF) = 1.3 V. Pin EN (“Enable”) has identical input structure with the exception that the drain of the overcurrent and thermal protection MOSFET is also connected to this pin. Due to this connection some care needs to be taken in driving this pin. The EN input may be driven in one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Figure 10. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Figure 11. The resistor REN should be chosen in the range from 2.2 K to 180 K. Recommended values for REN and CEN are respectively 100 K and 5.6 nF. More information on selecting the values is found in Section 7.5: Non-dissipative overcurrent protection on page 21. Figure 9. Logic inputs internal structure 9 (6' 3527(&7,21 ',19 Figure 10. EN pin open collector driving 9 9 5(1 23(1 &2//(&725 287387 (1 &(1 (6' 3527(&7,21 ',19 Figure 11. EN pin push-pull driving 9 386+38// 287387 5(1 (1 &(1 (6' 3527(&7,21 ',19 14/34 DocID9454 Rev 3 L6228 PWM current control 6 PWM current control The L6228device includes a constant off time PWM current controller for each of the two bridges. The current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 12. As the current in the motor builds up the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense comparator triggers the monostable switching the bridge off. The power MOS remains off for the time set by the monostable and the motor current recirculates as defined by the selected decay mode, described in Section 7: Decay modes on page 19. When the monostable times out the bridge will again turn on. Since the internal deadtime, used to prevent cross conduction in the bridge, delays the turn on of the power MOS, the effective off time is the sum of the monostable time plus the deadtime. Figure 12. PWM current controller simplified schematic 96$RU% %/$1.,1*7,0( 021267$%/( 72*$7(/2*,& PV )5207+( /2:6,'( *$7('5,9(56 P$ +  6 4  021267$%/( 6(7 + %/$1.(5 ,287 5 287$RU% '5,9(56  '($'7,0(  '5,9(56  '($'7,0(  9 3+$6( 67(33(502725 287$RU% 9 6(16( &203$5$725 /  &203$5$725 287387 5&$RU% &2)) /  6(16($RU% 95()$RU% 52)) 56(16( ',19 Figure 13 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. More details regarding the synchronous rectification and the output stage configuration are included in Section 7: Decay modes on page 19. Immediately after the power MOS turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The L6228 device provides a 1 s blanking time tBLANK that inhibits the comparator output so that this current spike cannot prematurely retrigger the monostable. DocID9454 Rev 3 15/34 34 PWM current control L6228 Figure 13. Output current regulation waveforms ,287 95() 56(16( W2)) W21 W2)) PVW%/$1. 96(16( PVW%/$1. 95() 6ORZGHFD\  6ORZGHFD\ FD\ FD\ )DVWGH )DVWGH W5&5,6( 95& W5&5,6( 9 9 W5&)$// W5&)$// PVW'7 PVW'7 21 2)) 6Q)@  $0 7.6 Thermal protection In addition to the overcurrent protection, the L6228 integrates a thermal protection for preventing the device destruction in case of junction overtemperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switchesoff when the junction temperature reaches 165 °C (typ. value) with 15 °C hysteresis (typ. value). 24/34 DocID9454 Rev 3 L6228 8 Application information Application information A typical bipolar stepper motor driver application using the L6228 device is shown in Figure 25. Typical component values for the application are shown in Table 7. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6228 device to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor connected from the EN input to ground sets the shutdown time when an overcurrent is detected (see Section 7.5: Non-dissipative overcurrent protection on page 21). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistors with a trace length as short as possible in the layout. The sense resistors should be non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused logic pins (except EN) are best connected to 5 V (high logic level) or GND (low logic level) (see Table 4: Pin description on page 6). It is recommended to keep power ground and signal ground separated on the PCB. Table 7. Component values for typical application Component Value Component Value C1 100 µF D1 1N4148 C2 100 nF D2 1N4148 CA 1 nF RA 39 K CB 1 nF RB 39 K CBOOT 220 nF REN 100 K CP 10 nF RP 100  CEN 5.6 nF RSENSEA 0.6  CREF 68 nF RSENSEB 0.6  DocID9454 Rev 3 25/34 34 Application information L6228 Figure 25. Typical application  96 9'& 96$ & 32:(5 *5281'  6,*1$/ *5281' 96% & ' &%227 53 ' &3     95()$ &5() 9&3 9%227 56(16($ 6(16($ 56(16(% 6(16(% 287$ 287$    287% *1' *1' *1' *1' (1         +$/))8// &/2&. )$676/2:'(&$< +$/))8// &/2&. &:&&: &:&&: &$  5&$ 5$ &%    (1$%/( &21752/   5(6(7 5(1 &(1  287% 5(6(7  0  5&% ',19 8.1 95() 9 95()% 5% Output current capability and IC power dissipation From Figure 26 to Figure 29 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving a two phase stepper motor, for different driving sequences:  HALF STEP mode (Figure 26) in which alternately one phase / two phases are energized.  NORMAL DRIVE (FULL STEP TWO PHASE ON) mode (Figure 27) in which two phases are energized during each step.  WAVE DRIVE (FULL STEP ONE PHASE ON) mode (Figure 28) in which only one phase is energized at each step.  MICROSTEPPING mode (Figure 29), in which the current follows a sine wave profile, provided through the Vref pins. For a given output current and driving sequence the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125 °C maximum). 26/34 DocID9454 Rev 3 L6228 Application information Figure 26. IC power dissipation versus output current in HALF STEP mode +$/ )67(3  ,$ , 287  ,%  3'>:@  , 287  7HVWFRQGLWLRQV 6XSSO\YROWDJH 9 1R3:0 I 6:  N+]VORZGHFD\          , 287 >$ @  $0 Figure 27. IC power dissipation versus output current in NORMAL mode (full step two phase on) 1250 $/'5,9( ,$   , 287 ,%  , 287 3'>: @  7HVWFRQGLWLRQV 6XSSO\YROWDJH 9        1R3:0 I 6: N+]VORZGHFD\   , 287 >$ @ $0 Figure 28. IC power dissipation versus output current in WAVE mode (full step one phase on) :$9('5,9(  ,$  , 287 ,%  3'>:@ , 287  7HVWFRQGLWLRQV 6XSSO\YROWDJH 9          1R3: 0 I6:  N+]VORZGHFD\ , 287>$@ $0 DocID9454 Rev 3 27/34 34 Application information L6228 Figure 29. IC power dissipation versus output current in MICROSTEPPING mode 0,&5267(33,1* ,$  , 287   ,% 3'>:@ , 287           , 287 >$@ 7HVWFRQGLWLRQV 6XSSO\YROWDJH 9 I 6: N+]VORZGHFD\ I 6: N+]VORZGHFD\ $0 8.2 Thermal management In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figure 30 and Figure 31 show the junction to ambient thermal resistance values for the PowerSO36 and SO24 packages. For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper thickness FR4 board with a 6 cm2 dissipating footprint (copper thickness of 35 µm), the Rth(j-amb) is about 35 °C/W. Figure 32 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15 °C/W. Figure 30. PowerSO36 junction ambient thermal resistance versus on-board copper area ž &:    :LWKRXWJURXQGOD\HU  :LWKJURXQGOD\HU  :LWKJURXQGOD\HU YLDKROHV 2QERDUGFRSSHUDUHD                V T  FP $0 28/34 DocID9454 Rev 3 L6228 Application information Figure 31. SO24 junction ambient thermal resistance versus on-board copper area ž &: 2QERDUGFRSSHUDUHD     &RSSHUDUHD LVRQWRSVLGH        V T  FP $0 Figure 32. Mounting the PowerSO package Slug soldered to PCB with dissipating area Slug soldered to PCB with dissipating area plus ground layer DocID9454 Rev 3 Slug soldered to PCB with dissipating area plus ground layer contacted through via holes 29/34 34 Package information 9 L6228 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 PowerSO36 package information Figure 33. PowerSO36 package outline 1 1 D H $ '(7$,/ $ $ F D '(7$,/ % ( H + '(7$,/ $ OHDG ' VOXJ D  %277209,(:  ( % ( ( ' '(7$,/ %    *DJH3ODQH  &  6 K[€ E / 6($7,1*3/$1( * †  0 $% 3620(& & &23/$1$5,7<   30/34 DocID9454 Rev 3 L6228 Package information Table 8. PowerSO36 package mechanical data Dimensions Symbol mm inch Min. Typ. Max. Min. Typ. Max. A - - 3.60 - - 0.141 a1 0.10 - 0.30 0.004 - 0.012 - 3.30 - - 0.130 a2 a3 0 - 0.10 0 - 0.004 b 0.22 - 0.38 0.008 - 0.015 c 0.23 - 0.32 0.009 - 0.012 D(1) 15.80 - 16.00 0.622 - 0.630 D1 9.40 - 9.80 0.370 - 0.385 E 13.90 - 14.50 0.547 - 0.570 e - 0.65 - - 0.0256 - e3 - 11.05 - - 0.435 - 10.90 - 11.10 0.429 - 0.437 E2 - - 2.90 - - 0.114 E3 5.80 - 6.20 0.228 - 0.244 E4 2.90 - 3.20 0.114 - 0.126 G 0 - 0.10 0 - 0.004 H 15.50 - 15.90 0.610 - 0.626 h - - 1.10 - - 0.043 L 0.80 - 1.10 0.031 - 0.043 (1) E1 N 10° (max.) S 8° (max.) 1. “D” and “E1” do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch). - Critical dimensions are “a3”, “E” and “G”. DocID9454 Rev 3 31/34 34 Package information 9.2 L6228 SO24 package information Figure 34. SO24 package outline  & Table 9. SO24 package mechanical data Dimensions (mm) Dimensions (inch) Symbol Min. Typ. Max. Min. Typ. Max. A 2.35 - 2.65 0.093 - 0.104 A1 0.10 - 0.30 0.004 - 0.012 B 0.33 - 0.51 0.013 - 0.020 C 0.23 - 0.32 0.009 - 0.013 D(1) 15.20 - 15.60 0.598 - 0.614 E 7.40 - 7.60 0.291 - 0.299 e - 1.27 - - 0.050 - H 10.0 - 10.65 0.394 - 0.419 h 0.25 - 0.75 0.010 - 0.030 L 0.40 - 1.27 0.016 - 0.050 - 0.004 k ddd 0° (min.), 8° (max.) - - 0.10 - 1. D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. 32/34 DocID9454 Rev 3 L6228 10 Revision history Revision history Table 10. Document revision history Date Revision Changes 03-Sep-2003 1 Initial release. 18-Feb-2014 2 Updated Section : Description on page 1 (removed “MultiPower-” from “MultiPower-BCD technology” Added Contents on page 2. Updated Section 1: Block diagram (added section title, numbered and moved Figure 1: Block diagram from page 1 to page 3. Added title to Section 2: Maximum ratings on page 4, added numbers and titles from Table 1: Absolute maximum ratings to Table 3: Thermal data. Added title to Section 3: Pin connections on page 6, added number and title to Figure 2: Pin connections (top view), renumbered note 1 below Figure 2, added title to Table 4: Pin description, renumbered note 1 below Table 4. Added title to Section 4: Electrical characteristics on page 9, added title and number to Table 5, renumbered notes 1 to 7 below Table 5. Renumbered Figure 3 to Figure 7. Added numbers to Section 5: Circuit description on page 13 (including Section 5.1 and Section 5.2). Removed “and uC” from Section 5.2. Renumbered Table 6 , added header to Table 6. Renumbered Figure 8 to Figure 11. Added numbers to Section 6: PWM current control on page 15. Renumbered Figure 12 to Figure 15. Added titles to Equation 1: on page 16 till Equation 4: on page 17. Added numbers to Section 7: Decay modes on page 19 (including Section 7.1 to Section 7.6). Renumbered Figure 16 to Figure 24. Added numbers to Section 8: Application information on page 25 (including Section 8.1 and Section 8.2). Renumbered Table 7, added header to Table 7. Renumbered Figure 25 to Figure 33. Updated Section 9: Package information on page 30 (added main title and ECOPACK text. Added titles from Table 8: PowerSO36 package mechanical data to Table 10: SO24 package mechanical data and from Figure 34: PowerSO36 package outline to Figure 36: SO24 package outline, reversed order of named tables and figures. Removed 3D figures of packages, replaced 0.200 by 0.020 inch of max. B value in Table 10). Added cross-references throughout document. Added Table 11: Document revision history. Minor modifications throughout document. 03-Oct-2018 3 Removed PowerDIP24 package from the whole document. Removed “Tj“ from Table 2 on page 4. Minor modifications throughout document. DocID9454 Rev 3 33/34 34 L6228 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved 34/34 DocID9454 Rev 3