L6229Q
DMOS driver for three-phase brushless DC motor
Features
■
Operating supply voltage from 8 to 52 V
■
2.8 A output peak current (1.4 A RMS)
■
RDS(on) 0.73 Ω typ. value @ TJ = 25 °C
■
Operating frequency up to 100 kHz
■
Non dissipative overcurrent detection and
protection
■
Diagnostic output
■
Constant tOFF PWM current controller
■
Slow decay synchronous rectification
■
60° and 120° hall effect decoding logic
■
Brake function
■
Cross conduction protection
■
Thermal shutdown
■
Under voltage lockout
■
Integrated fast free wheeling diodes
VFQFPN32 5 mm x 5 mm
Description
The L6229Q is a DMOS fully integrated threephase motor driver with overcurrent protection.
Realized in BCDmultipower technology, the
device combines isolated DMOS power
transistors with CMOS and bipolar circuits on the
same chip.
The device includes all the circuitry needed to
drive a three-phase BLDC motor including: a
three-phase DMOS bridge, a constant off time
PWM current controller and the decoding logic for
single ended hall sensors that generates the
required sequence for the power stage.
Available in VFQFPN-32 5 x 5 package, the
L6229Q features a non-dissipative overcurrent
protection on the high side power MOSFETs and
thermal shutdown.
Table 1.
Device summary
Order codes
Package
L6229Q
Packaging
Tube
VFQFPN32 5x5x1.0 mm
L6229QTR
August 2010
Tape and reel
Doc ID 15209 Rev 3
1/28
www.st.com
28
Contents
L6229Q
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6
5.1
Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3
PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4
Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5
Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6
Tacho . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.7
Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 20
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
Output current capability and ic power dissipation . . . . . . . . . . . . . . . . . . 23
6.2
Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2/28
Doc ID 15209 Rev 3
L6229Q
1
Block diagram
Block diagram
Figure 1.
Block diagram
VBOOT
VCP
VBOOT
VBOOT
VSA
THERMAL
PROTECTION
CHARGE
PUMP
OCD1
DIAG
OCD
OUT1
10V
OCD1
OCD2
OCD
OCD3
VBOOT
EN
BRAKE
FWD/REV
OCD2
H3
HALL-EFFECT
SENSORS
DECODING
LOGIC
H2
GATE
LOGIC
SENSEA
VBOOT
H1
RCPULSE
OUT2
10V
TACHO
MONOSTABLE
VSB
OCD3
OUT3
10V
TACHO
10V
5V
SENSEB
PWM
VOLTAGE
REGULATOR
ONE SHOT
MONOSTABLE
MASKING
TIME
+
SENSE
COMPARATOR
VREF
RCOFF
D99IN1095B
Doc ID 15209 Rev 3
3/28
Electrical data
L6229Q
2
Electrical data
2.1
Absolute maximum ratings
Table 2.
Absolute maximum ratings
Symbol
Parameter
VS
VOD
VBOOT
Parameter
Value
Unit
Supply voltage
VSA = VSB = VS
60
V
Differential voltage between:
VSA, OUT1, OUT2, SENSEA and
VSB, OUT3, SENSEB
VSA = VSB = VS = 60 V;
VSENSEA = VSENSEB =
GND
60
V
Bootstrap peak voltage
VSA = VSB = VS
VS + 10
V
VIN, VEN
Logic inputs voltage range
-0.3 to +7
V
VREF
Voltage range at pin VREF
-0.3 to +7
V
Voltage range at pin RCOFF
-0.3 to +7
V
Voltage range at pin RCPULSE
-0.3 to +7
V
-1 to +4
V
VSA = VSB = VS;
TPULSE < 1 ms
3.55
A
RMS supply current (for each VS pin) VSA = VSB = VS
1.4
A
-40 to 150
°C
VRCOFF
VRCPULSE
VSENSE
Voltage range at pins SENSEA and
SENSEB
IS(peak)
Pulsed supply current (for each VS
pin)
IS
Storage and operating temperature
range
Tstg, TOP
2.2
Recommended operating conditions
Table 3.
Recommended operating conditions
Symbol
VS
VOD
VREFA, VREFB
VSENSEA,
VSENSEB
IOUT
4/28
Parameter
Parameter
Supply voltage
VSA = VSB = VS
Differential voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
Voltage range at pins VREFA and
VREFB
Voltage range at pins SENSEA and
SENSEB
(pulsed tW < trr)
(DC)
Min
Max
Unit
8
52
V
52
V
-0.1
5
V
-6
-1
6
1
V
V
1.4
A
+125
°C
100
kHz
RMS output current
TJ
Operating junction temperature
fsw
Switching frequency
Doc ID 15209 Rev 3
-25
L6229Q
2.3
Electrical data
Thermal data
Table 4.
Symbol
Rth(JA)
Thermal data
Parameter
Thermal resistance junction-ambient max. (1)
Value
Unit
42
°C/W
2
1. Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm on the top side plus 6
cm2 ground layer connected through 18 via holes (9 below the IC).
Doc ID 15209 Rev 3
5/28
Pin connection
Pin connection
OUT1
RCOFF
SENSEA
DIAG
H1
H3
H2
Pin connection (top view)
32
31
30
29
28
27
26
25
23
OUT2
NC
3
22
VSA
NC
4
21
GND
NC
5
20
VSB
NC
6
19
OUT3
NC
7
18
NC
NC
8
17
VBOOT
TACHO
9
Note:
6/28
10
11
12
13
14
15
16
BRAKE
2
VREF
NC
EN
VCP
FW/REW
24
SENSEB
1
RCPULSE
GND
NC
Figure 2.
NC
3
L6229Q
1
The pins 2 to 8 are connected to die PAD.
2
The die PAD must be connected to GND pin.
Doc ID 15209 Rev 3
L6229Q
Table 5.
Pin connection
Pin description
N°
Pin
Type
Function
1, 21
GND
GND
9
TACHO
Open drain
output
Frequency-to-voltage open drain output. Every pulse from pin H1 is shaped
as a fixed and adjustable length pulse.
11
RCPULSE
RC pin
RC network pin. A parallel RC network connected between this pin and
ground sets the duration of the monostable pulse used for the frequency-tovoltage converter.
12
SENSEB
13
FWD/REV
Logic input
Selects the direction of the rotation. HIGH logic level sets forward operation,
whereas LOW logic level sets reverse operation.
If not used, it has to be connected to GND or +5 V.
14
EN
Logic input
Chip enable. LOW logic level switches OFF all power MOSFETs.
If not used, it has to be connected to +5 V.
15
VREF
Logic input
Current controller reference voltage.
Do not leave this pin open or connect to GND.
16
BRAKE
Logic input
Brake input pin. LOW logic level switches ON all high side power MOSFETs,
implementing the brake function.
If not used, it has to be connected to +5 V.
17
VBOOT
Supply
voltage
19
OUT3
20
VSB
Power supply
Half bridge 3 power supply voltage. It must be connected to the supply
voltage together with pin VSA.
22
VSA
Power supply
Half bridge 1 and half bridge 2 power supply voltage. It must be connected to
the supply voltage together with pin VSB.
23
OUT2
24
VCP
25
H2
Sensor input Single ended hall effect sensor input 2.
26
H3
Sensor input Single ended hall effect sensor input 3.
27
H1
Sensor input Single ended hall effect sensor input 1.
28
DIAG
Open drain
output
29
SENSEA
Power supply
30
RCOFF
RC pin
31
OUT1
Ground terminals.
Half bridge 3 source Pin. This pin must be connected together with pin
Power supply SENSEA to power ground through a sensing power resistor. At this pin also
the Inverting Input of the sense comparator is connected.
Bootstrap voltage needed for driving the upper power MOSFETs.
Power output Output half bridge 3.
Power output Output half bridge 2.
Output
Charge pump oscillator output.
Overcurrent detection and thermal protection pin. An internal open drain
transistor pulls to GND when an overcurrent on one of the high side
MOSFETs is detected or during thermal protection.
Half bridge 1 and half bridge 2 source pin. This pin must be connected
together with pin SENSEB to power ground through a sensing power resistor.
RC network pin. A parallel RC network connected between this pin and
ground sets the current controller OFF-Time.
Power output Output half bridge 1.
Doc ID 15209 Rev 3
7/28
Electrical characteristics
L6229Q
4
Electrical characteristics
Table 6.
Electrical characteristics
(VS = 48 V, TA = 25 °C, unless otherwise specified)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
VSth(ON)
Turn-on threshold
5.8
6.3
6.8
V
VSth(OFF)
Turn-off threshold
5
5.5
6
V
5
10
mA
IS
Tj(OFF)
All bridges OFF;
TJ = -25 °C to 125 °C(1)
Quiescent supply current
Thermal shutdown temperature
°C
165
Output DMOS transistors
RDS(on)
IDSS
High-side + low-side switch ON
resistance
TJ = 25 °C
1.47
1.69
Ω
TJ =125 °C (1)
2.35
2.70
Ω
2
mA
EN = Low; OUT = VS
Leakage current
EN = Low; OUT = GND
-0.3
mA
Source drain diodes
VSD
Forward ON voltage
ISD = 1.4 A, EN = LOW
1.15
1.3
V
trr
Reverse recovery time
If = 1.4 A
300
ns
tfr
Forward recovery time
200
ns
Logic inputs (EN, CONTROL, HALF/FULL, CLOCK, RESET, CW/CCW)
VIL
Low level logic input voltage
-0.3
0.8
V
VIH
High level logic input voltage
2
7
V
IIL
Low level logic input current
GND logic input voltage
IIH
High level logic input current
7 V logic input voltage
-10
µA
1.8
10
µA
2.0
V
Vth(ON)
Turn-on input threshold
Vth(OFF)
Turn-off input threshold
0.8
1.3
V
Vth(HYS)
Input threshold hysteresis
0.25
0.5
V
650
Switching characteristics
tD(ON)EN
Enable to output turn-on delay
time (2)
500
tD(OFF)EN
Enable to output turn-off delay time (2)
500
tD(on)IN
tD(off)IN
tRISE
tFALL
tDT
8/28
Other logic inputs to OUT turn-ON delay
time
ILOAD = 1.4 A, resistive load
Other logic inputs to OUT turn-OFF
delay time
Output rise time (2)
Output fall time
(2)
Dead time
ns
1000
ns
1.6
µs
800
ns
40
250
ns
40
250
ns
0.5
Doc ID 15209 Rev 3
800
1
µs
L6229Q
Table 6.
Electrical characteristics
Electrical characteristics (continued)
(VS = 48 V, TA = 25 °C, unless otherwise specified)
Symbol
fCP
Parameter
Test condition
Charge pump frequency
TJ = -25 °C to 125 °C
Min
(1)
Typ
Max
Unit
0.6
1
MHz
PWM comparator and monostable
IRCOFF
VOFFSET
Source current at pin RCOFF
Offset voltage on sense comparator
(4)
tprop
Turn OFF propagation delay
tblank
Internal blanking time on sense
comparator
tON(min)
VRCOFF = 2.5 V
(3)
3.5
5.5
mA
Vref = 0.5 V
±5
mV
Vref = 0.5 V
500
ns
1
µs
Minimum on time
2.5
tOFF
PWM recirculation time
IBIAS
Input bias current at pin VREF
3
µs
ROFF = 20 kΩ; COFF = 1 nF
13
μs
ROFF = 100 kΩ; COFF = 1 nF
61
μs
10
µA
Tacho monostable
IRCPULSE
Source current at pin RCPULSE
tPULSE
Monostable of time
RTACHO
Open drain ON resistance
VRCPULSE = 2.5 V
3.5
5.5
mA
RPUL = 20 kΩ; CPUL = 1 nF
12
μs
RPUL = 100 kΩ; CPUL = 1 nF
60
μs
40
60
W
2.8
3.55
A
60
W
Over current detection and protection
ISOVER
Supply overcurrent protection threshold TJ = -25 to 125 °C (2)
ROPDR
Open drain ON resistance
IDIAG = 4 mA
40
OCD high level leakage current
VDIAG = 5 V
1
µA
IDIAG = 4 mA; CDIAG < 100 pF
200
ns
IDIAG = 4 mA; CDIAG < 100 pF
100
ns
IOH
tOCD(ON)
tOCD(OFF)
OCD turn-ON delay time
(4)
OCD turn-OFF delay time
(4)
2
1. Tested at 25 °C in a restricted range and guaranteed by characterization
2. See Figure 3.
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
4. See Figure 4.
Doc ID 15209 Rev 3
9/28
Electrical characteristics
Figure 3.
L6229Q
Switching characteristic definition
EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tD(OFF)EN
Figure 4.
tRISE
tFALL
tD(ON)EN
Overcurrent detection timing definition
IOUT
ISOVER
ON
BRIDGE
OFF
VDIAG
90%
10%
tOCD(ON)
10/28
Doc ID 15209 Rev 3
tOCD(OFF)
D02IN1387
L6229Q
Circuit description
5
Circuit description
5.1
Power stages and charge pump
The L6229Q integrates a three-phase bridge, which consists of 6 power MOSFETs
connected as shown on the block diagram (see Figure 1). each power MOS has an
RDS(ON) = 0.73 Ω (typical value @ 25 °C) with intrinsic fast freewheeling diode. Switching
patterns are generated by the PWM current controller and the hall effect sensor decoding
logic (see relative paragraph 3.3 and 3.5). Cross conduction protection is implemented by
using a dead time (tDT = 1 µs typical value) set by internal timing circuit between the turn off
and turn on of two power MOSFETs in one leg of a bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped supply (VBOOT) is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600 kHz (typically)
with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are
shown in Table 7.
Table 7.
Figure 5.
Charge pump external component values
Component
Value
CBOOT
220 nF
CP
10 nF
D1
1N4148
D2
1N4148
Charge pump circuit
VS
D1
CBOOT
D2
CP
VCP
VBOOT
VSA
Doc ID 15209 Rev 3
VSB
D01IN1328
11/28
Circuit description
5.2
L6229Q
Logic inputs
Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS and microcontroller compatible
logic inputs. The internal structure is shown in Figure 6. Typical value for turn-on and turn-off
thresholds are respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V.
Pin EN (Enable) has identical input structure with the exception that the drain of the
Overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection some care needs to be taken in driving this pin. The EN input may be driven in
one of two configurations as shown in Figure 10 or Figure 11. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in
Figure 10. If the driver is a standard Push-Pull structure the resistor REN and the capacitor
CEN are connected as shown in Figure 11. The resistor REN should be chosen in the range
from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 10 kΩ and
5.6 nF. More information on selecting the values is found in the overcurrent protection
section.
Figure 6.
Logic inputs internal structure
5V
ESD
PROTECTION
D01IN1329
Figure 7.
Pin EN open collector driving
DIAG
5V
5V
REN
OPEN
COLLECTOR
OUTPUT
CEN
EN
ESD
PROTECTION
D02IN1378
Figure 8.
Pin EN push-pull driving
DIAG
5V
PUSH-PULL
OUTPUT
REN
EN
CEN
ESD
PROTECTION
D02IN1379
12/28
Doc ID 15209 Rev 3
L6229Q
5.3
Circuit description
PWM current control
The L6229Q includes a constant off time PWM current controller. The current control circuit
senses the bridge current by sensing the voltage drop across an external sense resistor
connected between the source of the three lower power MOS transistors and ground, as
shown in Figure 9. As the current in the motor increases the voltage across the sense
resistor increases proportionally. When the voltage drop across the sense resistor becomes
greater than the voltage at the reference input pin VREF the sense comparator triggers the
monostable switching the bridge off. The power MOS remain off for the time set by the
monostable and the motor current recirculates around the upper half of the bridge in slow
decay mode as described in the next section. When the monostable times out, the bridge
will again turn on. Since the internal dead time, used to prevent cross conduction in the
bridge, delays the turn on of the power MOS, the effective off time tOFF is the sum of the
monostable time plus the dead time.
Figure 10 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the pin RC voltage and the status of the bridge. More details
regarding the synchronous rectification and the output stage configuration are included in
the next section.
Immediately after the power MOS turn on, a high peak current flows through the sense
resistor due to the reverse recovery of the freewheeling diodes. The L6229Q provides a 1 µs
blanking time tBLANK that inhibits the comparator output so that the current spike cannot
prematurely re trigger the monostable.
Figure 9.
PWM current controller simplified schematic
VSB
VSA
VS
BLANKING TIME
MONOSTABLE
TO GATE
LOGIC
1μs
5mA
FROM THE
LOW-SIDE
GATE DRIVERS
MONOSTABLE
SET
S
(0)
BLANKER
OUT2
Q
(1)
OUT3
R
DRIVERS
+
DEAD TIME
-
DRIVERS
+
DEAD TIME
+
5V
2.5V
OUT1
DRIVERS
+
DEAD TIME
+
SENSE
COMPARATOR
COFF
-
RCOFF
VREF
ROFF
RSENSE
SENSEB
SENSEA
D02IN1380
Doc ID 15209 Rev 3
13/28
Circuit description
L6229Q
Figure 10. Output current regulation waveforms
IOUT
VREF
RSENSE
tON
tOFF
tOFF
1μs tBLANK
VSENSE
1μs tBLANK
VREF
Slow Decay
0
Slow Decay
tRCRISE
VRC
tRCRISE
5V
2.5V
tRCFALL
tRCFALL
1μs tDT
1μs tDT
ON
OFF
SYNCHRONOUS RECTIFICATION
B
D02IN1351
C
D
A
B
C
D
Figure 11 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be
approximately calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated
Dead Time with:
20 kΩ ≤ ROFF ≤ 100 kΩ
0.47 nF ≤ COFF ≤ 100 nF
tDT = 1 µs (typical value)
Therefore:
tOFF(MIN) = 6.6 µs
tOFF(MAX) = 6 ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the
pin RCOFF. The rise time tRCRISE will only be an issue if the capacitor is not completely
charged before the next time the monostable is triggered. Therefore, the on time tON, which
depends by motors and supply parameters, has to be bigger than tRCRISE for allowing a
good current regulation by the PWM stage. Furthermore, the on time tON can not be smaller
than the minimum on time tON(MIN).
14/28
Doc ID 15209 Rev 3
L6229Q
Circuit description
⎧ t ON > t ON ( MIN ) = 2.5μs ⎫
⎨
⎬
⎩ t ON > t RCRISE – t DT
⎭
(typ. value)
tRCRISE = 600 · COFF
Figure 12 shows the lower limit for the on time tON for having a good PWM current regulation
capacity. It has to be said that tON is always bigger than tON(MIN) because the device imposes
this condition, but it can be smaller than tRCRISE - tDT. In this last case the device continues
to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and,
therefore, higher switching frequency), but, the smaller is the value for COFF, the more
influential will be the noises on the circuit performance.
Figure 11. tOFF versus COFF and ROFF
4
1 .10
R off = 100kΩ
3
1 .10
R off = 47kΩ
toff [μs]
R off = 20kΩ
100
10
1
0.1
1
10
100
Coff [nF]
Figure 12. Area where tON can vary maintaining the PWM regulation
ton(min) [us]
100
10
2.5μs (typ. value)
1
0.1
1
10
100
Coff [nF]
Doc ID 15209 Rev 3
15/28
Circuit description
5.4
L6229Q
Slow decay mode
Figure 13 shows the operation of the bridge in the slow decay mode during the off time. At
any time only two legs of the three-phase bridge are active, therefore only the two active
legs of the bridge are shown in the figure and the third leg will be off. At the start of the Off
Time, the lower power MOS is switched off and the current recirculates around the upper
half of the bridge. Since the voltage across the coil is low, the current decays slowly. After
the dead time the upper power MOS is operated in the synchronous rectification mode
reducing the impedance of the freewheeling diode and the related conducting losses. When
the monostable times out, upper MOS that was operating the synchronous mode turns off
and the lower power MOS is turned on again after some delay set by the dead time to
prevent cross conduction.
Figure 13. Slow decay mode output stage configurations
A) ON TIME
B) 1μs DEAD TIME
D01IN1336
5.5
C) SYNCHRONOUS
RECTIFICATION
D) 1μs DEAD TIME
Decoding logic
The decoding logic section is a combinatory logic that provides the appropriate driving of the
three-phase bridge outputs according to the signals coming from the three hall sensors that
detect rotor position in a 3-phase BLDC motor. This novel combinatory logic discriminates
between the actual sensor positions for sensors spaced at 60, 120, 240 and 300 electrical
degrees. This decoding method allows the implementation of a universal IC without
dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are
valid for rotor positions with 120 electrical degrees sensor phasing (see Figure 14, positions
1, 2, 3a, 4, 5 and 6a) and six combinations are valid for rotor positions with 60 electrical
degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b). Four of them are in
common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical
degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical
degrees sensor phasing (3b and 6b).
The decoder can drive motors with different sensor configuration simply by following the
Table 8. For any input configuration (H1, H2 and H3) there is one output configuration (OUT1,
OUT2 and OUT3). The output configuration 3a is the same than 3b and analogously output
configuration 6a is the same than 6b.
The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and
the sequence of the Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60
16/28
Doc ID 15209 Rev 3
L6229Q
Circuit description
and the 120 codes it is possible to drive the motor with all the four conventions by changing
the direction set.
Table 8.
60 and 120 electrical degree decoding logic in forward direction
Hall 120°
1
2
3a
-
4
5
6a
-
Hall 60°
1
2
-
3b
4
5
-
6b
H1
H
H
L
H
L
L
H
L
H2
L
H
H
H
H
L
L
L
H3
L
L
L
H
H
H
H
L
OUT1
Vs
High Z
GND
GND
GND
High Z
Vs
Vs
OUT2
High Z
Vs
Vs
Vs
High Z
GND
GND
GND
OUT3
GND
GND
High Z
High Z
Vs
Vs
High Z
High Z
Phasing
1->3
2->3
2->1
2->1
3->1
3->2
1->2
1->2
Figure 14. 120° hall sensor sequence
H1
H3
H1
H2
1
=H
H3
H1
H2
2
H3
H1
H2
H3
3a
H1
H2
4
H3
H1
H2
5
H3
H2
6a
=L
Figure 15. 60° hall sensor sequence
H1
H1
H2
H3
H2
H3
1
=H
H1
2
H1
H2
H3
3b
H1
H2
H3
4
H1
H2
H3
5
H2
H3
6b
=L
Doc ID 15209 Rev 3
17/28
Circuit description
5.6
L6229Q
Tacho
A tachometer function consists of a monostable, with constant off time (tPULSE), whose input
is one hall effect signal (H1). It allows developing an easy speed control loop by using an
external op amp, as shown in Figure 17. For component values refer to Application
Information section.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the
hall effect sensors H1, the monostable is triggered and the MOSFET connected to pin
TACHO is turned off for a constant time tPULSE (see Figure 16). The off time tPULSE can be
set using the external RC network (RPUL, CPUL) connected to the pin RCPULSE. Figure 18
gives the relation between tPULSE and CPUL, RPUL. We have approximately:
tPULSE = 0.6 · RPUL · CPUL
where CPUL should be chosen in the range 1 nF … 100 nF and RPUL in the range
20 kΩ … 100 kΩ.
By connecting the tachometer pin to an external pull-up resistor, the output signal average
value VM is proportional to the frequency of the hall effect signal and, therefore, to the motor
speed. This realizes a simple frequency-to-voltage converter. An op amp, configured as an
integrator, filters the signal and compares it with a reference voltage VREF, which sets the
speed of the motor.
t PULSE
V M = ------------------ ⋅ V DD
T
Figure 16. Tacho operation waveforms
H1
H2
H3
VTACHO
VDD
VM
t PULSE
T
18/28
Doc ID 15209 Rev 3
L6229Q
Circuit description
Figure 17. Tachometer speed control loop
H1
RCPULSE
TACHO
MONOSTABLE
VDD
RPUL
CPUL
RDD
R3
TACHO
C1
R4
VREF
R1
VREF
CREF2
CREF1
R2
Figure 18. tPULSE versus CPUL and RPUL
4
1 .10
R PUL = 100kΩ
R PUL = 47kΩ
3
1 .10
tpulse [μs]
R PUL = 20kΩ
100
10
1
10
Cpul [nF]
Doc ID 15209 Rev 3
100
19/28
Circuit description
5.7
L6229Q
Non-dissipative overcurrent detection and protection
The L6229Q integrates an overcurrent detection circuit (OCD) for full protection. This circuit
provides output-to-output and output-to-ground short circuit protection as well. With this
internal over current detection, the external current sense resistor normally used and its
associated power dissipation are eliminated. Figure 19 shows a simplified schematic for the
overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current IREF. When the
output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD
comparator signals a fault condition. When a fault condition is detected, an internal open
drain MOS with a pull down capability of 4 mA connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a μC or to shut down the threephase bridge simply by connecting it to pin EN and adding an external R-C (see REN, CEN).
Figure 19. Overcurrent protection simplified schematic
OUT1
VSA
HIGH SIDE DMOS
μC or LOGIC
VDD
REN
VSB
HIGH SIDE DMOS
I2
POWER DMOS
n cells
POWER DMOS
n cells
I3
POWER SENSE
1 cell
POWER DMOS
n cells
POWER SENSE
1 cell
+
OCD
COMPARATOR
EN
OUT3
HIGH SIDE DMOS
I1
POWER SENSE
1 cell
TO GATE
LOGIC
OUT2
I1 / n
I2/ n
I1+I2 / n
CEN
INTERNAL
OPEN-DRAIN
DIAG
RDS(ON)
40Ω TYP.
IREF
OVER TEMPERATURE
I3/ n
IREF
D02IN1381
Figure 20 shows the overcurrent detection operation. The disable time tDISABLE before
recovering normal operation can be easily programmed by means of the accurate
thresholds of the logic inputs. It is affected whether by CEN and REN values and its
magnitude is reported in Figure 21. The delay time tDELAY before turning off the bridge when
an overcurrent has been detected depends only by CEN value. Its magnitude is reported in
Figure 22
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore
the value of CEN should be chosen as big as possible according to the maximum tolerable
delay time and the REN value should be chosen according to the desired disable time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs
disable time.
20/28
Doc ID 15209 Rev 3
L6229Q
Circuit description
Figure 20. Overcurrent protection waveforms
IOUT
ISOVER
VEN=VDIAG
VDD
Vth(ON)
Vth(OFF)
VEN(LOW)
ON
OCD
OFF
ON
tDELAY
BRIDGE
tDISABLE
OFF
tOCD(ON)
tEN(FALL)
tOCD(OFF)
tEN(RISE)
tD(ON)EN
tD(OFF)EN
D02IN1383
Figure 21. tDISABLE versus CEN and REN
R EN = 220 kΩ
3
1 .1 0
R EN = 100 kΩ
R EN = 47 kΩ
R EN = 33 kΩ
tDISABLE [µs]
R EN = 10 kΩ
100
10
1
1
10
100
C E N [n F ]
Figure 22. tDELAY versus CEN.
tdelay [μs]
10
1
0.1
1
10
Cen [nF]
Doc ID 15209 Rev 3
100
21/28
Application information
6
L6229Q
Application information
A typical application using L6229Q is shown in Figure 23. Typical component values for the
application are shown in Table 9. A high quality ceramic capacitor (C2) in the range of
100 nF to 200 nF should be placed between the power pins VSA and VSB and ground near
the L6229Q to improve the high frequency filtering on the power supply and reduce high
frequency transients generated by the switching. The capacitor (CEN) connected from the
EN input to ground sets the shut down time when an over current is detected (see
overcurrent protection). The two current sensing inputs (SENSEA and SENSEB) should be
connected to the sensing resistor RSENSE with a trace length as short as possible in the
layout. The sense resistor should be non-inductive resistor to minimize the dI/dt transients
across the resistor. To increase noise immunity, unused logic pins are best connected to 5 V
(high logic level) or GND (low logic level) (see pin description). It is recommended to keep
power ground and signal ground separated on PCB.
Table 9.
22/28
Component values for typical application
Component
Value
C1
100 µF
C2
100 nF
C3
220 nF
CBOOT
220 nF
COFF
1 nF
CPUL
10 nF
CREF1
33 nF
CREF2
100 nF
CEN
5.6 nF
CP
10 nF
D1
1N4148
D2
1N4148
R1
5 k6Ω
R2
1 k8Ω
R3
4 k7Ω
R4
1 MΩ
RDD
1 kΩ
REN
100 kΩ
RSENSE
0.6 Ω
ROFF
33 kΩ
RPUL
47 kΩ
RH1, RH2, RH3
10 kΩ
Doc ID 15209 Rev 3
L6229Q
Application information
Figure 23. Typical application
to SENSEB
to EN
H1
H3
H2
32
31
30
29
28
27
26
25
NC
RCOFF
SENSEA
DIAG
H1
H3
H2
COFF
OUT1
ROFF
Cp
1
GND
VCP 24
2
NC
3
NC
VSA 22
4
NC
GND 21
5
NC
VSB 20
6
NC
OUT3 19
7
NC
NC 18
8
NC
OUT2 23
EN
VREF
BRAKE
9
10
11
12
13
14
15
16
CPUL
RPUL
D2
+
C1
_
SIGNAL
GROUND
VBOOT 17
VREF
R1
CREF1
CREF1
R2
C3
R4
REN
CEN
6.1
Vs
8 ÷ 52 VDC
C2
POWER
GROUND
Cboot
BRAKE
H1 H2 H3
FW/REW
RH3
RSENSE
RH2
FWD/REW
RH1
SENSEB
+5V
RCPULSE
M
NC
HALL
SENSOR
TACHO
D1
THREE-PHASE MOTOR
ENABLE
+5V
R3
RDD
Output current capability and ic power dissipation
In Figure 24 is shown the approximate relation between the output current and the IC power
dissipation using PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper
dissipating area to guarantee a safe operating junction temperature (125 °C maximum).
Figure 24. IC power dissipation versus output power
I1
IOUT
10
I2
8
PD [W]
6
IOUT
I3
IOUT
4
Test Condition s:
Supply Voltage = 24 V
2
0
0
0.25 0.5 0.75
1
1.25
1.5
IOUT [A]
Doc ID 15209 Rev 3
No PWM
fSW = 30 kHz (slow decay)
23/28
Application information
6.2
L6229Q
Thermal management
In most applications the power dissipation in the IC is the main factor that sets the maximum
current that can be delivered by the device in a safe operating condition. Therefore, it has to
be taken into account very carefully. Besides the available space on the PCB, the right
package should be chosen considering the power dissipation. Heat sinking can be achieved
using copper on the PCB with proper area and thickness.
For instance, using a VFQFPN32L 5 x 5 package the typical Rth(JA) is about 42 °C/W when
mounted on a double-layer FR4 PCB with a dissipating copper area of 0.5 cm2 on the top
side plus 6 cm2 ground layer connected through 18 via holes (9 below the IC).
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L6229Q
7
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 10.
VFQFPN 5 x 5 x 1.0, 32 lead, pitch 0.50
Databook (mm)
Dim.
Min
Typ
Max
A
0.80
0.85
0.95
b
0.18
0.25
0.30
b1
0.165
0.175
0.185
D
4.85
5.00
5.15
D2
3.00
3.10
3.20
D3
1.10
1.20
1.30
E
4.85
5.00
5.15
E2
4.20
4.30
4.40
E3
0.60
0.70
0.80
e
L
0.50
0.30
ddd
Note:
0.40
0.50
0.08
VFQFPN stands for thermally enhanced very thin profile fine pitch quad flat package no
lead. Very thin profile: 0.80 < A < 1.00 mm.
Details of terminal 1 are optional but must be located on the top surface of the package by
using either a mold or marked features.
Doc ID 15209 Rev 3
25/28
Package mechanical data
L6229Q
Figure 25. Package dimensions
26/28
Doc ID 15209 Rev 3
L6229Q
8
Revision history
Revision history
Table 11.
Document revision history
Date
Revision
Changes
25-Nov-2008
1
First release
26-Feb-2009
2
Updated Table 4 on page 5
30-Aug-2010
3
Updated Table 1 on page 1
Doc ID 15209 Rev 3
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L6229Q
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Doc ID 15209 Rev 3
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