L6234

® L6234 THREE PHASE MOTOR DRIVER SUPPLY VOLTAGE FROM 7 TO 52V 5A PEAK CURRENT RDS ON 0.3Ω TYP. VALUE AT 25°C CROSS CONDUCTION PROTECTION TTL COMPATIBLE DRIVER OPERATING FREQUENCY TO 50KHz THERMAL SHUTDOWN INTRINSIC FAST FREE WHEELING DIODES INPUT AND ENABLE FUNCTION FOR EVERY HALF BRIDGE 10V EXTERNAL REFERENCE AVAILABLE DESCRIPTION The L6234 is a triple half bridge to drive a brushless motor. It is realized in Multipower BCD technology which combines isolated DMOS power transistors with CMOS and Bipolar circuits on the same chip. By using mixed technology it has been possible to optimize the logic circuitry and the power stage to achieve the best possible performance. The output DMOS transistors can sustain a very high current due to the fact that the DMOS structure is not affected by the second breakdown efPIN CONNECTION (Top view) POWER DIP (16+2+2) PowerSO20 ORDERING NUMBERS: L6234 (POWER DIP 16+2+2) L6234PD (PowerSO20) fect, the RMS maximum current is practically limited by the dissipation capability of the package. All the logic inputs are TTL, CMOS and µP compatible. Each channel is controlled by two separate logic input. L6234 is available in 20 pin POWER DIP package (16+2+2) and in PowerSO20. OUT1 IN1 EN1 VS GND GND VS EN3 IN3 OUT3 1 2 3 4 5 6 7 8 9 10 D98IN848 20 19 18 17 16 15 14 13 12 11 OUT2 IN2 EN2 SENSE1 GND GND SENSE2 VBOOT VCP VREF GND SENSE1 EN2 IN2 OUT2 OUT1 IN1 EN1 VS GND 1 2 3 4 5 6 7 8 9 10 D94IN129A 20 19 18 17 16 15 14 13 12 11 GND SENSE2 VBOOT Vcp VREF OUT3 IN3 EN3 VS GND POWER DIP (16+2+2) PowerSO20 August 2003 1/10 L6234 BLOCK DIAGRAM 0.22µF 10nF VCP CHARGE PUMP IN1 1µF VREF VBOOT VREF= 10V Vs 7 to 52V TH1 OUT1 EN1 TL1 0.1 µF 100µF 1N4148 IN2 TH2 OUT2 EN2 THERMAL PROTECTION IN3 TL2 SENSE1 TH3 OUT3 EN3 TL3 SENSE2 GND D95IN309A RSENSE 2/10 L6234 THERMAL DATA Symbol Rth j-pin Rth j-amb1 Rth j-amb2 Rth j-case Parameter Thermal Resistance, Junction to Pin Thermal Resistance, Junction to Ambient (see Thermal Characteristics) Thermal Resistance, Junction to Ambient (see Thermal Characteristics) Thermal Resistance Junction-case DIP16+2+2 12 40 50 – PowerSO20 – – – 1.5 Unit °C/W °C/W °C/W °C/W THERMAL CHARACTERISTICS Rth j-pins DIP16+2+2. The thermal resistance is referred to the thermal path from the dissipating region on the top surface of the silicon chip, to the points along the four central pins of the package, at a distance of 1.5 mm away from the stand-offs. Rth j-amb1 If a dissipating surface, thick at least 35 µm, and with a surface similar or bigger than the one shown, is created making use of the printed circuit. Such heatsinking surface is considered on the bottom side of an horizontal PCB (worst case). Rth j-amb2 If the power dissipating pins (the four central ones), as well as the others, have a minimum thermal connection with the external world (very thin strips only) so that the dissipation takes place through still air and through the PCB itself. It is the same situation of point above, without any heatsinking surface created on purpose on the board. Additional data on the PowerDip and the PowerSO20 package can be found in: Application Note AN467: Thermal Characteristics of the PowerDip 20,24 Packages Soldered on 1,2,3 oz. Copper PCB Application Note AN668: A New High Power IC Surface Mount Package: PowerSO20 Power IC Packaging from Insertion to Surface Mounting. Figure 1: Printed Heatsink 3/10 L6234 ABSOLUTE MAXIMUM RATINGS Symbol VS VIN,VEN Ipeak VSENSE Vb VOD fC VREF Ptot Ptot Tstg, Tj Parameter Power Supply Voltage Input Enable Voltage Pulsed Output Current (note 1) Sensing Voltage (DC Voltage) Bootstrap Peak Voltage Differential Output Voltage (between any of the 3 OUT pins) Commutation Frequency Reference Voltage Total Power Dissipation Total Power Dissipation L6234PD Tamb = 70°C L6234 Tamb = 70°C Value 52 – 0.3 to 7 5 -1 to 4 62 60 50 12 2.3 1.6 (*) -40 to 150 Unit V V A V V V KHz V W W °C Storage and Junction Temperature Range Note 1: Pulse width limited only by junction temperature and the transient thermal impedance (*) Mounted on board with minimized copper area RECOMMENDED OPERATING CONDITIONS Symbol VS VOD Iout VSENSE Tj Supply Voltage Peak to Peak Differential Voltage (between any of the 3 OUT pins) DC Output Current Power SO20 (Tamb = 25°C) DC Output Current Power DIP (Tamb = 25°C) with infinite heatsink Sensing Voltage (pulsed tw < 300nsec) Sensing Voltage (DC) Junction Temperature Range Parameter Value 7 to 42 52 4 2.8 -4 to 4 -1 to 1 -40 to 125 Unit V V A A V V °C PIN FUNCTIONS Powerdip 1 20 10 2 19 9 3 18 8 4,7 14 17 11 12 13 5,6 15,16 4/10 PowerSO20 6 5 15 7 4 14 8 3 13 9, 12 19 2 16 17 18 1,10 11,20 Name OUT 1 OUT 2 OUT 3 IN 1 IN 2 IN 3 EN 1 EN 2 EN 3 Vs SENSE2 SENSE1 Vref Vcp VBOOT GND Output of the channels 1/2/3. Function Logic input of channels 1/2/3. A logic HIGH level (when the corresponding EN pin is HIGH) switches ON the upper DMOS Power Transistor, while a logic LOW switches ON the corresponding low side DMOS Power. Enable of the channels 1/2/3. A logic LOW level on this pin switches off both power DMOS of the related channel. Power Supply Voltage. A resistance Rsense connected to this pin provides feedback for motor current control for the bridge 3. A resistance Rsense connected to this pin provides feedback for motor current control for the bridges 1 and 2. Internal Voltage Reference. A capacitor connected from this pin to GND increases the stability of the Power DMOS drive circuit. Bootstrap Oscillator. Oscillator output for the external charge pump. Overvoltage input to drive the upper DMOS Common Ground Terminal. In Powerdip and SO packages these pins are used to dissipate the heat forward the PCB. L6234 ELECTRICAL CHARACTERISTICS (Vs = 42V ; Tj = 25°C unless otherwise specified) Symbol VS Vref IS TS TD Parameter Supply Voltage Reference Voltage Quiescent Supply Current Thermal Shutdown Dead Time Protection 150 300 Test Condition Min. 7 10 6.5 Typ. Max. 52 Unit V V mA °C ns OUTPUT DMOS TRANSISTOR Symbol IDSS RDS (ON) Parameter Leakage Current ON Resistance 0.3 Test Condition Min. Typ. Max. 1 Unit mA Ω SOURCE DRAIN DIODE Symbol VSD TRR Tpr Parameter Forward ON Voltage Reverse Recovery Time Forward Recovery Time IF = 4A Test Condition ISD = 4A; EN = LOW Min. Typ. 1.2 900 200 Max. Unit V ns ns LOGIC LEVELS Symbol VINL, VENL VINH, VENH IINL, IENL IINH, IENH Parameter Input LOW Voltage Input HIGH Voltage Input LOW Current Input HIGH Current VIN,VEN = L VIN,VEN = H 30 Test Condition Min. -0.3 2 Typ. Max. 0.8 7 -10 Unit V V µA µA CIRCUIT DESCRIPTION L6234 is a triple half bridge designed to drive brushless DC motors. Each half bridge has 2 power DMOS transistors with RdsON = 0.3Ω. The 3 half bridges can be controlled independently by means of the 3 inputs IN1, IN2, IN3 and the 3 inputs EN1, EN2, and EN3. An external connection to the 3 common low side DMOS sources is provided to connect a sensing resistor for constant current chopping application. The driving stage and the logic stage are designed to work from 7V to 52V. 5/10 L6234 Figure 1. Quiescent Current vs. Supply Voltage. Iq [m A ] 10 9 8 7 6 5 T j = 1 30 °C T j = 25 °C T j = -4 0 °C Tj = 25°C Figure 2. Normalized Quiescent Current vs. switching frequency. Iq/(Iq@500Hz) 1.75 Tj = 130°C 1.5 T j = -40°C T j = 1 00 °C 1.25 4 3 1 2 1 0 0 8 16 24 V s [V ] 32 40 48 0.75 0 10 20 30 fsw [kHz ] 40 50 60 Figure 3. Typical RDS (ON) vs. Supply Voltage. R D S (O N ) [ Ω ] 0 .7 0 .6 0 .5 0 .4 T j = 2 5 °C Figure 4. Source Drain Forward ON voltage vs. Junction Temperature. VSD [V] 2 1.75 1.5 1.25 1 0.75 T j = 1 3 0 °C 0 .3 0 .2 0 .1 0 T j= - 4 0 ° C 0.5 Iout=4A Io u t = 4 A 0.25 0 -50 0 8 16 24 32 V s [V ] 40 48 -25 0 25 50 Tj [°C ] 75 100 125 150 Figure 5. Typical Diode Forward ON characteristics IS D [A ] 5 T j = 25 °C Figure 6. Reference Voltage vs. Supply Voltage. Vref [V ] 12 4 D M O S (O N ) D M O S (O FF) 10 8 3 6 2 4 T j = 2 5°C 1 2 0 0 0.5 1 V S D [V ] 1.5 2 0 0 10 20 30 V s [V ] 40 50 6/10 L6234 Figure 7. Reference Voltage vs. Junction Temperature. V re f [V ] 11 V s = 5 2V Figure 8. PowerSO-20 Transient Thermal Resistance 10 9 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 T j [ °C ] 75 1 00 1 25 1 50 Vs = 7V V s = 2 4V V s = 1 0V Figure 9. PowerSO-20 Thermal Resistance (Mounted on Aluminium substrate) Figure 10. PowerSO-20 Thermal Resistance (Mounted on FR4 monolayer substrate) Figure 11. PowerSO-20: with external heatsink Figure 12. Thermal Impedance of PowerSO-20 and standard SO20 7/10 L6234 DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T 10 0.8 5.8 0 15.5 10.9 0 0.4 0.23 15.8 9.4 13.9 1.27 11.43 11.1 2.9 6.2 0.1 15.9 1.1 1.1 0.031 8˚ (typ.) 8˚ (max.) 0.394 0.228 0.000 0.610 0.429 0.1 mm MIN. TYP. MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 0.000 0.016 0.009 0.622 0.370 0.547 0.050 0.450 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.004 MIN. inch TYP. MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570 Weight: 1.9gr OUTLINE AND MECHANICAL DATA (1) “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions: “E”, “G” and “a3”. PowerSO20 N N a2 b e A R c DETAIL B a1 E DETAIL A DETAIL A e3 H lead D a3 DETAIL B 20 11 Gage Plane 0.35 slug -C- S E2 T E1 BOTTOM VIEW L SEATING PLANE G C (COPLANARITY) E3 1 10 h x 45 PSO20MEC D1 0056635 8/10 L6234 mm MIN. a1 B b b1 D E e e3 F I L Z 3.30 1.27 8.80 2.54 22.86 7.10 5.10 0.130 0.38 0.51 0.85 0.50 0.50 24.80 0.346 0.100 0.900 0.280 0.201 0.015 1.40 TYP. MAX. MIN. 0.020 0.033 0.020 0.020 0.976 0.055 inch TYP. MAX. DIM. OUTLINE AND MECHANICAL DATA Powerdip 20 0.050 9/10 L6234 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 2003 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 10/10