L6374

L6374 INDUSTRIAL QUAD LINE DRIVER ADVANCE DATA FOUR INDEPENDENT LINE DRIVERS WITH 100 mA UP TO 35V OUTPUTS INPUT SIGNALS BETWEEN -7V AND +35V, WITH PRESETTABLE THRESHOLD PUSH-PULL OUTPUTS WITH THREE STATE CONTROL AND TRUE ZERO CURRENT BETWEEN VS AND GROUND CURRENT LIMITING ON EACH OUTPUT EFFECTIVE IN THE FULL ”GROUND TO VS” OUTPUT VOLTAGE RANGE OUTPUT VOLTAGE CLAMP TO VS AND TO GROUND OVERTEMPERATURE AND UNDERVOLTAGE PROTECTIONS DIAGNOSTIC FOR OVERTEMPERATURE, UNDERVOLTAGE AND OVERCURRENT PRESETTABLE DELAY FOR OVERCURRENT DIAGNOSTIC HIGH SPEED OPERATION: UP TO 300kHz WITH 35V SWING BLOCK DIAGRAM POWERDIP 16+2+2 SO 16+2+2 ORDERING NUMBER: L6374DP (POWERDIP 16+2+2) L6374FP (SO 16+2+2) DESCRIPTION The L6374 is especially designed to be used as a line driver in industrial control systems based on the 24V signal levels (IEC1131, 24VDC). December 1994 1/13 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L6374 ABSOLUTE MAXIMUM RATINGS Symbol VS Vilog Iilog Ii Vi Iout 7, 8, 9, 10 3, 4, 17, 18 Pin 1 12, 13 Supply Voltage (DC) Logic Input Voltage (DC) Logic Input forced current, per pin Channel Input Current (forced) Channel Input Voltage Output Current (forced, apart from inductive load) Output Current (forced, apart from inductive load) same tW < 10ms Output Voltage (forced, not resulting from an inductive kick) 11 14 13 Setting pin forced current Setting pin forced voltage External voltage Externally forced current Voltage on the delay capacitor, externally forced Ambient temperature, operating range Junction temperature, operating range (see Overtemperature Protection) Storage temperature Parameter Supply Voltage (t W < 10ms) Value 50 40 -0.3 to 7 ±1 ±2 - 7 to 35 ± 100 ±1 -0.3 to VS +0.3 ±1 -0.3 to 5 -0.3 to 35 -10 to 10 -0.3 to 4.5 -25 to 85 -25 to 125 -55 to 150 Unit V V V mA mA V mA A V mA V V mA V °C °C °C Vout Iset Vset Vdiag Idiag VC3 Top Tj Tstg PIN CONNECTION (Top view) 2/13 L6374 ELECTRICAL CHARACTERISTICS (VS = 24V; Tj = -25 to 125°C; unless otherwise specified.) DC OPERATION Symbol VS Vsh Hys1 Iqsc Vref Iref Vth Vil 7, 8, 9, 10 11 Pin 1 Parameter Supply Voltage UV UpperThreshold UV Hysteresis Quiescent Current Input Comparators Reference Voltage Sink/Source Current on Reference Pin Comparator Threshold with External Bias Input Low Level Outputs Open Reference pin Floating Vref = 0V Vref = 5V VS = 9 to 12V VS = 12 to 35V VREF Externally Biased Pin VREF Floating Vih Input High Level VREF Externally Biased Pin VREF Floating Vi Ibias Hys2 Th HT Isc Von Input Voltage (Operative Range) Input Bias Current Input Comparators Hysteresis OVT Upper Threshold OVT Hysteresis 3, 4, Current Limit 17, 18 Internal Voltage Drop @ Rated Current Vi = -7 to VS; Vout = 0 to VS; Iout = ± 100mA; Sourced @ High Output, Sunk @ Low Output Tj = 125°C Same, Tj = 25°C Ilkg Vin Iin Idlkg Vdiag 14 12 Output 3-State Leakage Current Push-Pull Mode Request 3-State Mode Request Input Current Diagnostic Output Leakage Diagnostic Output Voltage Drop Vi = 0V Diagnostic Off; Vdiag = 24V Idiag =5mA 200 Vout = 0 to VS -25 -0.2 2 10 110 0 < Vi < VS Vi = -7V See Analog Inputs Sections 1.05 -30 10 -0.2 -0.2 -7 -7 VREF +0.2 2 -7 -1 -1 100 -0.5 200 170 20 200 400 300 600 Test Condition Min. 10.8 9 250 450 3 1.25 -20 20 Typ. Max. 35 10.8 650 5 1.35 -10 30 2.0 5.0 VREF -0.2 0.8 35 35 35 1 -0.1 350 Unit V V mV mA V µA µA V V V V V V V µA mA mV °C °C mA mV 250 400 25 0.8 5.5 25 5 500 mV µA V V µA µA mV AC OPERATION (VS = 10.8 to 35V; Tj = -25 to 125°C; Iout = 100mA; unless otherwise specified; see switching waveforms diagrams) Symbol tdr tdf tr tf Pin Parameter R l to VS R l to ground R l to VS 3, 4, Rise Time 17, 18 Fall Time R l to ground R l to VS R l to ground R l to VS Test Condition R l to ground Min. Typ. 1000 500 500 1000 120 120 150 150 Max. 1500 1000 1000 1500 250 250 300 300 Unit ns ns ns ns ns ns ns ns 7 to 4 Delay Time on Rising Edge 8 to 3 9 to18 10to17 Delay Time on Falling Edge 3/13 L6374 THERMAL DATA Symbol R th j-pin R th j-amb1 R th j-amb2 Parameter Thermal Resistance, Junction to Pin Thermal Resistance, Junction to Ambient (see Thermal Characteristics) Thermal Resistance, Junction to Ambient (see Thermal Characteristics) DIP20 12 40 50 SO20 17 65 80 Unit °C/W °C/W °C/W THERMAL CHARACTERISTICS Rth j-pins POWERDIP. The thermal resistance is referred to the thermal path from the dissipating region on the top surface of the silicon chip, to the points along the four central pins of the package, at a distance of 1.5 mm away from the stand-offs. SO. Similarly, the reference point is the knee on the four central pins, where the pins are upwardly bent and the soldering joint with the PCB footprint can be made. Rth j-amb1 If a dissipating surface, thick at least 35 µm, and with a surface similar or bigger than the one shown, is created making use of the printed circuit. Figure 1: Printed Heatsink Such heatsinking surface is considered on the bottom side of an horizontal PCB (worst case). Rth j-amb2 If the power dissipating pins (the four central ones), as well as the others, have a minimum thermal connection with the external world (very thin strips only) so that the dissipation takes place through still air and through the PCB itself. It is the same situation of point above, without any heatsinking surface created on purpose on the board. Additional data for the PowerDip package can be found in: Application Note 9030: Thermal Characteristics of the PowerDip 20,24 Packages Soldered on 1,2,3 oz. Copper PCB 4/13 L6374 OVERTEMPERATURE PROTECTION (OVT) If the chip temperature exceeds T h (measured in a central position in the chip) the chip deactivates itself. The following actions are taken: - all the output stages are forced in the ”three state” condition, i.e. are disconnected from the output pins; only the clamping diodes at the outputs remain active; - the signal Diag is activated (active low). Normal operation is resumed as soon as (typically after some seconds) the chip temperature monitored goes back below Th -HT. The different upper and lower thresholds with hysteretic behavior, assure that no intermittent conditions can be generated. UNDERVOLTAGE PROTECTION (UV) The supply voltage is expected to range from 11V to 35V, even if its reference value is considered to be 24V. In this range the L6374 operates correctly. Below 10.8V the overall system has to be considered not reliable. Consequently the supply voltage is monitored continuously and a signal, called UV, is internally generated and used. The signal is ”on” as long as the supply voltage does not reach the upper internal threshold of the Vs comparator (called Vsh). The UV signal disappears above Vsh. Once the UV signal has been removed, the supply voltage must decrease below the lower threshold (i.e. below Vsh -Hys1) before it is turned on again. The hysteresis Hys1 is provided to prevent intermittent operation of the device at low supply voltages that may have a superimposed ripple around the average value. The UV signal inhibits the outputs, putting them in three-state, but has no effect on the creation of the reference voltages for the internal comparators, nor on the continuous operation of the charge-pump circuits. DIAGNOSTIC LOGIC The situations that are monitored and signalled with the Diag output pin are: - current limit (OVC) in action; there are 8 individual current limiting circuits, two per each output, i.e. one per every output transistor; they limit the current that can be either sourced or sunk from each output, to a typical value of 150mA, equal for all of them; - undervoltage protection (UV); - overtemperature protection (OVP); The diagnostic signal is transmitted via an open drain output (for ease of wired-or connection of several such signals) and a low level represents the presence of at least one of the monitored conditions, mentioned above. PROGRAMMABLE DELAY The current limiting circuits can be requested to perform even in absence of a real fault condition, for a short period, if the load is of capacitive nature or if it is a filament lamp (that exhibits a very low resistance during the initial heating phase). To avoid the forwarding of misleading, short diagnostic pulses in coincidence with the intervention of the current limiting circuits when operating on capacitive loads, a delay of about 5µs is inserted on the signal path, between the ”OR” of the current limit signals and its use as external diagnostic. It takes about 1µs to charge (or discharge) by 24V a capacitor of 5nF with a current of 120mA . To implement longer delays (from the intervention of one of the current limiting circuits to the activation of the diagnostic) an external capacitor can be connected between pin C3 and ground (pin C3 is otherwise left open). The delay shall then be determined by the ratio of about 10 pF/µs, using the value of the capacitance connected to the pin. ANALOG INPUTS (I1,I2,I3,I4) The input stage of each channel is a high impedence comparator with built-in hysteresis (200mV) for high noise immunity. Each comparator has one input connected to all the others and tied to a common pin Ref (Pin 11). If this pin is left floating an internal precise band gap voltage reference (1.25V) is applied, otherwise these inputs can be externally programmed by connecting an external voltage source (from 0 to 5V) and the current on this pin is internally limited to ±20µA. The other input pin of each comparator can swing from -7 to 35V. For this reason it has been implemented the structure shown in Figure 2 and the device can also be used as line receiver. When the input voltage is negative, the current is internally limited by a 15kΩ resistor as shown in Figure 2. High and low input thresholds can be obtained by adding and subtracting half of the hysteresis to the voltage of pin Ref (see Figure 3). Figure 2: Equivalent input circuit 5/13 L6374 Figure 3: Input Comparator Threshold Vout Hys2 2 Hys2 2 Vs Vref D94IN073 Vi 3 STATE / PUSH-PULL INPUT The input 3st/Pp is instead intended for a digital incoming signal. It has an internal threshold set at 1.26V; an internal bias circuit (10µA typical) simulates a high level (three-state) if the pin is disconnected. THE SWITCHING OF THE OUTPUT STAGE The cross conduction of the two transistors of an output stage of the L6374 would be significantly noisy, because the transistors here can carry peak currents in excess of 100mA, and even more in the few nanoseconds before the current limiting circuits are really effective. Figure 4: VS = 35V, 350Ω connected to VS/2. Consequently the device has been designed so as to avoid such cross conduction. At every switching transition, first of all the transistor in conduction is turned off. Then, after a safe interval of around 200ns, the other transistor is turned on. When analyzing the switching cycle, and the associated switching times, it is useful to identify some subsequent phases: - delay from the input pin to the output reaction; - off transition in the output stage; - dead time; - on transition in the output stage. Figure 4 helps understand such sequence. In 6/13 L6374 fact, with a purely resistive load connected to Vs/2 no parasitic elements interfere significantly. The waveform can be significantly less easy to interpret if the load has not the perfect symmetry of that case, as showed below. For instance, it is enough to connect the resistive load to ground, or to Vs – as figure 5 and 6 – show to hide some of the switching phases described. If the load is connected to ground, the waveform stays stuck to ground as long as the output stage is in high impedance; viceversa when the load is connected to Vs the waveform will linger close to the supply voltage as long as possible. If an output load made of an inductor and a resistor in series is used, the inductive kick at the beginning of every output transition generates the equivalent effect of an ”anticipated” switching when the inductor can discharge; while the switching looks ”delayed” if the output transition tends to initiate a charging phase (see figure 7). With a load almost free from parasitic elements, the waveforms resemble the ones of the purely Figure 5: VS = 35V, 350Ω connected to ground. resistive cases. With a real, more composite load, the effect of the inductive kick in comparison to the resistive load, would be more apparent. With a capacitor and a resistor in parallel as a load, another type of waveform can be seen (reported in figure 8). As long as the output stage stays in the transient high impedance state, the output voltage will follow the classic exponential law of an RC relaxation. As soon as the other transistor is switched on and takes charge, the waveform is quickly forcibly brought to its steady state value. From the above it is possible to see how the switching times, inherently very fast, of the output stages, may be difficult to identify in a waveform if the output load is not accurately taken into consideration. Figure 9 show typical switching waveform for inputs and outputs. 7/13 L6374 Figure 6. VS = 35V, 350Ω connected to VS. Figure 7. VS = 35V, 350Ω & 1mH connected to ground. 8/13 L6374 Figure 8: VS = 35V, 350Ω || 1nF connected to ground. Figure 9: Switching Waveforms. In 50% 50% tdr Out t df t 90% 90% 10% tr tf 10% D94IN074 t 9/13 L6374 APPLICATION NOTE It is recommended not to leave the Ref pin (pin 11) floating: if not used with an external voltage reference, it is better to connect an external capacitor (of at least 10nF) between this pin and ground. This capacitor filters the voltage reference against voltage spikes that can be generated by the commutation of the output stages. This is very common using capacitive loads: in fact, the initial transient of such loads behaves like a short circuit, so the current flowing through the outputs presents very high spikes. Moreover, if the device is used as a line receiver. (i.e. the input signals can go below ground) it is required not to leave the Ref pin (pin 11) floating: in this case, the pin can be connected to ground or to a fixed external voltage reference. 10/13 L6374 DIP20 PACKAGE MECHANICAL DATA DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.30 1.27 8.80 2.54 22.86 7.10 5.10 0.130 0.050 0.38 0.51 0.85 0.50 0.50 24.80 0.346 0.100 0.900 0.280 0.201 0.015 1.40 mm TYP. MAX. MIN. 0.020 0.033 0.020 0.020 0.976 0.055 inch TYP. MAX. 11/13 L6374 SO20 PACKAGE MECHANICAL DATA DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.4 0.5 12.6 10 1.27 11.43 7.6 1.27 0.75 8 (max.) 0.291 0.020 13.0 10.65 0.35 0.23 0.5 45 (typ.) 0.496 0.394 0.050 0.450 0.299 0.050 0.030 0.512 0.419 0.1 mm TYP. MAX. 2.65 0.3 2.45 0.49 0.32 0.014 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.012 0.096 0.019 0.013 12/13 L6374 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. © 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 13/13