L6391
High voltage high and low-side driver
Datasheet - production data
Applications
Motor driver for home appliances, factory
automation, industrial drives and fans
HID ballasts, power supply units
Description
The L6391 is a high voltage device manufactured
with the BCD™ “OFF-LINE” technology. It is a
single-chip half-bridge gate driver for N-channel
power MOSFET or IGBT.
Features
High voltage rail up to 600 V
dV/dt immunity ± 50 V/nsec in full temperature
range
Driver current capability:
– 290 mA source
– 430 mA sink
Switching times 75/35 nsec rise/fall with 1 nF
load
The high-side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing the microcontroller/DSP.
An integrated comparator is available for
protections against overcurrent, overtemperature,
etc.
3.3 V, 5 V TTL/CMOS inputs with hysteresis
Integrated bootstrap diode
Comparator for fault protections
Smart shutdown function
Adjustable deadtime
Interlocking function
Compact and simplified layout
Bill of material reduction
Effective fault protection
Flexible, easy and fast design
September 2015
This is information on a product in full production.
DocID17892 Rev 3
1/23
www.st.com
Contents
L6391
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
10
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SO-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
11
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
DocID17892 Rev 3
L6391
1
Block diagram
Block diagram
Figure 1. Block diagram
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DocID17892 Rev 3
3/23
23
Pin connection
2
L6391
Pin connection
'7
HVG
1&
gate driver outputs OFF
*1'
(HALF-BRIDGE TRI-STATE)
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DEADTIME
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INT
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NG
Figure 2. Pin connection (top view)
DTHL
gate driver outputs OFF
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Table 1. Pin description
Pin
number
Pin name
Type
1
LIN
I
2
SD/OD (1)
I/O
3
HIN
I
High-side driver logic input (active high)
4
VCC
P
Lower section supply voltage
5
DT
I
Deadtime setting
6
NC
7
GND
P
Ground
8
CP-
I
Comparator negative input
9
CP+
I
Comparator positive input
10
LVG(1)
O
Low-side driver output
11
NC
12
OUT
(1)
Function
Low-side driver logic input (active low)
Shutdown logic input (active low)/open-drain
comparator output
Not connected
Not connected
P
High-side (floating) common voltage
13
HVG
O
High-side driver output
14
BOOT
P
Bootstrapped supply voltage
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/23
DocID17892 Rev 3
L6391
3
Truth table
Truth table
Table 2. Truth table
Input
Output
SD
LIN
HIN
LVG
HVG
L
X(1)
X(1)
L
L
H
H
L
L
L
H
L
H
L
L
H
L
L
H
L
H
H
H
L
H
1. X: don't care.
DocID17892 Rev 3
5/23
23
Electrical data
L6391
4
Electrical data
4.1
Absolute maximum ratings
Table 3. Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min.
Max.
Vcc
Supply voltage
-0.3
21
V
Vout
Output voltage
Vboot - 21
Vboot + 0.3
V
Vboot
Bootstrap voltage
-0.3
620
V
Vhvg
High-side gate output voltage
Vout - 0.3
Vboot + 0.3
V
Vlvg
Low-side gate output voltage
-0.3
Vcc + 0.3
V
Vcp-
Comparator negative input voltage
-0.3
Vcc + 0.3
V
Vcp+
Comparator positive input voltage
-0.3
Vcc + 0.3
V
Vi
Logic input voltage
-0.3
15
V
VOD
Open-drain voltage
-0.3
15
V
50
V/ns
dvout / dt Allowed output slew rate
4.2
Ptot
Total power dissipation (TA = 25 °C)
800
mW
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
ESD
Human body model
-50
2
kV
Thermal data
Table 4. Thermal data
Symbol
Rth(JA)
6/23
Parameter
Thermal resistance junction to ambient
DocID17892 Rev 3
SO-14
Unit
120
°C/W
L6391
4.3
Electrical data
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Pin
Vcc
4
VBO(1)
Parameter
Test conditions
Min.
Max.
Unit
Supply voltage
12.5
20
V
14 - 12 Floating supply voltage
12.4
20
V
580
V
(2)
Vout
12
DC output voltage
VCP-
8
Comparator negative
input voltage
VCP+ [2.5 V]
VCC(3)
V
VCP+
9
Comparator positive
input voltage
VCP- [2.5 V]
VCC(3)
V
fsw
Switching frequency
HVG, LVG load CL = 1 nF
800
kHz
TJ
Junction temperature
125
°C
-9
-40
1. VBO = VBOOT - VOUT.
2. LVG off. Vcc = 12.5 V. Logic is operational if VBOOT > 5 V.
3. At least one of the comparator's inputs must be lower than 2.5 V to guarantee proper operation.
DocID17892 Rev 3
7/23
23
Electrical characteristics
L6391
5
Electrical characteristics
5.1
AC operation
Table 6. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol
ton
toff
tsd
Pin
Parameter
Test conditions
High/low-side driver turn-on
1 vs. 10 propagation delay
3 vs. 13 High/low-side driver turn-off
propagation delay
2 vs. 10, Shutdown to high/low-side
13
driver propagation delay
tisd
Comparator triggering to
high/low-side driver turn-off
propagation delay
MT
Delay matching, HS and LS
turn-on/off
DT
5
Matching deadtime(2)
MDT
tr
tf
Deadtime setting range(1)
10,13
Vout = 0 V
Vboot = Vcc
CL = 1 nF
Vi = 0 to 3.3 V
see Figure 3
50
125
200
ns
50
125
200
ns
50
125
200
ns
200
250
ns
30
ns
Measured applying a voltage step from
0 V to 3.3 V to pin CP+; CP- = 0.5 V
RDT = 0 , CL = 1 nF
0.1
RDT = 37 k, CL = 1 nF, CDT = 100 nF
0.48
0.6
0.72
µs
RDT = 136 k, CL = 1 nF, CDT = 100 nF 1.35
1.6
1.85
µs
RDT = 260 k, CL = 1 nF, CDT = 100 nF
3.0
3.4
µs
RDT = 0 , CL = 1 nF
80
ns
RDT = 37 k, CL = 1 nF, CDT = 100 nF
120
ns
RDT = 136 k, CL = 1 nF, CDT = 100 nF
250
ns
RDT = 260 k, CL = 1 nF, CDT = 100 nF
400
ns
2.6
0.18 0.25
µs
Rise time
CL = 1 nF
75
120
ns
Fall time
CL = 1 nF
35
70
ns
1. See Figure 4.
2. MDT = | DTLH - DTHL | (see Figure 5 on page 12).
8/23
Min. Typ. Max. Unit
DocID17892 Rev 3
L6391
Electrical characteristics
Figure 3. Timing
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Figure 4. Typical deadtime vs. DT resistor value
3.5
Approximated formula for
Rdt calculation (typ.):
3
DT (us)
2.5
Ω = 92.2 · DT[μs] - 16.6
Rdt[kΩ]
2
1.5
1
0.5
0
0
50
100
150
Rdt (kOhm)
DocID17892 Rev 3
200
250
300
AM16763v1
9/23
23
Electrical characteristics
5.2
L6391
DC operation
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C)
Symbol
Pin
Min.
Typ.
Vcc UV hysteresis
1.2
1.5
1.8
V
Vcc_thON
Vcc UV turn-ON threshold
11.5
12
12.5
V
Vcc_thOFF
Vcc UV turn-OFF threshold
10
10.5
11
V
Undervoltage quiescent supply
current
Vcc = 9.5 V
SD = 5 V; LIN = 5 V;
HIN = GND; RDT = 0 ;
CP+ = GND; CP- = 5 V
100
150
A
Quiescent current
Vcc = 15 V
SD = 5 V; LIN = 5 V;
HIN = GND; RDT = 0 ;
CP+ = GND; CP- = 5 V
500
1000
A
Vcc_hys
Iqccu
4
Iqcc
Parameter
Test conditions
Max. Unit
Bootstrapped supply voltage section(1)
VBO_hys
VBO UV hysteresis
1.2
1.5
1.8
V
VBO_thON
VBO UV turn-ON threshold
10.6
11.5
12.4
V
VBO_thOFF
VBO UV turn-OFF threshold
9.1
10
10.9
V
VBO = 9 V
SD = 5 V; LIN and
HIN = 5 V; RDT = 0 ;
CP+ = GND; CP- = 5 V
70
110
A
VBO = 15 V
SD = 5 V; LIN and
HIN = 5 V; RDT = 0 ;
CP+ = GND; CP- = 5 V
200
240
A
10
A
IQBOU
Undervoltage VBO quiescent
14 - 12 current
IQBO
VBO quiescent current
ILK
High voltage leakage current
Bootstrap driver on resistance
RDS(on)
Vhvg = Vout = Vboot = 600 V
(2)
LVG ON
120
W
Driving buffer section
Iso
10, 13
Isi
High/low-side source short-circuit
VIN = Vih (tp < 10 s)
current
200
290
mA
High/low-side sink short-circuit
current
250
430
mA
VIN = Vil (tp < 10 s)
Logic inputs
Vil
Vih
Vil_S
10/23
1, 2, 3
1, 3
Low level logic threshold
0.8
1.1
V
High level logic threshold voltage
1.9
2.25
V
0.8
V
Single input voltage
LIN and HIN connected
together and floating
DocID17892 Rev 3
L6391
Electrical characteristics
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C) (continued)
Symbol
IHINh
IHINl
ILINl
ILINh
ISDh
ISDl
Pin
3
1
2
Parameter
Test conditions
HIN logic “1” input bias current
HIN = 15 V
HIN logic “0” input bias current
HIN = 0 V
LIN logic “0” input bias current
LIN = 0 V
LIN logic “1” input bias current
LIN = 15 V
SD logic “1” input bias current
SD = 15 V
SD logic “0” input bias current
SD = 0 V
Min.
Typ.
Max. Unit
110
175
260
A
1
A
20
A
1
A
100
A
1
A
3
6
10
40
1. VBO = VBOOT - VOUT.
2. RDS(on) is tested in the following way: RDS(on) = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC,VBOOT1) - I2(VCC,VBOOT2)]
where I1 is pin 14 current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2.
Table 8. Sense comparator(1) (VCC = 15 V, TJ = +25 °C)
Symbol
Pin
Parameter
Vio
8, 9
Input offset voltage
Iib
8, 9
Input bias current
Vol
2
td_comp
SR
2
Test conditions
Min.
Typ.
Max.
Unit
15
mV
VCP+ = 1 V, VCP - = 0.5 V
1
A
Open-drain low level
output voltage
Iod = - 3 mA VCP+ = 1 V;
VCP- = 0.5 V;
0.5
V
Comparator delay
Rpull = 100 k to 5 V on
SD/OD pin; VCP- = 0.5 V;
voltage step on CP+ = 0 to
3.3 V
90
130
ns
Slew rate
CL = 180 pF; Rpu = 5 k
60
-15
V/s
1. Comparator is disabled when Vcc is in UVLO condition.
DocID17892 Rev 3
11/23
23
Waveform definitions
6
L6391
Waveform definitions
Figure 5. Deadtime and interlocking waveform definitions
OC K
ING
LVG
IINT
ER L
ER L
OC K
HIN
INT
CONTROL SIGNAL EDGE
OVERLAPPED:
INTERLOCKING + DEADTIME
ING
LIN
DTHL
DTLH
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNAL EDGE
SYNCHRONOUS (*):
DEADTIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNAL EDGE
NOT OVERLAPPED,
BUT INSIDE THE DEADTIME:
DEADTIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNAL EDGE
NOT OVERLAPPED,
OUTSIDE THE DEADTIME:
DIRECT DRIVING
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected togheter and driven by just one control signal
12/23
DocID17892 Rev 3
L6391
7
Smart shutdown function
Smart shutdown function
The L6391 device integrates a comparator committed to the fault sensing function. Both
comparator's inputs are available on pins 8 and 9. For example, applying a voltage
reference to CP- and connecting the CP+ to an external shunt resistor, a simple overcurrent
detection function can be implemented.
The output signal of the comparator is fed to an integrated MOSFET with the open-drain
output available on the pin 2, shared with the SD input. When the comparator triggers, the
device is set in shutdown state and both its outputs are set to low level leaving the halfbridge in tristate.
Figure 6. Smart shutdown timing waveforms
CP-
CP+
HIN/LIN
PROTECTION
HVG/LVG
SD/OD
open-drain gate
(internal)
disable time
Fast shutdown
:
the driver outputs are set in SD state immediately after the comparator
triggering even if the SD signal has not yet reached the lower input threshold
An approximation of the disable time is given by:
SHUTDOWN CIRCUIT
VBIAS
where:
RSD
SD/OD
FROM/TO
CONTROLLER
CSD
RON_OD
SMART
SD
LOGIC
RPD_SD
AM16755v1
DocID17892 Rev 3
13/23
23
Smart shutdown function
L6391
In common overcurrent protection architectures, the comparator output is usually connected
to the SD input and an RC network is connected to this SD/OD line in order to provide
a monostable circuit, which implements a protection time following the fault condition.
Differently from the common fault detection systems, the L6391 smart shutdown
architecture allows immediate turn-off of the output gate driver in case of fault, by minimizing
the propagation delay between the fault detection event and the current output switch-off. In
fact the time delay between the fault and the output turn-off is no longer dependent on the
RC value of the external network connected to the SD/OD pin. In the smart shutdown
circuitry, the fault signal has a preferential path which directly switches off the outputs after
the comparator triggering. At the same time, the internal logic turns on the open-drain output
and holds it on until the SD voltage goes below the SD logic input lower threshold. When
such threshold is reached, the open-drain output is turned off, allowing the external pull-up
to recharge the capacitor. The driver outputs restart following the input pins as soon as the
voltage at the SD/OD pin reaches the higher threshold of the SD logic input. The smart
shutdown system gives the possibility to increase the time constant of the external RC
network (that determines the disable time after the fault event) up to very large values
without increasing the delay time of the protection.
Any external signal provided to the SD pin is not latched and can be used as control signal
in order to perform, for instance, PWM chopping through this pin. In fact when a PWM signal
is applied to the SD input and the logic inputs of the gate driver are stable, the outputs
switch from the low level to the state defined by the logic inputs and vice versa.
In some applications, it may be useful to latch the driver in the shutdown condition for an
arbitrary time, until the controller decides to reset it to normal operation. This may, for
example, be achieved by a circuit as the one shown in Figure 7. When the open-drain starts
pulling down the SD/OD pin, the external latch turns on and keeps the pin to GND,
preventing it from being pulled up again once the SD logic input lower threshold is reached
and the internal open-drain turns off. One pin of the controller is used to release the external
latch, and one to externally force a shutdown condition and also to read the status of the
SD/OD pin.
Figure 7. Protection latching circuit
HV BUS
VBOOT
HIN
LIN
L6391
HVG
GND
DT
R1
9*R
SD/OD
VDD
R2
R
SD_force
VDD
GND
OUT
LVG
SD/OD
CP+
C1
OPOUT
L639x
VCC
VCC
L639x
μC
+
+
VCC
-
C2
SD/OD
C3
VBIAS
CP-
R3
2*R
SD_sense
C1: disable time setting capacitor
C2, C3: small noise filtering capacitors
AM16756v1
In applications using only one L6391 for the protection of different legs (such as a singleshunt inverter, for example), the resistor divider, shown in Figure 8, can be implemented.
This simple network allows the SD pins of the other devices to reach a voltage lower than
L6391 Vil, so that each device can get its low logic level regardless of part to part variations
of the thresholds.
14/23
DocID17892 Rev 3
L6391
Smart shutdown function
Figure 8. SD level shifting circuit
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DocID17892 Rev 3
15/23
23
16/23
DocID17892 Rev 3
FROM /TO
CONTROLLER
VBIAS
7
5
DT
GND
2
SD/OD
1
LIN
FROM CONTROLLER
4
3
VCC
HIN
VCC
5V
UV
DETECTION
SMART
SD
from LVG
TIME
DEAD
SHOOT
THROUGH
PREVENTION
LOGIC
BOOTSTRAP DRIVER
COMPARATOR
LEVEL
SHIFTER
-
+
5V
UV
DETECTION
FLOATING STRUCTURE
R
S
VC C
12
13
8
9
10
LVG
DRIVER
HVG
DRIVER
14
CP-
CP+
LVG
OUT
HVG
BOOT
VBIAS
H.V.
TO LOAD
Cboot
8
FROM CONTROLLER
+
Typical application diagram
L6391
Typical application diagram
Figure 9. Application diagram
AM02458v1
L6391
9
Bootstrap driver
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is usually
accomplished by a high voltage fast recovery diode (Figure 10). In the L6391 device
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with diode in series, as shown
in Figure 11. An internal charge pump (Figure 11) provides the DMOS driving voltage.
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Q gate
C EXT = -------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
Equation 2
C BOOT >>>C EXT
if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop is 300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has also to take into account
the leakage and quiescent losses.
HVG steady-state consumption is lower than 240 A, so if HVG TON is 5 ms, CBOOT has to
supply CEXT with 1.2 C. This charge on a 1 F capacitor means a voltage drop of 1.2 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDS(on) (typical value:
120 ). At low frequency this drop can be neglected. Anyway, the rise of frequency has to
take into account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
Q gate
V drop = I ch arg e R DS on V drop = ------------------R DS on
T ch arg e
where Qgate is the gate charge of the external power MOS, RDS(on) is the on resistance of
the bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor.
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Bootstrap driver
L6391
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact:
Equation 4
30nC
V drop = --------------- 120 0.7V
5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 10. Bootstrap driver with high voltage fast recovery diode
DBOOT
VCC
BOOT
H.V.
HVG
CBOOT
OUT
TO LOAD
LVG
Figure 11. Bootstrap driver with internal charge pump
BOOT
VCC
H.V.
HVG
CBOOT
OUT
TO LOAD
LVG
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Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
SO-14 package information
Figure 12. SO-14 package outline
0016019_E
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Package information
L6391
Table 9. SO-14 package mechanical data
Dimensions (mm )
Symbol
Min.
Typ.
Max.
A
1.35
1.75
A1
0.10
0.25
A2
1.10
1.65
B
0.33
0.51
C
0.19
0.25
D
8.55
8.75
E
3.80
4.00
e
1.27
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
K
0
8
e
0.40
ddd
0.10
Figure 13. SO-14 footprint
".
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Order codes
Order codes
Table 10. Order codes
Order code
Package
Packaging
L6391D
SO-14
Tube
L6391DTR
SO-14
Tape and reel
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Revision history
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L6391
Revision history
Table 11. Document revision history
Date
Revision
14-Dec-2010
1
First release.
2
Added HBM parameter to Table 3.
Added IQBO max. value to Table 7.
Changed Vil and Vih min. and max. values in Table 7.
Added note to Table 8.
Updated Section 7 and Section .
Changed Figure 6 and added Figure 7 and Figure 8.
Updated SO-14 mechanical data.
Updated DIP-14 mechanical data.
3
Removed DIP-14 package from the entire document.
Updated Table 4 on page 6 (updated Rth(JA) value).
Moved Table 10 on page 21 (moved from page 1 to page 21, updated
titles.
Updated Table 3 on page 6 (updated ESD parameter and value).
Updated note 1.and 2. below Table 7 on page 10 (minor
modifications, replaced VCBOOTx by VBOOTx ).
Added Figure 13 on page 20.
Updated cross-references throughout document.
Minor modifications throughout document.
10-May-2013
11-Sep-2015
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Changes
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