L6452_06

L6452 Dual 13x16 Matrix Head Ink Jet Driver Features ■ ■ ■ ■ ■ ■ ■ DRIVES TWO 13X16 MATRIX HEADS HEAD TEMPERATURE SENSING POWER UP SYSTEM ELECTRICAL NOZZLE CHECK 8 BIT A/D 5 BIT D/A ± 4KV ESD PROTECTED OUTPUTS PQFP100 Description L6452 is a device designed to drive two 13x16 matrix ink jet print heads in printer applications. The output stage is able to source simultaneously 400 mA on each of the 16 power lines (columns) with a duty cycle of 33% in normal printing and 66% in head pre-heating. On the address lines (rows), the load is only capacitive (MOS FET driving capability). The driver can control two print heads, but only one is active at a time. The address scanning counter is included and can be disabled to allow a different scanning scheme. In order to avoid output activation during the supply transient, an internal power-up system is implemented. As supporting function, L6452 is capable of sensing the head silicon temperature and to electrically check each nozzle. The device protection. is also integrating a thermal Order codes Part number E-L6452 L6452DIE8 Op. Temp range, °C 0 to 70 0 to 70 Package PQFP100 DIE Packing Tray -- February 2006 Rev 2 1/22 www.st.com 22 Contents L6452 Contents 1 2 3 Block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 3.2 3.3 3.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Counter Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Decoder Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Print Head Temperature Control Part . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Print Head Block Diagram (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2/22 L6452 Block diagrams 1 Figure 1. Block diagrams Block diagram POWER & LOGICAL SUPPLIES PRINT HEAD DRIVER 16 POWER LINES CONTROL LINES 13 ADDRESS LINES CHANNEL A PRINT HEAD A 13 ADDRESS LINES CHANNEL B PRINT HEAD B A/D & PRINT HEAD TEMPERATURE CONTROL LINES PRINT HEAD TEMPERATURE CONTROL ANALOG INPUTS D97IN523 Figure 2. Block Diagram: Power Line Output Stage. Va 1.25mA DATA BIT 0 1 0 OUTPUT0 DATA BIT 1 FROM 16 BIT DATA LATCH OUTPUT1 DATA BIT 15 LONGPULSE SHORTPULSE TRIGGER NCEN D97IN525B OUTPUT15 NCOUT 3/22 Block diagrams L6452 Figure 3. Block Diagram: Nozzle activation part LONGPULSE SHORTPULSE OUTPUT0 OUTPUT1 OUTPUT2 OUTPUT3 OUTPUT4 OUTPUT5 16 BIT SERIAL INPUT & PARALLEL OUTPUT OUTPUT6 16 BIT LATCH 16 POWER OUTPUT STAGES OUTPUT7 OUTPUT8 OUTPUT9 OUTPUT10 OUTPUT11 OUTPUT12 OUTPUT13 OUTPUT14 OUTPUT15 SDI SDC LATCHCLEAR LATCHDATA NCEN NCOUT HSA1 HSA2 HSA3 HSA4 HSA5 13 MOS DRIVERS CHANNEL A 0 to 13 UP/DOWN COUNTER HSA6 HSA7 HSA8 HSA9 C0 HSA10 HSA11 HSA12 4 to 13 LINES DECODER HSA13 C1 SELECTOR ENIC S3 UPC/S2 RESC/S1 CLKC/S0 C3 C2 HSB1 HSB2 HSB3 HSB4 HSB5 13 MOS DRIVERS CHANNEL B HSB6 HSB7 HSB8 HSB9 HSB10 CHSEL ENCH D97IN524A HSB11 HSB12 HSB13 4/22 L6452 Pin description 2 Pin description Figure 4. Pin connection (Top view) STEPUPBOOST ONENABLE CRCLOCK STEPUPGND VSTEP-UP CLKC/S0 RESC/S1 CRDATA UPC/S2 CSGND VXB VXA 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CRLATCH OUTPUT15 VC POWGND OUTPUT14 OUTPUT13 VC OUTPUT12 OUTPUT11 VC OUTPUT10 OUTPUT9 VC OUTPUT8 POWGND OUTPUT7 VC OUTPUT6 OUTPUT5 VC OUTPUT4 OUTPUT3 VC OUTPUT2 OUTPUT1 VC POWGND OUTPUT0 LATCHCLEAR NCEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 D97IN489C CHSEL 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ENCH REXT RXA RXB VDD Va S3 ENIC GND HSA1 HSA2 HSA3 HSA4 HSA5 HSA6 HSA7 HSA8 HSA9 HSA10 HSA11 HSA12 HSA13 Vr HSB13 HSB12 HSB11 HSB10 HSB9 HSB8 HSB7 HSB6 HSB5 HSB4 HSB3 HSB2 HSB1 GND ADCK ADDATA ANALOGND CONVSTART ADCGND RESET NCOUT CH0BUF VREF CH5 CH4 CH3 CH2 LATCHDATA LONGPULSE Table 1. Pin # 1 2, 5, 6, 8, 9, 11, 12, 14, 16, 18, 19, 21, 22, 24, 25, 28 Pin function Name CRlatch Function A rising edge transfer the information from CR shift register into the control register latching the data on the falling edge Output15...0 High side DMOS outputs. To be active, ShortPulse and/or LongPulse and NcEn must have a low level SHORTPULSE SDC CH1 SDI Va 5/22 Pin description L6452 Pin function - continued Name Function Table 1. Pin # 3, 7, 10, 13, 17, 20, 23, 26 4, 15, 27, 51, 79, 92 29 Vc Outputs Power Supply GND LatchClear logic and power ground A high level resets all bit in the latch A high level enables the internal current sources and disables all DMOS outputs. To be active, the internal current sources must have their corresponding bit set in the 16 bit latch and LongPulse must be set to low level. This function is called Nozzle Check Enable. A rising edge latches the 16 bit stored in the shift register in the 16 bit latch Serial data input of the shift register The data bit presented to the SDI pin is stored into the register on the rising edge of this pin A low level activates all outputs having their corresponding bit in the 16 bit latch set (this pin has an internal pull-up resistor) A low level activates all outputs having their corresponding bit in the 16 bit latch reset (this pin has an internal pull-up resistor) A low level disables all functions and clears all registers A high level enables the A/D to start the new conversion A/D clock signal; the ADDATA signal are valid on the falling edge of this pin If NcEn is high this output provides a high level when the open load is detected on the output. If NcEn is low this output provides a high level when a short circuit is detected on HSA/B output Analog output signal (CH0 buffered) A/D serial data output Analog ground connection Ground of internal ADC Power supply Reference voltage generator A/D input signals Head selector address output channel B Head Select Power Supply Head selector address output channel A Enable Internal Counter: A high level enables the counter and the internal decoder will activate of the HSx outputs according to the counter’s outputs. Signal S0 becomes ClkC and S1 becomes ResC 30 NcEn 31 32 33 34 35 36 37 38 LatchData SDI SDC LongPulse ShortPulse Reset ConvStart ADCK 39 40 41 42 43 44, 90 45 46 to 50 52 to 64 65 66 to 78 NCOut CH0buf ADDATA AnalogGND ADCGND Va Vref CH5..CH1 HSB1..HSB13 Vr HSA13..HSA1 80 EnlC 6/22 L6452 Table 1. Pin # 81 82 83 Pin description Pin function - continued Name ChSel S3 UpC/S2 Function Channel Select: A low level enables channel A and a high level enables channel B Decoder input signals when EnIC is low UpCount/S2: A high level enables the internal counter to up counting. A low level enables down counting depending on EnlC value it becomes S2. Reset Count/S1: A low level resets the internal counter depending on EnlC value it becomes S1. Enable Channel: A low level enables the selected channel (this input has an internal pull up resistor) A high level clocks the internal counter depending on EnlC value it becomes S0. Ground of step up block Boost voltage Driving voltage of power DMOS stage 5V logic supply An external resistor connected to ground fixes the internal current source value Current source outputs RxA, RxB voltage after an optional external filter A low level enables the current source generator according the A/B and ON/OFF control register bit Data on pin CRdata are stored into the register on the rising edge of this pin Control register serial data input 84 ResC/S1 85 EnCh 86 87 88 89 91 93 94, 95 96, 97 98 99 100 ClkC/S0 StepUpGND StepUpBoost VstepUp VDD Rext RxB, RxA VxA, VxB OnEnable CRclock CRdata 7/22 Electrical specifications L6452 3 3.1 Electrical specifications Absolute maximum ratings Table 2. Symbol Vc Vr Va Vdd Vstep_up ESD Vin Iout Tj Tamb Tstg Absolute maximum ratings Parameter Power line supply voltage Address line supply voltage Analog supply voltage Logic supply voltage Driving voltage of power DMOS stage In accordance with IEC 1000-4-2 (1) Logic input voltage range Output continuous current Junction temperature Operating temperature range Storage temperature range Value 14 14 14 6 28 ±4 -0.3 to Vdd + 0.3 0.5 150 0 to 70 -55 to 150 Unit V V V V V kV V A °C °C °C (1) All the pins connected to the pen passed ESD Contact Electrostatic Discharge @ ±4kV (150pF, 330Ohm source). 3.2 Table 3. DC Electrical characteristics DC Electrical characteristics (Tj = 25°C) Parameter Power Line Supply voltage Address line supply voltage Analog supply voltage Logic supply voltage Vc sleep supply current Vr sleep supply current Va sleep supply current Vc supply current Vr supply current Va supply current IRext= 3mA OnEnable = 1 Reset = 0 (1) Symbol Vc Vr Va Vdd Ics Irs Ias Ic Ir Ia Test Condition Min. 10.5 (2) Typ. 11.5 11.5 11.5 5 Max. 12.5 12.5 12.5 5.5 1 0.3 3 1.5 0.6 13 Unit V V V V mA mA mA mA mA mA (1) (1) 10.5 10.5 4.5 8/22 L6452 Table 3. Symbol Idd Vref Irefext Iccs ∆Iccs/Iccs Vampout Electrical specifications DC Electrical characteristics (Tj = 25°C) - continued Parameter Vdd supply current Reference Voltage Reference current (external) Programmed constant current Constant current regulation Output voltage of integrated amplifier V ref I ccs = -------------- ⋅ 4 2R ext Va=11V Tamb = 5 to 55°C e (3) 12 0.33 Va-1 Test Condition sleep or normal condition Tamb= 5 to 55°C 4.85 5 Min. Typ. Max. 5 5.15 7 13.5 Unit mA V mA mA % V Vcm Operating input voltage at pins Vref= 5V g1=1.2 g2 = 3 Vxa and Vxb 7 V g1 g2 Vstep-up Amp. A1 Voltage gain Amp.A2 Voltage gain Driving Voltage of power DMOS 1.188 2.95 1.2 3.02 Vc +11 1.212 3.10 V A/D CONVERTER VA/D in A/D input voltage Selected Channel: CH1 to CH5 Selected Ch=CH0 Input CH1 to CH5 selected or not 0 e (3) Vref Vref ±1 V V µA Iexch A/D input current OFFSET VOLTAGE GENERATION / DAC Voffset Vstep Kdac Offset Voltage Voltage increment (1LSB) Voffset/Vref Vref = 5V Vref= 5V 2.5 + e (3) 7.34 156 ±3 V mV % Any step N ≥ 4 A/D CONVERTER TIMINGS Tcscks Tcsckh Tckout Tcsz Fadck Tcslow ConvStart set up time ConvStart hold time Falling edge of clock to data out valid delay ConvStart falling edge to output in Hi-Z delay Clock frequency Conv. Start low level time 5.6 Cload ≤ 20pF 200 200 200 200 250 ns ns ns ns KHz µs 9/22 Electrical specifications L6452 Table 3. Symbol Tacqth Tacqpr DC Electrical characteristics (Tj = 25°C) - continued Parameter Theoretical acquisition time Real acquisition time Test Condition fadck= 250 kHz fadck= 250 kHz Min. 32.4 36 Typ. Max. Unit µs µs DIGITAL INTERFACE INPUT Vinp Vinm Vhys Iin Schmitt Trigger positive-going Threshold Schmitt Trigger negative-going Threshold Schmitt Trigger Hysteresis Input Current (Vin=0; Vdd=5) (4) 1/3Vdd 0.1 50 0.3 150 2/3Vdd V V 1 300 V µA CR LATCH TIMINGS Tls Tlhigh Tlconv tstore Latch set up time Latch high time Latch data valid to A/D input valid delay Latching data time Selected channel: CH1..CH5 CH0 100 100 ns ns µs µs ns 4 7 200 Note: The control register (driving signals CRdata, CRclock) is accessed with the same timing specifications as the data 16 bit shift register (signals SDI, SDC) SHIFT REGISTER AND LATCH TIMING Ta Tb Tc Td Te Tf Tg Tset Set up time Hold time Serial clock low time Serial clock high time Serial clock period Latch set up time Latch data high time NcEn setup time with respect to LongPulse (or ShortPulse) Asserted NcEn hold time with respect to LongPulse (or ShortPulse) Asserted Set-up time from latch to Pulse (short and long) Time from Pulse deassertion to new data latching 35 35 35 35 125 100 100 160 ns ns ns ns ns ns ns ns Thold 0 ns Tlp Tpl 125 125 ns ns 10/22 L6452 Table 3. Symbol Electrical specifications DC Electrical characteristics (Tj = 25°C) - continued Parameter Test Condition Min. Typ. Max. Unit OUTPUTS ELECTRICAL CHARACTERISTICS Iout Rds(ON) Tpdr Output Current (outputs 0..15) On Resistance Power output Turn on Time DC=33%; preheating DC=66% Tj= 25°C From 50% LongPulse to 90% power output rising edge Load = 30 Ohm in parallel with 1.5nF From 50% LongPulse to 90% power output falling edge Load = 30 Ohm in parallel with 1.5nF 0.5 1 400 1.3 160 mA Ω ns Tpd Rpon Toff delay time Open Nozzle Check 100 2 ns kΩ HEAD ADDRESS SELECTOR OUTPUT Th UpC/S2, ResC/S1, ChSel, ClkC/S0 and EnIC set-up time with respect to EnCh UpC/S2, ResC/S1, ChSel, ClkC/S0 and EnIC hold time with respect to EnCh UpC/S2 with respect to hold time ClkC/S0 UpC/S2 with respect to setup time ClkC/S0 Enable input to active output delay time Clock to active output delay time Disable input to inactive output delay time Counter Clock Frequency Clock duty cycle Address Turn on time Address Turn off time From 50% ClkC/S0 or selector signal to 90% of the address output variation Load: see Figure 11. 10 150 ns Tk 50 ns Tj Ti Tm Tn To fclk-counter Clkdc Ton Toff 200 100 100 150 100 1 90 325 325 ns ns ns ns ns MHz % ns ns (1) The three supply voltage are independent inside the specified value; (2) The Min. value for Vc power line has been verified down to 4V in application lab.; nevertheless the parameters are guaranteed within spec limit of the above DC ELECTRICAL CHARACTERISTICS table. (3) e = 2 · Vstep (4) This applies to input pins having an internal pull-up (ENCH, LONGPULSE, SHORTPULSE) 11/22 Electrical specifications L6452 3.3 Counter Truth Table EnIC = 1 UpC/S2 = 1 ResC/S1 = 1 Clock Counter 0 C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 C1 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 C0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 EnIC = 1 UpC/S2 = 0 ResC/S1 = 1 Clock Counter 0 C3 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 C2 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 C0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 12/22 L6452 Electrical specifications 3.4 Decoder Truth Table OUTPUTS (HS) ACTIVE All inactive 1 2 3 4 5 6 7 8 9 10 11 12 13 All inactive All inactive C3* 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2* 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1* 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 C0* 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 * C3 = S3, C2 = S2, C1 = S1, C0 = S0, when EnIC = 0 This table is valid for both Channel A and Channel B and when EnCh is set to low level. 13/22 Print Head Temperature Control Part L6452 4 4.1 Print Head Temperature Control Part Introduction For quality printing, it is necessary to know and control the temperature of the print head. Thus, the latter has a built - in aluminium resistor, whose value changes slightly with the temperature. The temperature determination is done by injecting a constant current in the resistor, and measuring the voltage drop across it. Since high - end printers have two heads, it must also be possible to switch quickly the measurement process from one to the other. The function is foreseen to be integrated into the head driver, and is described hereafter. 4.2 Print Head Block Diagram (Figure 5.) At first we have a constant current source, which can be disabled by an external pin (OnEnable) or by a control register, described later. The value of the current can be programmed by an external resistor, and is given by: V ref ⋅ 4 I CCS = ------------------2 ⋅ R ext This current is injected either into the resistor of the head A (Ralu. A) or B (Ralu. B), depending of the switch SW3. The resistors are grounded, and the voltage at their > side (Vx) is re-entered via the pins VxA and VxB. Using separate pins from RxA and RxB permits to be more flexible, and a filter can eventually be added as shown in the drawing. The voltage Vx is amplified by A1 and A2, and then converted in a digital value. To be compatible with the input range of the A/D converter, it is necessary to subtract an offset voltage Voffset from Vx. Moreover, as the initial value of the aluminum resistor is very imprecise. Voffset must be adjustable; this is done by means of a 5 bit - D/A converter, giving 32 different values. Finally, the voltage at the input of the A/D converter is: VCH0 = g1 · g2 · VX - g2 × VOFFSET or VCH0 = g1 · g2 · Ralu · ICCS - g2 · VOFFSET; VOFFSET = VREF/2 + N · VREF/32 N = 0, 1, ...31 The reference voltage generator (VREF) is integrated, and used for the current source and both the A/D and D/A converters. In this way, the system performance is independent from the precision of VREF; this one should, however, be stable. Vref is also available on pin #45, and can be used for low consumption purposes. (The external sinked current has to be a DC current). The system is under control of a 10 bit register, CR. CR is accessed serially and has a transparent latch, which can be used or not (by trying the latch signal CR latch to VCC). 14/22 L6452 Figure 5. Print Head Block Diagram Print Head Temperature Control Part VREF Va REF VOLT VREF OUT VREF A1 g1 A A2 + g2 CH0 D CONVSTART ADCK ADDATA CH5 CH4 + Vx VOFFSET VREF A D/A 5 BIT B D C SW3 CH0BUF CH3 CH2 CH1 A/D INPUTS REXT HIGH-SIDE CONSTANT CURRENT SOURCE SW1 SW2 VREF/2 ONENABLE LATCH 10 BIT CRLATCH CONTROL REGISTER CRCLOCK CRDATA SHIFT REG. 10 BIT A/B ON/OFF DA4 DA3 DA2 DA1 DA0 ADDR2 ADDR1 ADDR0 RXA, RXB VXA, VXB ANALOG GND RALU A RALU B Note; the analog ground is separated from the digital ground of the remaining part of the driver D97IN533C Figure 6. Control Register details. SHIFT DIRECTION CR9 A/B CR8 ON/OFF CR7 DA4 CR6 DA3 CR5 DA2 CR4 DA1 CR3 CR2 CR1 CR0 DA0 ADDR2 ADDR1 ADDR0 SELECTION OF RESISTOR A (A/B = 0) or B (A/B = 0) for TEMPERATURE MEASUREMENT D/A INPUTS FOR OFFSET COMPENSATION DA0 = LSB DA4 = MSB POSITIVE LOGIC CHANNEL SELECTION A/D INPUT D97IN534B ONE INTERNAL CHANNEL (VX MEASUREMENT) FIVE UNCOMMITTED, GENRAL-PURPOSE EXTERNAL CHANNELS SWITCHES THE CURRENT SOURCE ON or OFF; LINKED WITH ONENABLE INPUT PIN ADDR2 ADDR1 ADDR0 CHANNEL ADDRESS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 (INTERNAL) 1 (EXTERNAL) 2 (EXTERNAL) 3 (EXTERNAL) 4 (EXTERNAL) 5 (EXTERNAL) 6 7 CH0BUF A B B B B B C D ON/OFF 0 1 0 1 ONENABLE 1 1 0 0 ACTION OFF OFF OFF ON 15/22 Print Head Temperature Control Part L6452 Figure 7. CR Latch Timings CRDATA DA0 ADDR2 ADDR1 ADDR0 CRCLOCK tls tlhigh tstore CRLATCH tlconv CONVSTART D97IN535B Figure 8. CONVSTART A/D Converter Timings ADCK ADDATA HIGH IMPEDANCE tcscks tcsckh 7 tckout 6 5 4 3 2 1 0 HIGH IMPEDANCE tcsx D97IN536 Figure 9. Power Output Timing LONGPULSE or SHORTPULSE 50% 50% 90% 90% POWER OUTPUT tpdr tpd (*) D97IN526B (*) tpd does not include the falling edge time because this is strictly dependent on the RC load. Figure 10. Trigger of Nozzle Check Signal VPOWER FROM THE COMMON CONNECTION OF ANALOG MULTIPLEXERS VLOGIC NOZZLE CHECK OUTPUT + 1 0 INTERNAL REFERENCE NCEN HSA/B SHORT CIRCUIT DETECTION D97IN527A 16/22 L6452 Figure 11. Address load reference Print Head Temperature Control Part HS OUTPUT 200Ω 250pF A Figure 12. Mode Counter UpC/S2 ResC/S1 ChSel EnIC ClkC/S0 ti tj EnCh tk th HSA1 : 13 or HSB1 : 13 tm tn D97IN529B to 17/22 Print Head Temperature Control Part L6452 Figure 13. Mode Selelector Sel 0:3 ChSel EnIC EnCh tk th HSA1 : 13 or HSB1 : 13 tm tn D97IN530A to Figure 14. Sequence of Shift Register Data Loading SDI D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SDC LATCHDATA LONGPULSE SHORTPULSE OUTPUT * OUTPUT ** * THE CORRESPONDING DATA BIT IS SET ** THE CORRESPONDING DATA BIT IS RESET tpl tlp D97IN531C D0 18/22 L6452 Figure 15. Latch Timing ta tb Print Head Temperature Control Part SDI SDCK LATCHDATA tf tc D97IN532A tg td te 19/22 Package information L6452 5 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 16. PQFP100 Mechanical Data & Package Dimensions DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.65 16.95 13.90 0.25 2.55 0.22 0.13 22.95 19.90 23.20 20.00 18.85 0.65 17.20 14.00 12.35 0.80 1.60 0°(min.), 7°(max.) 0.95 0.026 17.45 14.10 0.667 0.547 2.80 3.05 0.38 0.23 23.45 20.10 mm TYP. MAX. 3.40 0.010 0.100 0.0087 0.005 0.903 0.783 0.913 0.787 0.742 0.026 0.677 0.551 0.486 0.031 0.063 0.037 0.687 0.555 0.110 0.120 0.015 0.009 0.923 0.791 MIN. inch TYP. MAX. 0.134 OUTLINE AND MECHANICAL DATA PQFP100 20/22 L6452 Revision history 6 Revision history Date 15-Mar-1999 Revision 1 Initial release. Modified Electrical Specification and any Time Diagrams. Modified pin and signal names through out the spec. Modified Table 1 Pin function pins 83, 84 & 86. Added ESD parameter in the Table 2 Absolute maximum ratings. Modified Table 3: Tset, Thold and Rpon parameters. Modified Figure 14. Changes 06-Feb-2006 2 21/22 L6452 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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