L6460

L6460 SPI configurable stepper and DC multi motor driver Features ■ ■ Operating supply voltage from 13 V to 38 V 4 full bridge driver configurable in multi-motor application to drive: – 2 DC and 1 stepper motor – 4 DC motor Bridge 1 and 2 (RDSon = 0.60 Ω) can be configured to work as: – Dual full bridge driver – Super DC driver – 2 half bridge driver – 1 super half bridge – 2 power switches – 1 super power switch Bridge 3 and 4 (RDSon = 0.85 Ω) can be configured to work as: – Same as bridges 1 and 2, listed above – Stepper motor driver: up to 1/16 microstepping – 2 buck regulators (bridge 3) – 1 super buck regulator – Battery charger (bridge 4) Power supply management – One switching buck regulator – One switching regulator controller – One linear regulator – One battery charger Fully protected through – Thermal warning and shutdown – Overcurrent protection – Undervoltage lock-out SPI interface Programmable watchdog function Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin Very low power dissipation in shut-down mode (~35 mW) Doc ID 17713 Rev 1 1/139 www.st.com 139 ■ TQFP64 exposed pad ■ ■ Auxiliary features – Multi-channels 9 bit ADC – 2 operational amplifiers – Digital comparator – 2 low voltage power switches – 3 general purpose PWM generators – 14 GPIOs Description The L6460 is optimized to control and drive multimotor system providing a unique level of integration in term of control, power and auxiliary features. Thanks to the high configurability L6460 can be customized to drive different motor architectures and to optimize the number of embedded features, such as the voltage regulators, the high precision A/D converter, the operational amplifier and the voltage comparators. The possibility to drive simultaneously stepper and DC motor makes L6460 the ideal solution for all the application featuring multi motors. Table 1. Device summary Package TQFP64 L6460TR Tape and reel Packing Tray ■ ■ ■ ■ ■ Order code L6460 ■ July 2010 Contents L6460 Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 1.2 1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 3 L6460’s main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 3.2 3.3 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 Internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1 4.2 4.3 VSupplyInt regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 V3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 Supervisory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 5.2 5.3 Power on reset (POR) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 nRESET generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6 7 8 Watchdog circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Internal clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1 8.2 8.3 8.4 8.5 8.6 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Basic device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Slave device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Master device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Single device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Sub-configurations for slave, master or single device modes . . . . . . . . . 41 2/139 Doc ID 17713 Rev 1 L6460 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 8.6.6 Contents Bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Primary regulator mode (KP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Simple regulator mode (KT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Bridge + VEXT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 10 Power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.1 10.2 10.3 10.4 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 nAWAKE pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 12 Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.1 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13 Switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.1 13.2 13.3 Pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Output equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Switching regulator controller application considerations . . . . . . . . . . . . . 54 14 Power bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 14.1 Possible configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 14.1.1 14.1.2 14.1.3 14.1.4 14.1.5 14.1.6 14.1.7 14.1.8 Full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Synchronous buck regulator configuration (Bridge 3) . . . . . . . . . . . . . . 73 Regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Battery charger or switching regulator (Bridge 4) . . . . . . . . . . . . . . . . . 76 15 AD converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Doc ID 17713 Rev 1 3/139 Contents L6460 15.1 Voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 16 17 18 19 Current DAC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 General purpose PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 19.1 19.2 General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2) . 90 Programmable PWM generator (GpPwm) . . . . . . . . . . . . . . . . . . . . . . . . 90 20 21 22 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Digital comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 GPIO pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 GPIO[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 GPIO[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 GPIO[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 GPIO[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 GPIO[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 GPIO[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 GPIO[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 GPIO[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 GPIO[8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 22.10 GPIO[9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 22.11 GPIO[10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 22.12 GPIO[11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 22.13 GPIO[12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.14 GPIO[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 22.15 GPIO[14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 23 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 23.1 23.2 Read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Doc ID 17713 Rev 1 4/139 L6460 Contents 24 25 26 27 Registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Schematic examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Doc ID 17713 Rev 1 5/139 List of tables L6460 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. 6/139 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 IC operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stretch time selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Watchdog timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Possible start-up pins state symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Start-up correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Main switching regulator PWM specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Main switching regulator current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Switching regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Switching regulator controller application: feedback reference. . . . . . . . . . . . . . . . . . . . . . 54 PWM selection truth table for bridge 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PWM selection truth table for bridge 3 or 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Bridge selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Bridge 3 and 4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Full bridge truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Half bridge truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Switch truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Sequencer driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Stepper driving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Stepper sequencer direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Internal sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Stepper off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Stepper fast decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Battery charger regulator controller PWM specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ADC truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Channel addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADC sample times when working as a 8-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC sample time when working as a 9-bit ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Voltage divider specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Current DAC truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Interrupt controller event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Comparison type truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 DataX selection truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 GPIO functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 GPIO[0] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 GPIO[1] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 GPIO[2] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 GPIO[3] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 GPIO[4] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 GPIO[5] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 GPIO[6] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 GPIO[7] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 GPIO[8] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Doc ID 17713 Rev 1 L6460 Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. List of tables GPIO[9] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 GPIO[10] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 GPIO[11] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 GPIO[12] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 GPIO[13] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 GPIO[14] truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Doc ID 17713 Rev 1 7/139 List of figures L6460 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VSupplyInt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Charge pump block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 nReset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Watchdog circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Standby mode function description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 nAWAKE function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Linear main regulator with external bipolar for high current . . . . . . . . . . . . . . . . . . . . . . . . 49 Main switching regulator functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Switching regulator controller functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Switching regulator controller output driving: equivalent circuit . . . . . . . . . . . . . . . . . . . . . 54 H Bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Bridge 1 and 2 PWM selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Super bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Internal comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Battery charger control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Li-ion battery charge profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Simple buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 A2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Current DAC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Configurable 3.3 V operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Interrupt controller diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Digital comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 GPIO[0] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 GPIO[1] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 GPIO[2] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 GPIO[3] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 GPIO[4] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 GPIO[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 GPIO[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 GPIO[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 GPIO[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 GPIO[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 GPIO[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 GPIO[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 GPIO[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8/139 Doc ID 17713 Rev 1 L6460 Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. List of figures GPIO[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 GPIO[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SPI write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 SPI input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SPI output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Application with 2 DC motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 135 Application with 2 DC motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 136 TQFP64 mechanical data an package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Doc ID 17713 Rev 1 9/139 General description L6460 1 1.1 General description Overview L6460 offers the possibility to control and power multi motor systems, through the management of simultaneous driving of stepper and DC motor. A number of features can be configured through the digital interface (SPI), including 3 voltage regulators, 1 high precision A/D converter, 2 operational amplifiers and 14 configurable GPIOs. The high flexibility allows the possibility to configure two, one full or half bridge to work as power stage featuring additional voltage buck regulators. Figure 1. Block diagram Note: See following Chapter 2 for a detailed description of possible configurations. 10/139 Doc ID 17713 Rev 1 L6460 General description 1.2 Pin connection Figure 2. Pin connection DC1_PLUS VSWDRV_GATE DC3_PLUS 50 VSWDRV_SW VSupplyInt VGPIO_SPI nRESET VSupply GPIO6 GPIO7 CPH VSupply VPump V3V3 64 DC1_PLUS VSWDRV_SNS VSWDRV_FB GPIO4 GPIO3 DC1_MINUS DC1_MINUS GND1 GND2 DC2_MINUS DC2_MINUS GPIO2 GPIO1 GPIO0 nSS DC2_PLUS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DC2_PLUS 63 62 61 60 59 58 57 56 55 54 53 52 51 49 48 DC3_SENSE GPIO5 GPIO9 GPIO10 GPIO11 N.C. DC3_MINUS DC3_SENSE DC4_SENSE DC4_MINUS N.C. GPIO14 GPIO13 GPIO12 nAWAKE DC4_SENSE GND_PAD N.C. 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 N.C. 18 VSupply 19 MISO CPL 20 MOSI 21 VLINmain_FB 22 VLINmain_OUT 23 GPIO8 24 VSWmain_SW 25 VSupply 26 VSWmain_FB 27 VREF_FB 28 IREF_FB 29 SCLK 30 VSupply 31 DC4_PLUS Doc ID 17713 Rev 1 11/139 General description L6460 1.3 Pin list Table 2. Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pins configuration Pin name DC1_PLUS Description Bridge 1 phase “plus” output Type Output Analog input Analog input Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Output Output Power/digital Power/digital Output Output Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Analog Input - CMOS input CMOS input Output Output Power input CMOS output CMOS input Analog input Power output Analog In/Out - CMOS bi-dir Power output Power Input Analog input Analog input Analog input CMOS input Power input Output VSWDRV_SNS Switching regulator controller sense VSWDRV_FB GPIO4 GPIO3 Switching regulator controller feedback General purpose I/O General purpose I/O DC1_MINUS Bridge 1 phase “minus” output DC1_MINUS Bridge 1 phase “minus” output GND1 GND2 Ground pin for bridge1 Ground pin for (1)(2)(3) bridge2(1)(2)(3) DC2_MINUS Bridge 2 phase “minus” output DC2_MINUS Bridge 2 phase “minus” output GPIO2 GPIO1 GPIO0 nSS DC2_PLUS DC2_PLUS VSupply MISO MOSI VLINmain_FB General purpose I/O General purpose I/O General purpose I/O SPI chip select pin Bridge 2 phase “plus” output Bridge 2 phase “plus” output Main voltage supply SPI serial data output SPI serial data input Linear main regulator feedback VLINmain_OUT Linear main regulator output GPIO 8 VSWmain_SW VSupply VSWmain_FB VREF_FB IREF_FB SCLK VSupply DC4_PLUS N.C. General purpose I/O Main switching regulator switching output Main voltage supply Main switching regulator feedback pin Regulator voltage feedback Regulator current feedback SPI input clock pin Main voltage supply Bridge 4 phase “plus” output Not connected DC4_SENSE Bridge 4 sense output(4) nAWAKE Device wake up Doc ID 17713 Rev 1 Output CMOS input 12/139 L6460 Table 2. Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 E_Pad General description Pins configuration (continued) Pin name GPIO12 GPIO13 GPIO14 N.C. Description General purpose I/O General purpose I/O General purpose I/O Not connected Output Output Output Output Type Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir DC4_MINUS Bridge 4 phase “minus” output DC4_SENSE Bridge 4 sense output(4) DC3_SENSE Bridge 3 sense output (4) DC3_MINUS Bridge 3 phase “minus” output N.C. GPIO11 GPIO10 GPIO9 GPIO5 Not connected General purpose I/O General purpose I/O General purpose I/O General purpose I/O Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Analog In/Out - CMOS bi-dir Output DC3_SENSE Bridge 3 sense output(4) N.C. DC3_PLUS VSupply nRESET V3v3 VSupplyInt GPIO7 VGPIO_SPI GPIO6 VSWDRV_SW Not connected Bridge 3 phase “plus” output Main voltage supply Open drain system reset pin Internal 3.3 volt regulator Internal voltage supply General purpose I/O Low voltage pins power supply General purpose I/O Switching regulator controller source input Output Power input CMOS Input/output Power Input/output Power Input Analog In/Out - CMOS bi-dir Power input Analog In/Out - CMOS bi-dir Power input Analog output Power Input/output Power Input/output Power Input/output Power input Output VSWDRV_GATE Switching driver gate drive pin VPump CPH CPL VSupply DC1_plus GND_PAD Charge pump voltage Charge pump high switch pin Charge pump low switch pin Main voltage supply Bridge 1 phase “plus” output (1)(2)(3) 1. These pins must be connected all together to a unique PCB ground. 2. Bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (GND1 or GND2) and the other is connected to exposed pad (E_Pad) ground ring. This makes the bond wires testing possible by forcing a current between E-Pad and GND1 or GND2 pins and using the other pin as sense pin to measure the resistance of E-Pad bonding. (N.B: grounds of two bridges are internally connected together). 3. The analog ground is connected to exposed pad E-Pad. 4. The pin must be tied to ground if bridge is not used as a stepper motor. Doc ID 17713 Rev 1 13/139 L6460’s main features L6460 2 L6460’s main features L6460 includes the following circuits: ● Four widely configurable full bridges: – Bridges 1 and 2: – – – – – Diagonal RDSon: 0.6 Ω typ. Max operative current = 2.5 A. Diagonal RDSon: 0.85 Ω typ. Max operative current = 1.5 A. Bridges 3 and 4: ● Possible configurations for each bridge are the following: – Bridge 1: – – – – – – – – DC motor driver. Super DC (bridge 1 and 2 paralleled form superbridge1). 2 independent half bridges. 1 super half bridge (bridge 1 side A and bridge 1 side B paralleled form superhalfbridge1). 2 independent switches (high or low side). 1 super switch (high or low side). Bridge 2 has the same configurations of bridge 1. Bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form superbridge2) plus the following: – – – ½ stepper motor driver. 2 buck regulators (VAUX1_SW, VAUX2_SW). 1 Super buck regulator (VAUX1//2_SW). ½ stepper motor driver. 1 super buck regulator (VAUX3_SW). Battery charger. – Bridge 4 has the same configurations of bridge 1 plus the following: – – – ● One buck type switching regulator (VSWmain) with: – – – – – – – Output regulated voltage range: 1-5 Volts. Output load current: 3.0 A. Internal output power DMOS. Internal soft start sequence. Internal PWM generation. Switching frequency: ~250 kHz. Pulse skipping strategy control. Output regulated voltage range: 1-30 Volts. Selectable current limitation. Internal PWM generation. Pulse skipping strategy control. Doc ID 17713 Rev 1 ● One switching regulator controller (VSWDRV) with: – – – – ● One linear regulator (VLINmain) that can be used to generate low current/low ripple 14/139 L6460 L6460’s main features voltages. This regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages. ● ● ● ● One bidirectional serial interface with address detection so that different ICs can share the same data bus. Integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin. Fourteen general purpose I/Os that can be used to drive/read internal/external analog/logic signals. One 8-bit/9-bit A/D converter (100 kS/s @ 9-bit, 200 kS/s @8-bit). It can be used to measure most of the internal signals, of the input pins and a voltage proportional to IC temperature. – – – – Current sink DAC: Three output current ranges: up to 0.64/6.4/64 mA. 64 (6-bit programmable) available current levels for each range. 5 V output tolerant. 3.3 V supply, rail to rail input compatibility, internally compensated. They can have all pins externally accessible or can be internally configured as a buffer o make internal reference voltages available outside of the chip. Unity gain bandwidth > 1 MHz. They can also be set as comparators with 3.3 V input compatibility and low offset. ● Two operational amplifiers: – – – – ● ● ● ● Two 3.3 V pass switches with 1 Ω RDSon and short circuit protected. Programmable watchdog function. Thermal shutdown protection with thermal warning capability. Very low power dissipation in “low power mode” (~35 mW) L6460 is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. Bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility L6460 includes 2 separate regulation loops for these regulators; when the bridge is used as a motor driver, the 2 regulation loops can be redirected on general purpose I/Os to leave the possibility to assembly a switching regulator by only adding an external FET. Doc ID 17713 Rev 1 15/139 Electrical specifications L6460 3 3.1 Electrical specifications Absolute maximum rating The following specifications define the maximum range of voltages or currents for L6460. Stresses above these absolute maximum specifications may cause permanent damage to the device. Exposure to absolute maximum ratings for extended periods may affect device reliability. Table 3. Absolute maximum ratings Description VSupply voltage VGPIO_SPI voltage V3V3 voltage Switching regulators output pin voltage range Switching regulators min pulsed voltage Charge pump voltage Junction temperature(2) tpulse < 500ns (1) Parameter VSupply VGPIO_SPI V3V3pin VSW VSW_pulse VPump TJ Test condition Min Max 40 3.9 Unit V V V V V -0.3 -1 -3 3.9 VSupply 15 -40 -40 190 TSD V °C °C Storage Operating 1. This value is useful to define the voltage rating for external capacitor to be connected from VPump to VSupply. VPump is internally generated and can never be supplied by external voltage source nor is intended to provide voltage to external loads. 2. TSD is the thermal shut down temperature of the device. 3.2 Operating ratings specifications Table 4. IC operating ratings Description VSupply voltage range VSupply operative current VSupply shut down state current VGPIO_SPI voltage range VGPIO_SPI operative current 3.3V input pin voltage range Output pin voltage range Feedback pin voltage range Output pin voltage range VSWDRV_SW pin voltage range Doc ID 17713 Rev 1 (4) (4) (4) (3) (2) Parameter VSupply ISupply IShut_down VGPIO_SPI IVGPIO_SPI V3v3 VLINmain_OUT VLINmain_FB VSWmain_SW VSWDRV_SW 16/139 Test condition Min 13 (1) Max 38 15 1.5 Unit V mA mA V mA V V V V V 2.4 3.6 0.4 3.6 0 0 -1 -1 VSupply 3.6 Vsupply VSupply L6460 Table 4. IC operating ratings Description Gate drive pin voltage Sense pin voltage Junction temperature Operating Test condition Electrical specifications Parameter VSWDRV_GATE VSWDRV_SNS TJ Min 0 Max VPump Unit V V °C VSupply VSupply -3V -40 125 1. For Vsupply lower than 21 V an external resistor between Vsupply and Vsupply Int pins are required. For Vsupply lower than 15 V external diodes for charge pump are required. 2. Operating supply current is measured with system regulators operating but not loaded. 3. Operating VGPIO_SPI current is measured with all circuits supplied by VGPIO_SPI (GPIO’s, operational amplifiers and pass switches) enabled but not loaded. 4. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 3.3 Table 5. Electrical characteristics Electrical characteristics Description Test condition Min Typ Max Unit Parameter VSupplyInt regulator VS_Int IS_Int VSupplyInt output voltage VSupplyInt operative current (1) (2) 18 19.5 11 21 V mA Charge pump VPump VPump FPump V3V3 regulator V3V3 Power on reset VSupply_POR_valid VSupply voltage for POR valid VSupply_POR_fall tSupply_POR_filt V3V3_POR_fall V3V3_POR_rise V3V3_POR_hys t3V3_POR_filt nRESET circuit VnRST_L nRESET low level output voltage I=10mA 0.4 V VSupply POR falling threshold VSupply POR filter Time V3v3 POR falling threshold V3v3 POR rising threshold V3v3 POR hysteresis V3v3 POR filter time V3V3 falling V3V3 rising 1.9 InRESET = 1mA VSupply falling 4 6 3 2.2 2.7 0.5 1.5 8 V V µs V V V µs V3v3 output voltage VSupply=32V 3.15 3.3 3.45 V Charge pump voltage VPump clock frequency VSupply=32V FOSC = 16MHz typ VSupply VSupply VSupply + 10.5 +12.5 + 14.5 FOSC/6 4 V kHz Doc ID 17713 Rev 1 17/139 Electrical specifications Table 5. Electrical characteristics (continued) Description nRESET fall time nRESET delay time VSupply falling threshold VSupply rising threshold VSupply hysteresis VSupply UV filter time VSupplyInt falling threshold VSupplyInt rising threshold VSupplyInt hysteresis VSupplyInt UV filter time VPump falling threshold VPump rising threshold VPump hysteresis VPump UV filter time VGPIO_SPI falling threshold VGPIO_SPI rising threshold VGPIO_SPI hysteresis VGPIO_SPI UV filter time 200 1.8 9.7 10.6 0.4 Test condition I=1mA C=50pF(3) (4) L6460 Parameter tnRST_fall tnRST_del VSupply_UV_f VSupply_UV_r VSupply_UV_hys tSupply_UV VS_Int_UV_f VS_Int_UV_r VS_Int_UV_hys tS_Int_UV VPump_UV_f VPump_UV_r VPump_UV_hys tPump_UV VGPIO_SPI_UV_f VGPIO_SPI_UV_r VGPIO_SPI_hys tGPIO_SPI_UV TSD circuit TTSD TWARM TDIFF tTSD_FILT tWARM_FILT Watchdog WD_Tclk Internal clock Fosc Min Typ Max 15 150 Unit ns ns V V V µs 10.2 10.5 0.3 11 11.5 0.5 3.5 10.7 11.4 0.7 3.5 11.8 12.5 0.7 11.7 12.2 1 V V V µs V V V µs V VSupply VSupply VSupply +7 + 7.5 +8 VSupply VSupply VSupply + 7.5 +8 + 8.5 0.3 0.5 3.5 2 2.2 250 3.5 2.4 300 0.7 V mV µs Thermal shut down temperature Warming temperature Thermal shut down to warming difference Thermal shut down filter time Warming filter time 170 140 30 8 8 °C °C °C µs µs Watchdog clock period Tosc * 222 s Oscillator frequency V3V3 = 3.3 V 14.1 16 17.6 MHz nAWAKE function VIL nAWAKE low logic level voltage Doc ID 17713 Rev 1 0.8 V 18/139 L6460 Table 5. Electrical characteristics (continued) Description nAWAKE high logic level voltage nAWAKE input hysteresis nAWAKE pin output current nAWAKE pin input current Filter time nAWAKE=0V(5) nAWAKE=0.8V (5) Electrical specifications Parameter VIH VHYS IOUT IINP tAWAKEFILT Test condition Min 1.6 Typ Max Unit V 0.25 -0.72 0.2 1.2 -2 0.4 V mA mA μs Main linear regulator Vdrop IPD VLINmain_Ref ILINmain_Ref IoutLINMax Ishort ΔVout/Vo ΔVout/ΔVSupply Vloop_acc VLIN_UV_f VLIN_UV_r VLIN_UV_hys tprim_uv Drop out voltage Internal switch pull down current Feedback reference voltage Feedback pin input current Maximum output current Output short circuit current Load regulation Line regulation Loop voltage accuracy Undervoltage falling threshold Undervoltage rising threshold Undervoltage hysteresis Under voltage deglitch filter (7) (7) Vdrop= Vsupply-VLINmain_OUT Linear Main Regulator disabled; VLINmain_OUT=1V 2 3 0.776 -2 0.8 0.824 2 V mA V µA mA 24 32 0.8 0.2 ±2.5 mA % % % 89.5 95.5 % % % µs VLINmain_OUT= Vsupply-2V VLINmain_OUT =0V, VLINmain_FB =0V 0 ≤ Iload ≤ IoutLINMax(6) Iload =10mA(6) 10 12 84.5 90.5 87 93 6 5 Main switching regulator SelFBref = ‘00’ VFBREF Main switching regulator feedback reference voltage SelFBref = ‘01’ SelFBref = ‘10’ SelFBref = ‘11’ IQ IQ_LP ISWmain_FB VSWmain_OUT Iload RDSonHS Output leakage current Output leakage current in “low power mode” VSWmain_FB pin current Output voltage range Maximum output load current Internal high side RDSon Tjunction = 125°C VSupply = 36V Tjunction = 125°C Tjunction = 125°C (9) (8) 0.776 0.97 2.425 2.91 -40 -15 -10 0.8 0.002 0.8 1 2.5 3 0.824 1.03 2.575 3.09 +40 +15 +10 5 3 V V V V µA µA µA V A Ω VSupply = 36V Iload=1A Tjunction = 125°C 0.33 0.95 Doc ID 17713 Rev 1 19/139 Electrical specifications Table 5. Electrical characteristics (continued) Description Loop voltage accuracy Under voltage falling threshold (10) Under voltage rising threshold Under voltage hysteresis Under voltage deglitch filter Current limit protection Current limit deglitch time Current limit response time Current limit response time in UV condition Switching output rise time Switching output fall time Operating frequency Normal operating mode (no UV)(11) SelIlimit =”0” SelIlimit =”1” 3.3 2.3 50 450 200 5 5 Fosc/6 4 650 400 30 30 (10) L6460 Parameter Vloop VSW_UV_f VSW_UV_r VSW_UV_hys tprim_uv Ilimit tdeglitch tI_lim tI_limUV tr tf FSW_PWM Test condition Min Typ ±3% Max Unit 84.5 90.5 87 93 6 5 5 3.5 89.5 95.5 % % % µs A A ns ns ns ns ns kHz UV condition (12) VSupply = 36V, RLOAD = 422 Ω(13) VSupply = 36V, RLOAD = 10 Ω(13) Switching regulator controller VGS_ext ISOURCE ISINK tSINK RSUSTAIN IQ IQ_LP Gate to source voltage for external FET Source current Sink current Sink discharge pulse time Gate-source sustain resistance Output leakage current Output leakage current in “Low Power Mode” (VSWCTR_GATE VSWCTR_SRC) = 0.2V VSupply = 36V, Tjunction = 125°C VSupply = 36V, Tjunction = 125°C SelFBref = ‘00’ (8) VFBREF Switching regulator feedback controller feedback reference voltage SelFBref = ‘01’ SelFBref = ‘10’ SelFBref = ‘11’ ISWDRV_FB Vloop VSWDRV_FB pin current Loop voltage accuracy VSupply = 36V, Tjunction = 125°C -40 -5 0.776 0.97 2.425 2.91 -10 ±3% 0.8 1 2.5 3 VPump=VSupply+12V VSWCTR_GATE=0V VSWCTR_GATE = VSupply 25 20 600 650 +40 +5 0.824 1.03 2.575 3.09 +10 VPump 50 V mA mA ns Ω µA µA V V V V µA 20/139 Doc ID 17713 Rev 1 L6460 Table 5. Electrical characteristics (continued) Description Under voltage falling threshold Under voltage rising threshold Under voltage hysteresis Under voltage deglitch filter Over current threshold voltage Current limit deglitch time Current limit response time Current Limit response time in UV condition. Operating frequency Normal operating mode (no UV) (11) UV condition (12) 250 50 (14) (14) Electrical specifications Parameter VSWD_UV_f VSWD_UV_r VSWD_UV_hys tprim_uv Vovc tdeglitch tI_lim tI_limUV FSWD_PWM Power bridges RDSon1_2 RDSon3_4 IMAX1_2 IMAX3_4 Idss IQ_LP Test condition Min 84.5 90.5 Typ 87 93 6 5 300 Max 89.5 95.5 Unit % % % µs 350 mV ns 500 380 Fosc/64 900 550 ns ns kHz Bridge 1 and 2 diagonal RDSon Bridge 3 and 4 diagonal RDSon Bridge 1 and 2 operative rms current Bridge 3 and 4 operative rms current Output leakage current. Output leakage current in “low power mode” I = 1.4A, VSupply = 36V, Tjunction = 125°C I = 1A, VSupply = 36V, Tjunction = 125°C 0.6 0.85 1.1 1.65 2.5 1.5 Ω Ω A A µA µA Tjunction = 125°C VSupply = 36V, Tjunction = 125°C -50 -10 0.6 1.4 2.4 2.4 0.7 1.5 2.5 2.5 1 2 3 3 1 2 3 3 +50 +10 1.6 2.6 3.6 3.6 1.7 2.7 3.7 3.7 IOC_LS1_2 MtrXSideYILimSel[1:0]=00 MtrXSideYILimSel[1:0]=01 Low side current protection for MtrXSideYILimSel[1:0]=10 (15) bridges 1 and 2 MtrXSideYILimSel[1:0]=11 (16) A IOC_HS1_2 MtrXSideYILimSel[1:0]=00 MtrXSideYILimSel[1:0]=01 High side current protection for MtrXSideYILimSel[1:0]=10 (15) bridges 1 and 2 MtrXSideYILimSel[1:0]=11(1 6) A IOC_LS3_4 IOC_HS3_4 tfilter Low side current protection for MtrXSideYILimSel[1:0]=11 (17)(18) bridges 3 and 4(15) High side current protection for MtrXSideYILimSel[1:0]=11(1 7)(18) bridges 3 and 4(15) Current limit filter time 1.55 1.6 2 2.5 2.5 5 A A μs Doc ID 17713 Rev 1 21/139 Electrical specifications Table 5. Electrical characteristics (continued) Description Current limit delay time MtrXIlimitOffTimeY[1:0]=00 MtrXIlimitOffTimeY[1:0]=01 MtrXIlimitOffTimeY[1:0]=10 MtrXIlimitOffTimeY[1:0]=11 (19) L6460 Parameter tdelay Test condition Min Typ 5 60 120 240 480 Max Unit μs µs µs µs µs tOC_off Over current Off time tr1_2 Output rise time bridges 1 and 2 Output rise time bridges 3 and 4 Output fall time bridges 1 and 2 Output fall time bridges 3 and 4 Anti crossover rising dead time Anti crossover falling dead time Operating frequency Delay from PWM to output transition VSupply = 36V, resistive load between outputs: R= 25 Ω(20) VSupply = 36V, resistive load between outputs: R= 36 Ω(20) VSupply = 36V, resistive load between outputs: R= 25 Ω(20) VSupply = 36V, resistive load between outputs: R= 36 Ω(20) 100 180 250 ns tr3_4 50 100 200 ns tf1_2 100 180 250 ns tf3_4 tdeadRise tdeadFall FPWM tresp 50 100 100 125 300 300 Fosc/51 2 500 250 450 450 ns ns ns kHz ns Bipolar stepper circuitry VSTEPREF Voffset Reference voltage Sense comparator offset StepBlkTime = ‘00’ StepBlkTime = ‘01’ tblk Blanking time StepBlkTime = ‘10’ StepBlkTime = ‘11’ Synchronous buck regulator (bridge 3) VAUX_SW IQ IQLP Output pin voltage range (DC3x) Output leakage current (26) (8) SelStepRef =0 SelStepRef =1 0.48 0.72 -12 0.65 1 1.5 3 0.50 0.75 0.52 0.78 12 V mV µs µs µs µs 0.95 1.45 2.25 4.25 1.25 1.9 3 5.5 -1 -50 -10 VSupply +50 +10 V µA µA Tjunction = 125°C Output leakage current in “Low VSupply = 36V Power Mode” Tjunction = 125°C 22/139 Doc ID 17713 Rev 1 L6460 Table 5. Electrical characteristics (continued) Description Test condition SelFBRef = ‘00’ VFBREF Synchronous buck regulator feedback reference voltage SelFBRef = ‘01’ (21) SelFBRef = ‘10’ SelFBRef = ‘11’ IGPIO_FB Vout Iload RDSonHS Vloop VREG_UV_f VREG_UV_r VREG_UV_hys taux_UV Ilimit tdeglitch tI_lim tI_limUV tr tf tdead FREGPWM GPIO feedback pin current Output voltage range Output load current Internal high/low side RDSon Loop voltage accuracy Under voltage falling threshold Under voltage rising threshold Under voltage hysteresis Under voltage deglitch filter Current limit protection Current limit deglitch time Current limit response time Current limit response time in UV condition. Switching output rise time Switching output fall time Crossover dead time Operating frequency Normal operating mode (no UV) (11) UV condition (12) VSupply = 36V, RLOAD = 422 Ω(25) VSupply = 36V, RLOAD = 10 Ω (23) 5 10 1.6 50 (24) (24) (22) Electrical specifications Parameter Min 0.776 0.97 2.425 2.91 -15 0.8 0.002 Typ 0.8 1 2.5 3 Max 0.824 1.03 2.575 3.09 15 30 1.5 Unit V V V V µA V A Ω Tjunction = 125°C 0V≤Feedback ≤ 3V VSupply = 36V(23) VSupply = 36V Tjunction = 125°C; Iload=1A 0.6 ±3% 84.5 90.5 87 93 6 5 0.8 89.5 95.5 % % % µs 2.5 A ns 480 350 700 500 30 50 ns ns ns ns ns kHz 100 Fosc/64 Battery charger (Bridge 4) VAUX3_SW IQ Output pin voltage range (DC4x) Output leakage current (26) -1 -100 1.37 (8) VSupply +100 1.412 1.8 2.143 2.5 1.455 1.854 2.207 2.575 V µA V V V V Tjunction = 125°C SelFBRef = ‘00’ VFBRef Battery charger control loop feedback reference voltage SelFBRef = ‘01’ SelFBRef = ‘10’ SelFBRef = ‘11’ 1.746 2.079 2.425 Doc ID 17713 Rev 1 23/139 Electrical specifications Table 5. Electrical characteristics (continued) Description Test condition SelCurrRef = ‘00’ VCurrRef Battery charger control loop feedback reference current SelCurrRef = ‘01’ SelCurrRef = ‘10’ SelCurrRef = ‘11’ Vout Iload RDSon Vloop VBC_UV_f VBC_UV_r VBC_UV_hys taux_UV Ilimit tdeglitch tI_lim tI_limUV tr tf tdead FBCPWM Output voltage range Output load current Internal high/low side RDSon Loop voltage accuracy Under voltage falling threshold (28) Under voltage rising threshold Under voltage hysteresis Under voltage deglitch filter Current limit protection Current limit deglitch time Current limit response time Current limit response time in UV condition. Switching output rise time Switching output fall time Crossover dead time Operating frequency Normal operating mode (no UV) (11) UV condition (12) VSupply = 36V, RLOAD = 422 Ω (25) VSupply = 36V, RLOAD = 10 Ω (25) 5 10 100 Fosc/64 3.2 50 480 350 700 500 30 50 (28) (8) L6460 Parameter Min 0.873 1.394 1.746 2.182 1.412 0.002 Typ 0.9 1.437 1.8 2.25 Max 0.927 1.48 1.854 2.318 30 3 Unit V V V V V A Ω VSupply = 36V VSupply = 36V (27) Tjunction = 125°C; ILOAD = 1.5A 0.3 ±3% 84.5 90.5 87 93 6 5 0.4 89.5 95.5 % % % µs 5 A ns ns ns ns ns ns kHz ADC with A2DType=0 (29) IMR INL DNL OE OEDrift GE GEDrift tconv Measurement range Integral non-linearity Differential non-linearity Offset error Offset error drift Gain error Gain error drift Minimum conversion time Resolution (35) A2dType = 0 A2dType = 0 A2dType = (30)(31) 0 V3v3 ±2 ±2 ±4 ±3 ±4 ±4 55 8 V LSB LSB LSB LSB LSB LSB µs bits 0(32)(31) A2dType = 0(33) A2dType = 0 over time and temperature A2dType = 0(34) A2dType = 0 over time and temperature 24/139 Doc ID 17713 Rev 1 L6460 Table 5. Electrical characteristics (continued) Description Input sampling capacitance (36) Electrical specifications Parameter Cin Test condition Min Typ Max 4 Unit pF ADC with A2DType=1 (37) IMR INL DNL OE OEDrift GE GEDrift tconv Measurement range Integral non-linearity Differential Non-Linearity Offset error Offset error drift Gain error Gain error drift Minimum conversion time Resolution Cin Current DAC VR IOUT_OFF IFULL_ERR Pin voltage operative range (GPIO8) Output off leakage current Full scale current error Integral non-linearity for 10 and 11 ranges Differential non-linearity for 10 and 11 ranges Integral non-linearity for 01 range Differential non-linearity for 01 range Gpio[8] divider total resistance Gpio[8] divider ratio Settling time (39) (38) A2dType = 1 A2dType = 1 A2dType = 1 (30)(31) (32)(31) 0 V3v3 ±1 ±1 ±4 ±3 ±4 ±4 10 9 V LSB LSB LSB LSB LSB LSB µs bits A2dType = 1 (33) A2dType = 1 over time and temperature A2dType = 1 (34) A2dType = 1 over time and temperature Input sampling capacitance (36) 4 pF 0.7 -1 -15 5.5 +1 +15 V µA % of IFULL typ DacValue[5:0] = 000000 DacRange[1:0] =xx DacValue[5:0] = 111111 INL10_11 DNL10_11 INL01 DNL01 RCurrDac_res RCurrDac_ratio tset ±2 ±2 ±1 ±1 45 3/5 5 LSB LSB LSB LSB kΩ µs Operational amplifier (40) VGPIO_SPI VICM VOUT_MAX Operational amplifier supply voltage range Input common mode voltage range Output voltage ILOAD =± 1mA 3.15 0 0.1 3.3 3.45 VGPIO_ SPI V V V 3.2 Doc ID 17713 Rev 1 25/139 Electrical specifications Table 5. Electrical characteristics (continued) Description Test condition OpxRef[1:0]=00 OpxRef[1:0]=01 OpxRef[1:0]=10 OpxRef[1:0]=11 VICM=1.65V ILOAD= 0mA Min 0.97 1.6 1.94 2.425 90 80 ILOAD= ±6mA VICM=1.65V -150 -500 -5 Cload=100pF VICM=1.65V Rload=330 Ω to VGPIO_SPI Vout=1.65V 12 Iload= 0 CLOAD=100pF 1.3 20 1.75 2 10 110 90 150 500 5 Typ 1 1.65 2 2.5 Max 1.03 1.7 2.06 2.575 L6460 Parameter Unit VOp1PlusRef VOp2PlusRef Operational amplifier 1 and 2 reference voltage V Avd CMRR PSRR I in _offs I in _bias V in _offs GBWP Iout Ishort_max SR Open loop gain Common mode rejection ratio Power supply rejection ratio Input offset current Input bias current Input offset voltage Gain bandwidth product Output current Short circuit current Slew rate dB dB dB nA nA mV MHz mA mA V/µs Operational amplifier used as comparator (40) (41) VOUT_MAX tOFF Output voltage Turn off propagation delay Iload =± 10mA VCM = 1.65V Δ Vi = -/+ 20mV CLOAD=100pF (42)(43) VCM = 1.65V Δ Vi = -/+ 20mV CLOAD=100pF (42)(43) VCM = 1.65V Δ Vi = -/+ 20mV CLOAD=100pF (42)(43) VCM = 1.65V Δ Vi = -/+ 20mV CLOAD=100pF (42)(43) 0.3 0.6 2.9 1 V µs tFALL Fall time 0.15 0.4 µs tON Turn on propagation delay 0.25 0.5 µs tRISE Rise time 0.2 0.4 µs Low power switch VPSW VOUT_MAX RDSon ILIMIT tdeglitch Input voltage range Output voltage Switch RDSon resistance Current limit Current limit deglitch time Iload=100mA 150 50 0.6 250 2.4 3.6 VGPIO_ SPI V V Ω mA ns 1 350 26/139 Doc ID 17713 Rev 1 L6460 Table 5. Electrical characteristics (continued) Description Current limit response time Max load capacitance Turn on propagation delay VGPIO_SPI=3.3V ILOAD=1mA CLOAD=100pF(44) VGPIO_SPI=3.3V ILOAD=1mA CLOAD=100pF(44) Test condition Min Electrical specifications Parameter tI_lim CLOAD tON Typ Max 650 2.5 Unit ns µF ns 450 650 tOFF Turn off propagation delay 250 450 ns Interrupt controller tPULSE tINTFILT Pulse duration Filter time 16*Tosc 200 µs ns GPIO[0], GPIO[1], GPIO[2], GPIO[3], GPIO[4], GPIO[6] VIH VIL VHYS VOL ILEAKAGE tDELAY High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Delay from serial write to pin Low IOUT = 15mA 0 ≤ Vout ≤ V3v3 CLOAD =50 pF(45) -1 0.15 0.22 0.5 1 500 1.6 0.8 V V V V µA ns GPIO[5], GPIO[7], GPIO[9], GPIO[10], GPIO[11], GPIO[12], GPIO[13], GPIO[14] VIH VIL VHYS VOL VOH ILEAKAGE tDELAY GPIO[8] VIH VIL VHYS VOL ILEAK_0 ILEAK_1 High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage Leakage current Leakage current IOUT = 15mA, EnGpio8DigIn=0, 0 ≤ Vout ≤ 5V EnGpio8DigIn=1, 0 ≤ Vout ≤ 5V -1 -1 0.13 0.22 0.4 1 5 1.6 0.8 V V V V µA µA High level input voltage Low level input voltage Input voltage hysteresis Low level output voltage High level output voltage Leakage current Delay from serial write to pin low IOUT = 15mA IOUT = 5mA 0 ≤Vout ≤ V3v3 CLOAD =50 pF(45) 2.75 -1 1 500 0.15 0.22 0.5 1.6 0.8 V V V V V µA ns Doc ID 17713 Rev 1 27/139 Electrical specifications Table 5. Electrical characteristics (continued) Description Test condition ADChannelX[4:0] =10001 and bit EnDacScale=0 CLOAD =50 pF(45) Min Typ Max L6460 Parameter Unit IAD A/D path absorbed current Delay from serial write to pin low -1 1 µA tDELAY SPI interface (40) VIH VIL VHYS VOH VOL tSCLK tSCLK_rise tSCLK_fall tSCLK_high tSCLK_low tnSS_setup tnSS_hold tnSS_min tMOSI_setup tMOSI_hold tMISO_rise tMISO_fall tMISO_valid tMISO_disable CLOAD 500 ns High level input voltage Low level input voltage Input voltage hysteresis High level output voltage Low level output voltage SCLK period SCLK rise time SCLK fall time SCLK high time SCLK low time nSS setup time nSS hold time nSS high minimum time MOSI setup time MOSI hold time MISO rise time MISO fall time MISO valid from clock low MISO disable time MOSI maximum load (46) (46) (46) 1.6 0.8 0.15 -10mA,(47) 10mA,(47) 62.5 2 2 20 20 10 10 30 10 10 2.75 0.4 0.22 V V V V V ns ns ns ns ns ns ns ns ns ns 9 9 ns ns ns ns pF IOUT = IOUT = CLOAD=50pF(48) CLOAD=50pF (48) 0 0 15 15 200 1. This value is useful to define the voltage rating for external capacitor to be connected from VSupply to VSupplyInt. 2. This typical value is only intended to give an estimation of the current consumption when L6460 is configured in simple regulators mode (see following Chapter 8.6.4) at the end of the start up sequence and with no load on regulators. This typical value allows a raw choose of the external resistor but the definitive choose must be done according to the recommendations on Chapter 4.1). 3. Measured between 10% and 90% of output voltage transition. 4. Measured from a fault detection to 50% of output voltage transition. 5. Current is defined to be positive when flowing into the pin. 6. Load regulation is calculated at a fixed junction temperature using short load pulses covering all the load current range. This is to avoid change on output voltage due to heating effect. 7. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VLINmain_FB). 8. Default state. 9. The regulated voltage can be calculated using the formula: VSWmain_OUT = VFBREF *(Ra+Rb)/Rb. 28/139 Doc ID 17713 Rev 1 L6460 Electrical specifications 10. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSW_main_FB). 11. This condition is intended to simulate an extra current on output. 12. This condition is intended to simulate a short circuit on output. 13. Rise and fall time are measured between 10% and 90% VSWmain output voltage. 14. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VSWDRV_FB). 15. The current protection values must be intended as a protection for the chip and not as a continuous current limitation. The protection is performed by switching off the output bridge when current reaches values higher than the IOC max. No protection could be guaranteed for values in the middle range between IMAX and IOC 16. In this cell X stands for 1 or 2, Y stands for A or B 17. In this cell X stands for 3 or 4, Y stands for A or B 18. The current protection thresholds for Bridge 3 and 4 are not selectable so only the max current value (MtrXSideYILimSel[1:0]= 11) is available. 19. Overcurrent Off time can be configured using SPI. 20. Rise and fall time are measured between 10% and 90% of DC output voltage. With device in full bridge configuration (resistive load between outputs). 21. Default state for Aux1 22. Default state for Aux2 23. The regulated voltage can be calculated using the formula: VAUX_SW = VFBREF *(Ra+Rb)/Rb. 24. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (GPIO1 and/or GPIO2) 25. Rise and fall time is measured between 10% and 90% of output voltage. 26. The external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 27. The regulated voltage can be calculated using the formula: VAUX3_SW = VFBREF *(Ra+Rb)/Rb. 28. Undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (VREF_FB). 29. The definition of LSB for this table is LSB=IMRmax/(27.5-1). 30. Integral Non Linearity error (INL) is defined as the maximum distance between any point of the ADC characteristic and the “best straight line” approximating the ADC transfer curve. 31. The ADC ensures monotonic characteristic and no missing codes. 32. Differential nonlinearity error (DNL) is defined as the difference between an actual step width and the ideal width value of 1 LSB. 33. Offset error (OE) is the deviation of the first code transition (000...000 to 000...001) from the ideal (i.e. GND + 0.5 LSB). 34. Gain error (GE) is the deviation of the last code transition (111...110 to 111...111) from the ideal (V3v3 - 0.5 LSB), after adjusting for offset error. 35. Please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is reduced when the ADC is used in the 8- bit resolution mode. 36. Actual input capacitance depends on the pin that must be converted. 37. The definition of LSB for this table is LSB=IMRmax/(29-1). 38. All parameters are guaranteed in the range between VOL and VR Max. 39. Measured from DacValue[5:0] change in SPI interface. 40. VGPIO_SPI = 3.3 V unless otherwise specified 41. In this section reports the operational amplifier parameters that change when used as comparator. 42. ΔVi is the differential voltage applied to input pins across the common voltage VCM. 43. Measured between 50% of input and output signal. 44. Time measured from change in SPI interface to 50% of external pin transition. 45. Measured between nSS rising edge and 50% of Vout. 46. Specification applies to nSS, SCLK and MOSI pins. 47. Current is considered to be positive when flowing towards the IC 48. These times are measured at the pin output between specified VOH and VOL. Doc ID 17713 Rev 1 29/139 Internal supplies L6460 4 Internal supplies L6460 includes three internal regulators used to provide a regulated voltage to internal circuits. The internal regulators are the following: - VSupplyInt regulator. - Charge pump regulator. - V3v3 regulator. 4.1 VSupplyInt regulator VSupplyInt is the output of an internal regulator used to supply some internal circuits. This regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected to this pin (preferably towards VSupply pin), recommended value is in the range 80 ÷ 120 nF. Figure 3. VSupplyInt pin Vsupply VsupplyInt IS_Int_TYP L6460 internal circuits L6460 GND The VSupplyInt pin may also be externally connected to VSupply pin by means of an external resistor REXT: this allows REXT, particularly when VSupply is at the max values of the operative supply range, to dissipate power that otherwise would be dissipated inside the chip. The choice of the optimal resistor depends on the application since it is strictly depending on both VSupply and the current used inside the chip (that is changing with the chosen configuration). REXT could be chosen by applying this formula: REXT = (VSupply min - VS_Int max)/(IS_Int max). IS_Int max is depending from the chosen configuration and represents the total current needed by the circuits connected to this pin. For example, with VSupply = 32 V and IS_Int = 12 mA a typical resistor value is 1 kΩ. 30/139 Doc ID 17713 Rev 1 L6460 Internal supplies 4.2 Charge pump regulator L6460 implements a charge pump regulator to generate a voltage over VSupply.This voltage is used to drive internal circuits and the external FET driver and cannot be used for any other purpose. This circuit is always under the supervisory circuit control, so no regulator can start before the VPump voltage reaches its undervoltage rising threshold. If VPump voltage falls down below its under voltage falling threshold, all the regulators will be switched off. The charge pump circuit is disabled when L6460 is in “low power mode”. Figure 4. Charge pump block diagram VSupplyInt VSupply CBOOST VPump CPH for VSupply lower than 15V , external diodes are required CFLY EnVPump Driver M2 M1 CPL + CLKBOOST Ref An example of capacitors value is: CFLY = 100 nF and CBOOST = 1 µF 4.3 V3v3 regulator V3v3 is the output of an internal regulator used to supply some low voltage internal circuits. This regulator is not intended to provide external current so it must not be used to supply external loads. An external capacitor must always be connected from this pin to GND, recommended value is in the range 80 ÷ 120 nF. Doc ID 17713 Rev 1 31/139 Supervisory system L6460 5 Supervisory system The supervisory circuitry monitors the state of several functions inside L6460 and resets the device (and other ICs if connected to nRESET pin) when the monitored functions are outside their normal range. Supervisory circuitry can be divided into three main blocks: – – – Power on reset (POR) generation circuitry. nRESET (nRST_int) generation circuitry. Thermal shut down (TSD) generation circuitry. POR circuitry monitors the voltages that L6460 needs to guarantee its own functionality; nRESET circuitry controls if L6460’s main voltages are inside the normal range; TSD is the thermal shut down of the chip in case of overheating. 5.1 Power on reset (POR) circuit Power on reset circuit monitors VSupply, and V3V3 voltages. The purpose of this circuit is to set the device is in a stable and controlled status until the minimum supply voltages that guarantee the device functionality are reached. The output signal of this circuit (in the following indicated as “POR”) becomes active when VSupply or V3V3 go under their falling threshold. When POR output signal is active, all functions and all flags inside L6460 are set in their reset state; once POR signal comes back from off state (meaning monitored voltages are above their rising threshold), the power up sequence is re-initialized. 5.2 nRESET generation circuit The nRESET circuit monitors VSupply, VSupplyInt, VPump, VGPIO_SPI and all system regulators (VSystem) voltages. The purpose of this circuit is to prevent the device functionality until the monitored voltages reach their operative value (please note that V3v3 is monitored by POR, so it must be above its minimum value, otherwise nRESET circuit is not active). This circuit generates an internal reset signal (in the following indicated as “nRST_int”) that will also be signaled to external circuits by pulling low the nRESET pin. The signal nRST_int becomes active in the following cases: 1. When one of the following voltages is lower than its own under voltage threshold: – – – – 2. 3. 4. VSupply and VSupplyInt. VPump. VSystem (all switching or linear system regulators voltages). VGPIO_SPI. When watchdog timer counter (see Chapter 6) elapse the watchdog timeout time (only if watchdog function is enabled). When L6460 is in “Low Power mode”. When EnExtSoftRst bit in SoftResReg register is at logic level = “1” and a “SoftRes” command is applied (see SoftResReg register description in Chapter 25). When an nRST_int event is caused by above cases, the nRESET pin will stay low for a “stretch” time that starts from the moment that nRST_int signal returns in the operative 32/139 Doc ID 17713 Rev 1 L6460 Supervisory system state. This stretch time can be selected by setting the ID[1:0] bits in the SampleID register according to following table. Table 6. Stretch time selection Selected stretch time ID[1] 0 0 1 1 ID[0] Typ 0 1 0 1 16ms 32ms 48ms 64ms Default state Note When nRST_int becomes active (logic level = “0”) it sets in their reset state some of the functions inside L6460. The main functions that will be reset by nRST_int signal are the following: – – – – – – – – – Serial interface will be reset and will not accept any other command. The bridges 1 and 2 will place their outputs in high impedance and PWM and direction signals will be reset. AD converter will be powered off. GPIOs will be powered off. Current DAC will be powered off. Operational amplifiers will be powered off. Watchdog count will be reset (while Watchdog flags won’t be reset). Interrupt controller will be powered off. Digital comparator will be powered off. Additionally the system regulators will be powered off but only if the voltage that caused the nRST_int event is checked before the system regulator in the power up sequence. This means that: – – – all system regulators will be powered off if nRST_int is caused by VSupply, VSupplyInt, VPump (and also if V3v3 causes a POR); no one of the system regulators will be powered off if nRST_int is caused by VGPIO_SPI; only the system regulators that follows the system regulator that caused the nRST_int in power up sequence will be powered off. Doc ID 17713 Rev 1 33/139 Supervisory system Figure 5. nReset generation circuit t nRST_int L6460 Filter UV comparator UV Filter V SupplyUV V SupplyInt UV comparator UV Filter V SupplyIntUV Low Power Mode V Supply V Pump UV comparator UV Filter nRESET pin V PumpUV nGateCtrl nRESET pin Driver V SysX UV comparator UV Filter SystemregulatorsUV POR WD_En_nRst V SysY UV comparator UV Filter to SPI Note: All regulator voltages included in power up sequence (VSysX – VSysY in Figure 5) will be considered as nRESET circuit voltages. 34/139 Doc ID 17713 Rev 1 WatchDog Elapsed L6460 Supervisory system 5.3 Thermal shut down generation circuit The third component of the supervisory circuit is the thermal shut down generation circuit. This circuit generates two different flags depending on the IC temperature: – – the “TSD” flag indicates that the IC temperature is greater than the maximum allowable temperature. the “Warm” flag, that can be read using serial interface, becomes active at a lower temperature respect to TSD signal, therefore it can be used to prevent the IC from reaching over temperature. When a TSD event occurs, L6460 will enter in the reset state placing the bridges in high impedance and turning off all regulators and other circuits until the internal temperature decreases below the Warm temperature. At this point, L6460 will restart the power up sequence and TSD bit will be set and will be readable as soon as L6460 will come out from the reset state. This TSD bit can be reset in three ways: – – – by writing a logic level ‘1’ in the ClearTSD bit in the ICTemp register (see Chapter 24); by a POR event; by entering in “Low Power Mode”. The Warm bit, set by L6460 when IC is working over the warming temperature, can be read using the SPI interface. Once this bit is set it can be reset in three ways: – – – by writing a logic level ‘1’ in the ClearWarm bit; by a POR event; by entering in “Low Power Mode”. The thermal sensor voltage can be converted using the internal A/D: this way the microcontroller can directly measure the IC temperature. To avoid unwanted commutation especially when temperature is near the thresholds, the output signal is filtered for both TSD and Warm. Doc ID 17713 Rev 1 35/139 Watchdog circuit L6460 6 Watchdog circuit The Watchdog timer can be used to reset L6460 if it is not serviced by the firmware that can periodically write at logic level “1’ the ClrWDog bit in the WatchDogStatus register. This circuit is disabled by default; firmware can enable it by setting at logic level ‘1’ the WDEnable bit in the WatchDogCfg register. When the Watchdog timeout event happens, L6460 sets to ‘1’ a latched bit WDTimeOut in theWatchDogStatus register that can be read using SPI interface; once this bit is set it can be cleared in three ways: – – – by writing a ‘1’ in the WDClear bit in the WatchDogStatus register. by writing a ‘1’ in the SoftReset bit in the WatchDogStatus register. by a POR event. The Watchdog function includes also a warning bit WDWarning to indicate, via serial interface or via the circuit called Interrupt Controller (see Chapter 21) that the watchdog is near to its timeout; this bit is asserted to logic level “1” exactly one watch dog clock period (WD_Tclk) before the watchdog timeout happens. Firmware can enable the WDTimeOut signal to cause an “nRst_int” event by setting to logic ‘1’ the WDEnnRst bit. Figure 6. Watchdog circuit block diagram WDdelay[3:0] WDEnable ClrWDog To nRSTint generation circuit WD_req_nRst WD_En_nRst Fosc Frequency divider WD_clk Watchdog counter WDTimeOut WDWarning To SPI The watchdog timeout has an imprecision of maximum one WD_Tclk. The effective programmed WD time is changed in the register only when the watchdog circuit is serviced by firmware with ClrWDog bit. At this time the watchdog timer is reset and the new value of the WD delay value is loaded. The watchdog timer can be programmed to generate different timeouts using the WDdelay[3:0] bits in the WatchDogCfg register according to following table. 36/139 Doc ID 17713 Rev 1 L6460 Table 7. Watchdog timeout specifications Watchdog circuit WD timeout WDdelay[3:0] Typ 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 8*WD_Tclk 9*WD_Tclk 10*WD_Tclk 11*WD_Tclk 12*WD_Tclk 13*WD_Tclk 14*WD_Tclk 15*WD_Tclk 16*WD_Tclk 17*WD_Tclk 18*WD_Tclk 19*WD_Tclk 20*WD_Tclk 21*WD_Tclk 22*WD_Tclk 23*WD_Tclk Doc ID 17713 Rev 1 37/139 Internal clock oscillator L6460 7 Internal clock oscillator L6460 includes a free running oscillator that does not require any external components. This circuit is used to generate the time base needed to generate the internal timings; the typical frequency is 16 MHz. The oscillator circuit starts as soon as the IC exits from the power on reset condition and it is stopped only when in “low power mode”. 38/139 Doc ID 17713 Rev 1 L6460 Start-up configurations 8 Start-up configurations L6460 start-up configuration is selected by setting in different states the GPIO[0], GPIO[3] and GPIO[4] pins. Each of these is a three state input pin and is able to distinguish among the following situations: Table 8. Possible start-up pins state symbol Pin condition Shorted to ground Shorted to V3v3 pin Floating State symbol 0 1 Z Note: “Shorted” means: R≤1KOhm; “Z” means: R≥10KOhm, C≤200pF 8.1 Operation modes When VSupply voltage is applied to L6460, the internal regulator V3v3, used to supply the logic circuits inside the device, starts its functionality. When it reaches its final value, L6460 enables the GPIO[0] pin state read circuitry, and, after a time TpinSample, it will sample the GPIO[0] state. If it is found to be in high impedance, L6460 does not consider GPIO[3] and GPIO[4] pins state and starts its “Basic device” mode sequence. If GPIO[0] is found to be connected to ground or to V3v3, L6460 checks the state of GPIO[3] and GPIO[4] pins to select its start-up configuration. The possible configurations can be classified in four “Major” modes: 1. 2. 3. 4. Basic device. Slave device. Master device. Single device. Hereafter is reported the correspondence table between GPIO[X] state and L6460 configurations. Doc ID 17713 Rev 1 39/139 Start-up configurations Table 9. Start-up correspondence Pin state(1) Major mode GPIO[0] Z 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 GPIO[3] X 0 0 0 Z Z Z 1 1 1 0 0 0 Z Z Z 1 1 1 GPIO[4] X 0 Z 1 Single 0 Z 1 0 Z 1 Master 0 Z 1 0 Z 1 Slave 0 Z 1 Simple regulator Bridge + VEXT (3) Secondary regulators. Simple regulator Bridge + VEXT (3) Secondary regulators Bridge Primary regulator Regulators Simple regulator Bridge + VEXT (3) Secondary regulators Bridge Primary regulator Regulators Basic Bridge Primary regulator Regulators Minor mode(2) L6460 1. “X” means “don’t care”. 2. The description of these modes is in the following Chapter 8.6 3. VEXT is the regulator output voltage obtained using the switching regulator controller with external FET. 8.2 Basic device mode The basic device mode is selected by leaving the GPIO[0] pin floating. In this mode L6460 doesn’t use GPIO[3] and GPIO[4] as configuration pins, leaving them free for other uses. When in this mode the regulators included in the start up sequence (except VSWmain) are considered as system regulators and they start in the following sequence: 1. 2. 3. 4. Auxiliary switching regulator1 (VAUX1_SW). Auxiliary switching regulator2 (VAUX2_SW). Main linear regulator (VSWmain). Main switching regulator (VSWmain) (Not system regulator). 40/139 Doc ID 17713 Rev 1 L6460 Start-up configurations 8.3 Slave device mode In slave device mode, L6460 consider the nAWAKE pin as an input enable. Since this is now a digital pin, the current pull up source inside the nAWAKE circuit is disabled. At the startup, if the nAWAKE pin is found to be low for a period higher than tAWAKEFILT, L6460 enters directly in the “Low Power mode”; when nAWAKE pin is pulled high for a period higher than tAWAKEFILT, L6460 begins its start up procedure. 8.4 Master device mode In master device mode, L6460 begins its start up procedure without waiting for any external enable signal and it uses GPIO[5] pin to drive the nAWAKE pin of Slave devices. During the whole start up time, it forces its GPIO[5] pin at logic level “0” in order to maintain all slave devices in “Low Power mode” as previously described. When start up operations are completed, L6460 forces the GPIO[5] output to logic level “1” to enable the slave devices and keeps GPIO[5] output at high level until it senses an under-voltage on any of its System regulators. If firmware writes in the PwrCtrl register to set Master L6460 in “Low Power mode” it immediately forces GPIO[5] output to logic level “0” to force the slave devices to enter in “Low Power mode”, then it waits for TMASTWAIT time and it starts its “Low Power mode” sequence. 8.5 Single device mode In single device mode, the device behaves similarly to master device mode but: 1. 2. It doesn’t use the GPIO[5] pin to drive slave devices. It doesn’t wait for TMASTWAIT before entering in “Low Power mode”. 8.6 Sub-configurations for slave, master or single device modes Each slave, master or single device modes can be divided in other minor modes depending on the start-up sequence needed for L6460 internal regulators. Unless otherwise specified, in all the following modes the regulators included in the start up sequence are considered system regulators and they start in the sequence indicated. 8.6.1 Bridge mode In this configuration bridges 3 and 4 are not used as regulators and therefore can be configured by the firmware in any of their possible bridge modes. When in this mode the power-up sequence is: 1. 2. Main switching regulator (VSWmain). Main linear regulator (VLINmain). Doc ID 17713 Rev 1 41/139 Start-up configurations L6460 8.6.2 Primary regulator mode (KP) In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence (VAUX2_SW) is not considered a system regulator. When in this mode the power-up sequence is: 1. 2. 3. Auxiliary switching regulator1 (VAUX1_SW). Main switching regulator (VSWmain) together with main linear regulator (VLINmain). Auxiliary switching regulator2 (VAUX2_SW) (Not system regulator). 8.6.3 Regulators mode In this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators, but the start up sequence is different previous one. When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VSWmain). Auxiliary switching regulator1 (VAUX1_SW) Auxiliary switching regulator2 (VAUX2_SW) 8.6.4 Simple regulator mode (KT) Also in this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. The last regulator in the sequence (VSWmain) is not considered a system regulator. When in this mode the power-up sequence is: 1. 2. 3. 4. Auxiliary switching regulator1 (VAUX1_SW). Auxiliary switching regulator2 (VAUX2_SW) Main linear regulator (VLINmain) Main switching regulator (VSWmain) (not system regulator). 8.6.5 Bridge + VEXT mode In this configuration bridges 3 and 4 are not used as regulators and the regulator obtained using the switching regulator controller (VSWDRV) is included in start-up. When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VSWmain). Switching regulator controller regulator (VSWDRV). Main linear regulator (VLINmain). 42/139 Doc ID 17713 Rev 1 L6460 Start-up configurations 8.6.6 Secondary regulators mode In this configuration, bridge 3 is configured as a single synchronous switching regulator using its two half bridges in parallel (VAUX_(1//2)SW). When in this mode the power-up sequence is: 1. 2. 3. Main switching regulator (VSWmain). Auxiliary switching regulator (VAUX(1//2)_SW). Main linear regulator (VLINmain). Doc ID 17713 Rev 1 43/139 Power sequencing L6460 9 Power sequencing As soon as VSupply and VSupplyInt are above their power on reset level, L6460 will start the charge pump circuit; once VPump voltage reaches its under voltage rising threshold, L6460 begins a sequence that starts the regulators considered system regulators. A regulator is considered a System regulator if: – – – It has to start in on state without any user action. It is included in the power-up sequence. Its under-voltage event is considered by L6460 as an error condition to be signaled through nRESET pin. Once VSupply and VSupplyInt, VPump and all the system regulators are over their under voltage rising threshold, L6460 enters in the normal operating state, that will release nRESET pin and will wait for SPI commands. L6460 will reduce the noise introduced in the system by switching out of phase all its power circuits (switching regulators, bridges and charge pump). The L6460's startup sequence of operation is the following: – – – – – – – start V3v3 internal linear regulator sample startup configuration wait enable if slave device start charge pump start system regulators (see order in Section 8.6) if master send enable to slave device wait until VGPIO_SPI becomes ok 44/139 Doc ID 17713 Rev 1 L6460 Power saving modes 10 Power saving modes Saving power is very important for today platforms: L6460 implements different functions to achieve different levels of power saving. Sections here below describe these different power saving modes. 10.1 Standby mode Almost all low voltage circuitry inside L6460 are powered by V3v3 internal regulator; this regulator is a linear regulator powered by VSupplyInt. This means that all the current provided by V3v3 regulator is directly coming from VSupplyInt and therefore the total power consumption is: Low voltage power = VSupply* IV3v3. because VSupplyInt is feeded by VSupply, directly or with a resistor in series. This power could be reduced by using a switching buck regulator to supply V3v3: in this case, assuming the buck regulator efficiency near to 100%, the dissipated power would become: Low voltage power ≈ 3.3V * IV3v3. To achieve this result there is the need to switch off the internal V3v3 linear regulator and to use an additional pin to provide a 3.3 V supply to internal circuits. L6460 can do this by using the low voltage switch implemented on GPIO6 pin. This switch internally connects VGPIO_SPI voltage to GPIO6 output so, by externally connecting GPIO6 to V3v3 pin, the VGPIO_SPI voltage can be provided to low voltage circuitry inside L6460. Figure 7. Standby mode function description VSupplyInt VGPIOSpi StdByMode Power Switch 1 GPIO6 External connection 3.3V 3.3 V 1.9 V 0 + 1 V3v3 Regulator - The StdByMode bit used to switch off V3v3 and switch on the power switch can be set to ‘1’ by writing the standby command in the StdByMode register. L6460 exits standby mode if a reset event happens or “Low Power mode” is selected. Because all internal low voltage circuitry powered by V3v3 are designed to work with a 3.3V voltage rail, when the standby mode is used, VGPIO_SPI is requested to be at 3.3V. Doc ID 17713 Rev 1 45/139 Power saving modes L6460 10.2 Hibernate mode L6460’s hibernate mode allows the firmware to switch off some (or all) selected System Regulators leaving in on state only those necessary to resume L6460 to operative condition when waked-up by an external signal. Hibernate mode is selected when the firmware writes the command word in the HibernateCmd register. When in hibernate mode L6460 will force regulators in the state (on/off) selected by the firmware by writing in the HibernateCmd register and will force nRESET pin low. The exiting from hibernate mode is achieved by forcing at low level nAWAKE pin (or GPIO5 pin if L6460 is in Slave mode); L6460 will also exit from hibernate mode if an undervoltage event happens on VSupply, VSupplyInt, VPump or V3v3. When the exit from hibernate mode is due to an external command, L6460 sets to ‘1’ the bit HibModeLth in the HibernateStatus register. 10.3 Low power mode When in normal operating mode, the microcontroller can place L6460 in “Low Power mode”. In this condition L6460 sets all bridges outputs in high impedance, powers down all regulators (including system regulators and charge pump) and disables almost all its circuits including internal clock reducing as much as possible power consumption. The only circuits that remain active are: – – – – V3V3 internal regulator. nAWAKE pin current pull-up. nRESET pin that will be pulled low. POR circuit. The entering in low power mode is obtained in different ways depending if L6460 is configured as slave device or not. When L6460 is configured as slave device the low power mode is directly controlled by nAWAKE pin that acts as an enable: if this pin is low for a time longer then tAWAKEFILT, Low Power mode is entered; if this pin is high L6460 exits from Low Power mode. In all other start-up configurations, Low Power mode is entered by writing a Low Power mode command in the PowerModeControl register; once L6460 is in Low Power mode it starts checking the nAWAKE pin status: if it is found low for a time longer than tAWAKEFILT, L6460 exits from Low Power mode and restarts its startup sequence. When the nAWAKE pin is externally pulled low, the “AWAKE” event is stored and it is readable through SPI. L6460 will also exit from Low Power mode if a POR event is found. Note: When in “Low power mode” VSupply is monitored only for its power on reset level. 10.4 nAWAKE pin At the start up, before L6460 has identified the required operation mode (see Chapter 8), a current sink IINP is always active to pull down nAWAKE pin. As soon as the operation mode (basic, slave, master or single device) is detected, the functionality of nAWAKE pin will be different. 46/139 Doc ID 17713 Rev 1 L6460 Power saving modes If L6460 is not configured as slave device a current source IOUT will be active on this pin, while the current sink IINP will be disabled. If L6460 is configured as a Slave device, the current sink IINP will be active until nAWAKE pin is detected high for the first time; after that both current sources IINP and IOUT will be disabled and the nAWAKE pin can be considered as a digital input. Here below is reported the nAWAKE pin simplified schematic. Figure 8. nAWAKE function block diagram V 3v3 SlaveMode I OUT AWAKE_req AWAKE nAWAKE seen high for the first time after start up. I INP Doc ID 17713 Rev 1 47/139 Linear main regulator L6460 11 Linear main regulator The linear main regulator is directly powered by VSupply voltage and it is one of the regulators that L6460 could consider as a system regulator. This means that the voltage generated by this regulator is not used to power any internal circuit, but L6460 will check that the feedback voltage VLINmain_FB is in the good value range before enabling all its internal functions. When an under-voltage event (with a duration longer than period tprim_uv defined by the deglitch filter) is detected during normal operation, L6460 will enter in reset state and it will signal this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal blocks. Here are summarized the primary features of the regulator: – – – – – Regulated output voltage from 0.8V to VSupply-2V with a maximum load of 10mA. Band gap generated internal reference voltage. Short circuit protected (output current is clamped to 22mA typ). Under voltage signal (both continuous and latched) accessible through serial interface. Low power dissipation mode. The internal series element is a P-channel MOS device. The voltage regulator will regulate its output so that feedback pin equals VLINmain_FB, therefore the regulated voltage can be calculated using the formula: VLINmain_OUT = VLINmain_ref *(Ra+Rb)/Rb Figure 9. Linear main regulator V supply Body Diode V LINmain_OUT Driver Cc + - Ra V LINmain_FB V LINmain_ref Rb To extend the output current capability this regulator can be used as a controller for an external active component able to provide higher current (i.e. a Darlington device); the external power element allows the handling of an higher current since it dissipates the power externally (the power dissipated by a linear driver supplied at VSupply and regulating a voltage VLINmain_OUT with an output current IOUT is about: Pd= (VSupply-VLINmain_OUT)*IOUT. 48/139 Doc ID 17713 Rev 1 L6460 Linear main regulator Figure 10. Linear main regulator with external bipolar for high current V supply Body Diode VLINmain_OUT Driver Cload + VLINmain_FB VLINmain_Ref Ra Rb Whichever configuration is used (regulator or controller), a ceramic capacitor must be connected on the output pin towards ground to guarantee the stability of the regulator; the value of this capacitance is in the range of 100 nF to 1 µF depending on the regulated voltage; ● ● ● ● VLINmain_OUT = 0.8 V --> 1 µF 0.8V< VLINmain_OUT < 2.5 V --> 0.68 µF 2.5V= VLINmain_OUT 5 V --> 0.33 µF VLINmain_OUT > 5 V --> 0.1 F When this regulator is disabled, the whole circuit is switched off and the current consumption is reduced to a very low level both from V3v3 and from VSupply. When in this condition, the output pin is pulled low by an internal switch. Doc ID 17713 Rev 1 49/139 Main switching regulator L6460 12 Main switching regulator Main switching regulator is an asynchronous switching regulator intended to be the source of the main voltage in the system. It implements a soft start strategy and could be a system regulator so even if its output voltage VSWmain is not used to power any internal circuit, L6460 will check that it is in the good value range before enabling all its internal functions. When L6460 detects a system regulator under-voltage event with a duration longer than the period defined by the deglitch filter (tprim_uv), it will enter in reset state signaling this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal block (e.g. bridges, GPIOs, …). The output voltage will be externally set by a divider network connected to feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to choose between four feedback voltage references (and, as a consequence, four under-voltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef bits in the MainSwCfg register. Here after are summarized the primary features of this regulator: – – – – – – – Internal power switch. Soft start circuitry to limit inrush current flow from primary supply. Internally generated PWM (250 kHz switching frequency). Nonlinear pulse skipping control. Protected against load short circuit. Cycle by cycle current limiting using internal current sensor. Under voltage signal (both continuous and latched) accessible through SPI. When L6460 is in “low power mode”, this regulator will be disabled. In order to save external components and power when using two or more L6460 IC’s on the same board, the primary switching regulator can be disabled by serial interface. Care must be paid using this function because an under-voltage on this regulator, as previously seen, will be read as a fault condition by L6460. 12.1 Pulse skipping operation Pulse skipping is a well known, non linear, control strategy used in switching regulators. In this technique (see Figure 11) the feedback comparator output is sampled at the beginning of each switching cycle. At this time, if the sampled value shows that output voltage is lower than requested one, the complete PWM duty cycle is applied to power switch; otherwise no PWM is applied and the switching cycle is skipped. Once PWM is applied to power element only a current limit event can disable the power switch before the whole duty cycle is finished. 50/139 Doc ID 17713 Rev 1 L6460 Figure 11. Main switching regulator functional blocks Main switching regulator VSupply Current Sense Charge pump Voltage High Side Driver VSWmain_SW La Ra C Voltage From Central Logic Control Logic Regulator Freq Loop Control + VSWmain_FB Rb Regulator Ref Under voltage flag Filter To Central Logic + Under voltage Threshold In pulse skipping control the duty cycle must be chosen by the user depending on supply voltage and output regulated voltage. Therefore the switching regulator has 4 possible duty cycles that can be changed by writing the VmainSwSelPWM bits in the MainSwCfg register according to following Table 10. Table 10. Main switching regulator PWM specification Duty cycle value Comments VmainSwSelPWM[1:0] 00 01 10 11 Typical 12% 15% 26% 63.5% Default state MainSwCfg register The output current is limited to a value that can be set by means of SelIlimit bit in the MainSwCfg register according to following Table 11. Table 11. Main switching regulator current limit Current limit (min) 3.3A 2.3A Comments Default state SelIlimit 0 1 Doc ID 17713 Rev 1 51/139 Switching regulator controller L6460 13 Switching regulator controller This circuit controls an external FET to implement a switching buck regulator using a non linear pulse skipping control with internally generated PWM signal. The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four undervoltage thresholds) using serial interface. The feedback reference voltage is selected by writing the SelFBRef bits in the SwCtrCfg. This regulator is switched off when L6460 is powered up for the first time and can be enabled using L6460’s SPI interface. Here after are summarized the main features of the regulator: – – – – – – – Soft start circuitry to limit inrush current flow from primary supply. Changeable feedback reference voltage Internally generated PWM (250 kHz switching frequency). Nonlinear pulse skipping control. Protected against load short circuit. Cycle by cycle current limiting using internal current sensor. Under voltage signal (both continuous and latched) accessible through SPI. 52/139 Doc ID 17713 Rev 1 L6460 Figure 12. Switching regulator controller functional blocks Switching regulator controller V supply Rsense CurrentSense Charge pump Voltage V SWDRW_sns N-CH Fet V SWDRV_gate V SWDRV Voltage Loop Control Driver La Ra C V SWDRV FB SW V out From Central Logic Control Logic Regulator Freq + SelFBRef1:0] [ Analog Mux Vref = 3 V Vref = 3V Vref=0.8V Vref=0.8V Rb V FBRef undervoltage flag Filter + To Central Logic SelFBRef Uv Threshold 1 Analog Mux Uv Threshold 2 Under voltage Threshold 13.1 Pulse skipping operation Pulse skipping strategy has already been explained on main switching regulator section. This regulator has 4 possible PWM duty cycles that can be changed writing in the SelSwCtrPWM bits in the SwCtrCfg register using SPI. Table 12. Switching regulator controller PWM specification Duty cycle value Comments SelSwCtrPWM[1:0] 00 01 10 11 Typical 9% 12% 22.5% 58% Default state SwCtrCfg register Doc ID 17713 Rev 1 53/139 Switching regulator controller L6460 13.2 Output equivalent circuit The switching regulator controller output driving stage can be represented with an equivalent circuit as in the Figure 13: Figure 13. Switching regulator controller output driving: equivalent circuit VPUMP I SOURCE Source command Tsink Sink pulse command RSUSTAIN Sink command I SINK V SWDRV_SW V SWDRV_gate As can be seen from the above figure, the external switch gate is charged with a current generator ISOURCE and it is discharged towards ground with a current generator ISINK that is applied for a TSINK pulse while an equivalent resistor RSUSTAIN is connected between gate and source until the sink command is present. 13.3 Switching regulator controller application considerations This controller can implement a step-down switching regulator used to provide a regulated voltage in the range 0.8 V – 32 V. Such kind of variation could be managed by considering some constraints in the application and particularly by choosing the correct feedback reference voltage as indicated in the Table 13. Table 13. Switching regulator controller application: feedback reference Feedback voltage reference 0.8V - 1V 2.5V - 3V Output regulated voltage range 0.8V ≤ Vout < 5V 5V ≤ Vout ≤ 32V 54/139 Doc ID 17713 Rev 1 L6460 Switching regulator controller An example of application can be considered the following, supposing the external mosfet type STD12NF06L: – – – – Max DC current load = 3 A Typ Over current threshold = 3 A * 1.5 = 4.5 A L = 150 µH C = 220-330 µF In this conditions the step-down regulator will result over-load protected, short-circuit protected over all the regulated voltage range and the VSupply range. Other application configurations could be evaluated before being implemented. Doc ID 17713 Rev 1 55/139 Power bridges L6460 14 Power bridges L6460 includes four H bridge power outputs (each one made by two independent half bridges) that are configurable in several different configurations. Each half bridge is protected against: over-current, over-temperature and short circuit to ground, to supply or across the load. When an over current event occurs, all outputs are turned off (after a filter time), and the over current bit is stored in the internal status register that can be read through SPI. Positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes (see Figure 14). Figure 14. H Bridge block diagram During the start up procedure the bridges are in high impedance and after that they can be enabled through SPI. When a fault condition happens, i.e. an over-temperature event, the bridges return in their start-up condition and they need to be re-enabled from the micro controller. The bridges can use PWM signals internally generated or externally provided (supplied through the GPIO pins). Internally generated PWM signals will run at approximately 31.25kHz with a duty cycle that, through serial interface, can be programmed and incremented in steps of 1/(512*Fosc). To reduce the peak current requested from supply voltage when all bridges are switching, the four internally generated PWM signals are outof-phase. Each half bridge will use the PWM signal selected by the respective MtrXSelPWMSideY[1:0] (X stands for 1, 2, 3 or 4; Y stands for A or B) bits in the SPI, but if two half bridges are configured as a full bridge, only the PWM signal chosen for side A will be used to drive the resulting H bridge. More in detail the PWM selection truth table will be as describe in the following tables: 56/139 Doc ID 17713 Rev 1 L6460 Table 14. PWM selection truth table for bridge 1 or 2 Power bridges MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] 0 0 1 1 0 1 0 1 Selected PWM(1) MotorXPWM (Configurable by means of MtrXCfg register). AuxXPWM (Configurable by means of AuxPwmXCtrl register). ExtPWM1 (from GPIO 9 input) ExtPWM2 (from GPIO 10 input) 1. In this table X stands for 1 or 2, Y stands for A or B. Table 15. PWM selection truth table for bridge 3 or 4 Selected PWM(1) MotorXPWM (Configurable by means of MtrXCfg register). AuxXPWM (Configurable by means of AuxPwmXCtrl register). ExtPWM3 (from GPIO 2 input) ExtPWM4 (from GPIO 11 input) MtrXSelPWMSideY [1] MtrXSelPWMSideY [0] 0 0 1 1 0 1 0 1 1. In this table X stands for 3 or 4, Y stands for A or B. In Figure 15 is reported a block diagram representing the possible PWM choices for each L6460 half bridges. The figure is related only to bridges 1 and 2, but it could be assumed to be valid also for bridges 3 and 4, with few differences due to different possible configurations of these last drivers. Doc ID 17713 Rev 1 57/139 Power bridges Figure 15. Bridge 1 and 2 PWM selection L6460 Mtr1SelPWMSide A[1:0] 00 Motor1 PWM 01 Aux1PWM 10 ExtPWM1 11 ExtPWM2 Mtr1_2Parallel Mtr1SelPWMSideB [1:0] Mtr1Tablel[1:0] 00 Motor1 PWM 01Aux1PWM 10ExtPWM1 11ExtPWM2 Motor 1 side A Logic Table Motor 1 sideB Logic Table Bridge1 Mtr1_2Parallel Mtr2SelPWMSideA[1:0] 00 Motor2 PWM 01Aux2Pwm 10ExtPwm1 11ExtPwm2 Mtr2SelPWMSide B [1:0] 00 Motor2 PWM 01 Aux2Pwm 10 ExtPwm1 11 ExtPwm2 Mtr1_2Parallel Motor 2 side A Logic Table Motor 2 sideB Logic Table Bridge 2 58/139 Doc ID 17713 Rev 1 Side B Power Section Mtr2Tablel[1:0] Side A Power Section Mtr2Tablel[1:0] Side B Power Section Side A Power Section L6460 Power bridges 14.1 Possible configurations The selection of the bridge configuration is done through SPI, by writing the MtrXTable[1:0] bits in the MtrXCfg register. The table below shows the correspondence between MtrXTable[1:0] bits and the bridge configuration. Table 16. Bridge selection MtrXTable[0] 0 1 0 1 Full bridge High or low side switch Half bridge High or low side switch Bridge configuration MtrXTable[1] 0 0 1 1 Bridge 1 & 2 can be paralleled by means of Mtr1_2Parallel bit in the Mtr1_2Cfg register: Bridge 1 and 2 paralleled will form superbridge1, bridge X side A and bridge X side B paralleled form SuperHalfBridgeX or SuperSwitchX. Bridge 3 & 4 can be configured by means of Mtr3_4CfgTable[1:0] bits in the Mtr3_4Cfg register according to following table: Table 17. Bridge 3 and 4 configuration Mtr3_4CfgTable[0] 0 1 0 1 Bridge 3 and 4 configuration Two independent bridges Two bridges in parallel Stepper motor Stepper motor Mtr3_4CfgTable[1] 0 0 1 1 The possible configurations for the bridges are described in the following. Doc ID 17713 Rev 1 59/139 Power bridges L6460 14.1.1 Full bridge When in full bridge configuration, the drivers will behave according to the following truth table: Table 18. TSD 1 0 0 0 0 0 0 0 0 0 0 Full bridge truth table Low power mode X X 1 0 0 0 0 0 0 0 0 Enable X X X 0 1 1 1 1 1 1 1 Current MtrXCtrl MtrXCtrl limit SideA SideB X X X X 1 0 0 0 0 0 0 X X X X X 0 0 0 1 1 1 X X X X X 0 1 1 0 0 1 PWM X X X X X X 0 1 0 1 X OUT+ Z Z Z Z Z 0 1 0 1 1 1 OUTZ Z Z Z Z 0 1 1 1 0 1 nRESET X 0 1 1 1 1 1 1 1 1 1 Note: Note: When “low power mode” is active, the bridges will enter in low power state and will reduce its biasing thus contributing to the power saving. When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the off time. 60/139 Doc ID 17713 Rev 1 L6460 Power bridges 14.1.2 Parallel configuration (super bridge) Bridges 1, 2, 3 and 4 can be configured to be used two by two (1 plus 2, 3 plus 4) as one super bridge thus enabling the driving of loads (motors) requiring high currents. In this configuration the half bridges will be paralleled and will work as one phase of the superbridge just created: the two phases + will become phase + of the newly created superbridge while the two phases - will become phase –. Figure 16. Super bridge configuration Parallel Full Bridge Super Bridge Bridge 1 (3) PH PH Bridge 2 (4) PH PH + - - + M When this configuration is chosen for bridges 1 (3) and 2 (4), the resulting bridge will use the driving logic of bridge 1 (3) so for programming it must be used the bridge 1 (3) control and status bits (direction, PWM, ...): i.e. the used PWM signal will be chosen by Mtr1SideAPwmSel[1:0] (Mtr3SideAPwmSel[1:0]) bits in SPI. If the bridges are not configured to be used in parallel, each side of the bridge will use the PWM selected by the respective MtrXPWMYSel[1:0] bits in the SPI, but if one of the two drivers is configured as a full bridge only one of the two selected PWM will be used to drive the motor and this is the PWM chosen for side A. In order to avoid any problem coming from different propagation times of PWM signals the anti-crossover dead times are slightly increased when the bridges are paralleled. 14.1.3 Half bridge configuration Each bridge can be configured to be used as 2 independent half bridges or as 1 super half bridge (see Figure 17). It is also possible to parallel more than one bridge and use all of them as a single super half bridge. Doc ID 17713 Rev 1 61/139 Power bridges Figure 17. Half bridge configuration V Supply L6460 V pump High side Driver Control Signals From SPI DCX Phase output Control Logic In this case each half bridge will behave according to the following truth table. Table 19. TSD 1 0 0 0 0 0 0 0 0 Half bridge truth table nReset X 0 1 1 1 1 1 1 1 Low power mode X X 1 0 0 0 0 0 0 Enable X X X 0 1 1 1 1 1 Current limit X X X X 0 0 0 0 1 MtrXCtrl SideA/B X X X X 0 0 1 1 X PWM X X X X 0 1 0 1 X OUT Z Z Z Z Z 0 Z 1 Z Note: When “low power mode” bit is active the bridges will reduce its biasing thus contributing to the power saving. When a current limit event occurs this event will be latched and the bridges will remain in high impedance state for the off time. 62/139 Signals Low side Driver Fault Doc ID 17713 Rev 1 L6460 Power bridges 14.1.4 Switch configuration Each bridge can be configured to be used as 2 independent switches that connects the output to supply or to ground. It is also possible to parallel the two switches and use them as a single super switch. All resulting switches will behave according to the following truth table. Table 20. TSD 1 0 0 0 0 0 0 0 Switch truth table nReset X 0 1 1 1 1 1 1 Low power mode X X 1 0 0 0 0 0 Enable X X X 0 1 1 1 1 Current limit X X X X 0 0 0 1 MtrXCtrl SideA/B X X X X 0 1 1 X PWM X X X X X 0 1 X OUT Z Z Z Z Z 1 0 Z Note: When “low power mode” bit is active the bridge will reduce its biasing thus contributing to the whole power saving. When a current limit event occurs this event will be latched and the bridge will remain in high impedance state for the toff time. 14.1.5 Bipolar stepper configuration The bridges 3 and 4 can be configured to be used as a micro-stepping, bidirectional driver for bipolar stepper motors. The primary features of the driver are the following: – – – Internal PWM current control. Micro stepping. Fast, mixed and slow current decay modes. Each H-bridge is controlled with a fixed and selectable off-time PWM current control circuit that limits the load current to a value set by choosing VSTEPREF voltage by means of the internal DAC and an the external RSENSE value. The max current level could be calculated using the formula: IMAX=VSTEPREF/RSENSE To obtain the best current profile, the user can choose three different current decay modes: slow, fast and mixed. Initially, during Ton, a diagonal pair of source and sink power MOS is enabled and current flows through the motor winding and the sense resistor. When the voltage across the sense resistor reaches the programmed DAC output voltage, the control logic will change the status of the bridge according to the selected decay mode (slow, fast or mixed). In slow decay mode the current is recirculated through the path including both high Doc ID 17713 Rev 1 63/139 Power bridges L6460 side power MOS for the whole off time. In fast decay mode the current is recirculated through the high and low side power MOS opposite respect to those forcing current to increase. Mixed decay mode is a selectable mix of the previous two modes (fast decay followed by slow decay) and allows the user to find the best trade off between load current ripple and fast current levels transition. Additionally, by setting the SeqMixedOnlyInDecreasingPh bit in the StpCfg1 register, the user can choose to apply the fast decay percentage in mixed mode always or only when the current is decreasing (i.e from 90° to 180° and from 270° to 360° of the sinusoidal wave). By using SPI interface the user can choose: ● ● ● ● ● ● ● Control type (external firmware control, half step, normal drive, wave drive, micro-step). Up to 16 current levels (quasi-sinusoidal increments) for each bridge. Current direction. Decay mode. Blanking time. Off time (32 values from 2µs to 64µs). Percentage of fast decay respect to toff (when in mixed decay mode). 64/139 Doc ID 17713 Rev 1 L6460 Figure 18. Bipolar stepper configuration Power bridges DC3_PHDC3SENSE V supply DC3_PH+ Stepper Motor VRefA Supply DC4 PHSupply PH- PH+ PH- PH+ DC4 PH+ Sense Sense Bridge Driver - Control Logic - Toff generation - DAC reference selection Bridge Driver Ref1 V STEPREF Ref2 VRefA VRefB DC4SENSE StepperDACPhA SelStepRef StepperDACPhB VRefB Using the StepCtrlMode[2:0] bits in StepCfg1 register, L6460 can be programmed to internally generate the stepping levels. In these cases and depending on the StepFromGpio bit in the StpCfg1 register the Stepper driver will move to next step each time the StepCmd bit is set at logic level “1” or at each pulse transition longer than ~1µs externally applied on GPIO12 (StepReq signal), according to Table 21. Doc ID 17713 Rev 1 65/139 Power bridges Table 21. Sequencer driver StepFromGpio 0 1 Sequencer driver StepCmd bit in StepCmd register. GPIO12 input pin. L6460 The allowable control modes are as follows: 1. 2. Stepping sequence left to external microcontroller: in this mode the current level in each motor winding is set by the microcontroller via the serial interface. Full step: in this mode the electrical angle will change by 90° steps at each StepReq signal transition. There are two possibilities: – Normal step (two phases on): in normal step mode both windings are energized simultaneously and the current will be alternately reversed. The resulting electrical angles will be 45°, 135°, 225° and 315°. Wave drive (one phase on): In wave drive mode each winding is alternately energized and reversed. The resulting electrical angles will be 90°, 180° and 270° and 360°. – 3. Half step: in this mode, one motor winding is energized and then two windings alternately so the electrical angles the motor will do when rotating in clockwise direction and using the same current limit in both the phases are: 45°, 90°, 135°, 180°, 225°, 270°, 315° and 360°. Microstepping: in this mode the current in each motor winding has a quasi sinusoidal profile. The increment between each step is obtained at each transition of StepCmd bit in StepCmd register. The difference between each step could be chosen (4, 8 or 16 levels for each phase) according to following table: Stepper driving mode Control mode No Control Half Step Normal Step Wave Drive 1/4 Step 1/8 Step 1/16 Step Description Stepping sequence control left to the external controller Half step Full step (two phases on) Full step (one phase on) Four micro steps Eight micro steps Sixteen micro steps 4. Table 22. StepCtrlMode[2:0] 000 or 111 001 010 011 100 101 110 Note: When in 1/16 step mode, the best phase approximation of sinusoidal wave, is obtained by repeating the “F” step as follows: 0, 1, 2, 3, … , D, E, F, F, F, E, D, … , 3, 2, 1, 0 When internal stepping sequence generation is used, the stepping direction is set by the StepDir bit according to the Table 23. 66/139 Doc ID 17713 Rev 1 L6460 Table 23. Stepper sequencer direction StepDir 0 1 Direction Counter clockwise (CCW) Clockwise (CW) Power bridges Note: It is intended as clockwise the sequence that forces a clockwise rotation of the versors representing the current module and phase. Doc ID 17713 Rev 1 67/139 Power bridges L6460 An internal DAC is used to digitally control the output regulated current. The available values are chosen to provide a quasi sinusoidal profile of the current. The current limit in each phase is decided by PhADAC[3:0] bits for phase A and PhBDAC[3:0] bits for phase B. The table below describes the relation between the value programmed in the stepper DAC and the current level. Table 24. DAC Phase current ratio respect to IMAX PhXDAC [3:0] Min 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Typ (Hi-Z) 9.8 19.5 29.0 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX % of IMAX Max Unit Note: The min and max values are guaranteed by testing the percentage of VSTEPREF that allows the commutation of the Rsense comparator. IMAX=VSTEPREF/ RSENSE. To obtain the best phase approximation of a sinusoidal wave, the user needs to repeat the final (100%) value. So the full values sequence should be as follows: 0, 1, 2, 3 … D, E, F, F, F, E, D … 3, 2, 1, 0. Even if the total spread shows overlapping between current steps, the monotonicity is guaranteed by design. When the internal sequencer the minimum angle resolution is nominally 5.625°, so depending on the control mode chosen, the selectable steps are Table 25. 68/139 Doc ID 17713 Rev 1 L6460 Table 25. Internal sequencer Control mode Power bridges Typical output current (% of IMAX) Resulting electrical angle Electrical degrees 45° 50.6° 56.2° 61.9° 67.5° 73.1° 78.8° 84.4° 90° 95.6° 101.2° 106.9° 112.5° 118.1° 123.8° 129.4° 135° 140.6° 146.2° 151.9° 157.5° 163.1° 168.8° 174.4° 180° 185.6° 191.2° 196.9° 202.5° 208.1° 213.8° Half step 1 Full step (2 phases on) 1 Full step (1 phase on) 1/4 step 1 1/8 step 1 1/16 step 1 2 Phase A (sin) 70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 100 98.1 95.7 92.4 88.2 83.1 77.3 70.7 63.4 55.6 47.1 38.3 29.0 19.5 9.8 HiZ -9.8 -19.5 -29.0 -38.3 -47.1 -55.6 Phase B (cos) 70.7 63.4 55.6 47.1 38.3 29.0 19.5 9.8 HiZ -9.8 -19.5 -29.0 -38.3 -47.1 -55.6 -63.4 -70.7 -77.3 -83.1 -88.2 -92.4 -95.7 -98.1 -100 -100 -100 -98.1 -95.7 -92.4 -88.2 -83.1 2 3 4 2 3 5 6 4 7 8 2 1 3 5 9 10 6 11 12 4 7 13 14 8 15 16 3 2 5 9 17 18 10 19 20 6 11 21 22 12 23 24 4 2 7 13 25 26 14 27 28 8 15 29 30 16 31 Doc ID 17713 Rev 1 69/139 Power bridges Table 25. Internal sequencer (continued) Control mode Typical output current (% of IMAX) L6460 Resulting electrical angle Electrical degrees 219.4° 225° 230.6° 236.2° 241.9° 247.5° 253.1° 258.8° 264.4° 270° 275.6° 281.2° 286.9° 292.5° 298.1° 303.8° 309.4° 315° 320.6° 326.2° 331.9° 337.5° 343.1° 348.8° 354.4° 360°/0° 5.6° 11.2° 16.9° 22.5° 28.1° Half step Full step (2 phases on) 3 Full step (1 phase on) 1/4 step 1/8 step 1/16 step 32 Phase A (sin) -63.4 -70.7 -77.3 -83.1 -88.2 -92.4 -95.7 -98.1 -100 -100 -100 -98.1 -95.7 -92.4 -88.2 -83.1 -77.3 -70.7 -63.4 -55.6 -47.1 -38.3 -29.0 -19.5 -9.8 HiZ 9.8 19.5 29.0 38.3 47.1 Phase B (cos) -77.3 -70.7 -63.4 -55.6 -47.1 -38.3 -29.0 -19.5 -9.8 HiZ 9.8 19.5 29.0 38.3 47.1 55.6 63.4 70.7 77.3 83.1 88.2 92.4 95.7 98.1 100 100 100 98.1 95.7 92.4 88.2 5 9 17 33 34 18 35 36 10 19 37 38 20 39 40 6 3 11 21 41 42 22 43 44 12 23 45 46 24 47 48 7 4 13 25 49 50 26 51 52 14 27 53 54 28 55 56 8 4 15 29 57 58 30 59 60 16 31 61 62 70/139 Doc ID 17713 Rev 1 L6460 Table 25. Internal sequencer (continued) Control mode Power bridges Typical output current (% of IMAX) Resulting electrical angle Electrical degrees 33.8° 39.4° Half step Full step (2 phases on) Full step (1 phase on) 1/4 step 1/8 step 32 1/16 step 63 64 Phase A (sin) 55.6 63.4 Phase B (cos) 83.1 77.3 The voltage spikes on Rsense could be filtered by selecting an appropriate blanking time on the output of current sense comparator. The Blanking time selection is made by using the StepBlkTime[1:0] bits in the StpCfg1 register. The stepper driver off time could be programmed by means of the StepOffTime[4:0] bits in StpCfg1 register. Table 26. Stepper off time Off time StepOffTime[4:0] Typ 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs µs Unit Doc ID 17713 Rev 1 71/139 Power bridges Table 26. Stepper off time (continued) Off time StepOffTime[4:0] Typ 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 42 44 46 48 50 52 54 56 58 60 62 64 µs µs µs µs µs µs µs µs µs µs µs µs Unit L6460 By means of MixDecPhA[4:0] and MixDecPhB[4:0] in StepCfg2 register, the percentage of off time during which each phase will stay in fast decay mode could be programmed according to Table 28. 72/139 Doc ID 17713 Rev 1 L6460 Table 27. Stepper fast decay MixDecPhX[4:0] Fast decay percentage during off time Typ 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 1xxxx 0 6.25 12.5 18.75 25 31.25 37.6 43.75 50 56.25 62.5 68.75 75 81.25 87.5 93.75 100 Power bridges Unit % % % % % % % % % % % % % % % % % 14.1.6 Synchronous buck regulator configuration (Bridge 3) Bridge 3 can be configured to be used as 2 independent synchronous buck regulators or as a single high current synchronous buck regulator using GPIOs pins in order to close the voltage loop. The resulting regulator(s) will implement a non linear, pulse skipping, control loop using an internally generated PWM signal. The voltage will be set externally with a divider network and PWM duty cycle that can be programmed in order to ensure a proper regulation. The regulator will be enabled/disabled using serial interface and will implement a soft start strategy similar to that used by primary switching regulator. Doc ID 17713 Rev 1 73/139 Power bridges Here after are summarized the primary features of the regulator(s): – – – – – – – – Synchronous rectification L6460 Automatic low side disabling when current in the inductance reaches 0 to optimize efficiency at low load Pulse skipping control Internally generated PWM Cycle by cycle current limiting using internal current sensor Protected against load short circuit Soft start circuitry Under voltage signal (both continuous and latched) accessible through serial interface. Figure 19. Regulator block diagram V supply CurrentSense Charge pump Voltage High Side Driver Half Bridge OUT La Ra V out Low Side Driver From Central Logic C Bridge Sense Voltage Loop Control Control Logic Vref=3V N.C. N.C. Vref= 0.8V Regulator Freq + GPIO USED as FB Rb Regulator Ref SelFBRef Obtained using spare analo g/dig ital blocks To Central Logic Filter + Under voltage Threshold Depending on the load current, there could be the necessity to add a Schottky diode on output to reduce internal thermal dissipation. This diode must be placed near to the pin and must be fast recovery and low series resistance type. For detail about pulse skipping please refer to main switching regulator Section 13.3 on page 54. The output voltage will be externally set by a divider network connected on feedback pin. To reduce as much as possible the regulation voltage error L6460 has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four under- 74/139 Doc ID 17713 Rev 1 L6460 Power bridges voltage thresholds) using serial interface. The feedback reference voltage is selected by writing the SelFBRef[1:0] bits in the Aux1SwCfg or Aux2SwCfg registers. The switching regulators have four possible PWM duty cycles that can be changed using SPI according to Table 28. Table 28. PWM specification Typical duty cycle value 10% 13% 24% 61% Default state for AUX1 Default state for AUX2 Comments AuxXPWMTable[1:0] 00 01 10 11 14.1.7 Regulation loop As seen before L6460 contains 2 regulation loops for switching regulators that are used when bridge 3 is used as a regulator. These loops are assembled using internal comparators and filters similar to that used in main switching regulator. When bridge 3 is not used for this purpose or when only one regulation loop is needed, the control loop is available on a GPIO output thus enabling the customer to assembly a basic buck switching regulator using an external Power FET. The comparators used in the above mentioned regulation loops are general purpose low voltage (3.3 V) comparators; when the relative regulation loop is not used they can be accessed as shown in the Figure 20. Figure 20. Internal comparator functional block diagram GPIOx GPIOy GPIOx DECODE LOGIC GPIOy DECODE LOGIC GPIOyMode GPIOxMode + GPIOz Value From SPI GPIOzMod e GPIOz DECODE LOGIC Doc ID 17713 Rev 1 - V 3v3 GPIOz GPIOz Logic Driver 75/139 Power bridges L6460 14.1.8 Battery charger or switching regulator (Bridge 4) The functionality of this circuit is obtained by using the bridge 4 output stage. This circuit is powered directly from VSupply and it is intended to be used as a battery charger or a switching regulator. The control loop block diagram is shown in the Figure 21. Figure 21. Battery charger control loop block diagram L6460 IREF_FB COMP_I VREF_FB COMP_V DIFF AMPLI PULSE SKIPPING BURST CONTROL LOGIC PEAK CURRENT MODE CONTROL LOGIC PWM BRIDGE 4 PARALLELED POWER STAGE DC4_plus DC4_minus TO LOAD Ilimit FBRef SelFBRef CurrRef SelCurrRef The battery charger control loop implements an asynchronous switching regulator intended to be used as a constant voltage/constant current programmable source. When used as a simple switching regulator, it could be a system regulator depending on startup configurations When a system regulator under-voltage event is detected L6460 will enter in reset state signaling this event to the microcontroller by pulling low the nRESET pin and disabling most of its internal blocks. When the control loop is intended to be used as a battery charger, the Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register. This is because in this case the undervoltage event that will be sure present when charging a battery (see battery charger profile in Figure 22) will not be considered during start up sequence. The regulated output voltage will be externally set by a resistor divider network connected to VREF_FB pin. L6460 has the possibility to choose between four voltage references (and, as a consequence, four under-voltage thresholds) using the serial interface. The feedback reference voltage selection is made by writing the SelFBRef[1:0] bits in the Aux3SwCfg1 register. The regulation of the output current can be done externally, by using a sense resistor connected in series on the path that provides current to the load. By using an external differential amplifier the customer can set the desired V = f(I) characteristic, and therefore 76/139 Doc ID 17713 Rev 1 L6460 Power bridges the regulated current: the voltage provided at the IREF_FB pin will be compared to the internal reference. L6460 has the possibility to choose between four voltage references using the serial interface, writing the SelCurrRef[1:0] bits in the Aux3SwCfg1 register. Regardless of the CurrRef voltage, if the IREF_FB pin remains below the chosen threshold, the internal current limitation will work (typical Ilimit current 4A). The battery charge profile can be chosen by fixing the desired CurrRef and FBRef internal reference voltages and by choosing the desired V = f(I) trans-characteristic of the external differential amplifier. In the Figure 22 is shown a typical Li-Ion battery charge profile. Figure 22. Li-ion battery charge profile Voltage or Current Veochrg Blue=Battery Voltage Vchrg Ichrg CurrRef depending Red=Battery Current FBRef depending Iprechrg Ieochrg Time Precharge phase Rapid charge phase Constant V. phase End Of Charge The battery charge loop control can be used to implement a buck type switching regulator. The regulated output voltage will be externally set by a resistor divider network connected to VREF_FB pin, as already described and the current protection will be the one implemented internally in the Bridge4 section. Doc ID 17713 Rev 1 77/139 Power bridges Figure 23. Simple buck regulator L6460 L6460 IREF_FB COMP_I VREF_FB COMP_V PULSE SKIPPING BURST CONTROL LOGIC PEAK CURRENT MODE CONTROL LOGIC PWM BRIDGE 4 PARALLELED POWER STAGE DC4_plus DC4_minus TO LOAD Ilimit FBRef SelFBRef CurrRef SelCurrRef When this control loop is intended to be used as a simple buck regulator, the proper Aux3BatteryCharge bit must be written in the Aux3SwCfg1 register. The regulator will also implement a soft start strategy. When L6460 “low power mode” is enabled this regulator will be disabled. Here after are summarized the primary features of the regulator: – – – – – – – – Internal power switch. Nonlinear pulse skipping control. Internally generated PWM (250 KHz switching frequency). Cycle by cycle current limiting using internal current sensor/ external current sense differential amplifier. Protected against load short circuit. Soft start circuitry to limit inrush current flow from primary supply. Under voltage signal (both continuous and latched) accessible through SPI. Over temperature protection. In pulse skipping control PWM the duty cycle must be decided by the user depending on supply voltage and regulated voltage. Therefore the switching regulator has 4 possible PWM duty cycles that can be changed writing in the Aux3PWMTable[1:0] bits in the Aux3SwCfg1 register according to the Table 31. 78/139 Doc ID 17713 Rev 1 L6460 Table 29. Battery charger regulator controller PWM specification Typical duty cycle value 10% 13% 24% 61% Power bridges Aux3PWMTable [1:0] 00 01 10 11 Comments Default state Doc ID 17713 Rev 1 79/139 AD converter L6460 15 AD converter L6460 integrates and makes accessible via SPI a general purpose multi-input channel 3.3V analog to digital converter (ADC). The ADC can be configured to be used as: ● ● 8-bit resolution ADC. 9-bit resolution ADC. The result of the conversion will always be a 9-bit word; the difference between the two configurations is that, to speed up the conversion, the resolution is reduced when the ADC is used in the 8-bit resolution mode. The ADC is seen at software level as a 2 channel ADC with different programmable sample times; a finite state machine will sample the requests done through the SPI interface on both the channel and will execute them in sequence. When used as 8-bit resolution the ADC can achieve a higher throughput and, if the minimum sample time is used, one conversion is completed in t = 5.5 µs. When used as 9-bit resolution ADC the circuit is slower and the minimum sample times are disabled. In that case the conversion will be completed in a time t= 10 µs. The use of ADC type must be decided at the start-up by writing in the one time programmable ADC configuration register; no A/D conversion will be enabled if this register is not set from last power-up sequence. This ADC can be used to measure some external pins as well as some L6460’s internal voltages. The converter is based on a cyclic architecture with an internal sample-and-hold circuit. Sample time can be changed using serial interface to enable good measure of higher impedance sources. 80/139 Doc ID 17713 Rev 1 L6460 Figure 24. A2D block diagram Sam Time 0 ple Analog Mux AD converter V supply V pump V3v3 VLINmain FB VSWmain FB VSWDRV_F B GPIO[0:14] RefOpAmpX OutStripStepperPHX Current DAC Temp Sensors S&H Sam Time 1 ple A2D A2DE able n Conversion Done 0 Conversion Done 1 Conversion Result Conversion Address 1 To SPI The A2D system is enabled by setting the A2DEnable bit to ‘1’ in the A2DControl register. The A2DType bit in the A2DConfigX registers selects the A2D active configuration (8-bit resolution or 9-bit) according to the Table 30. Table 30. ADC truth table A2DType X 0 1 A2D operation Disabled ADC working as a 8-bit ADC ADC working as a 9-bit ADC A2DEnable 0 1 1 The multiplexer channel to be converted can be chosen by writing the A2DChannel1[4:0] or A2DChannel2[4:0] bits in the A2DConfigX register; the channel addresses table is reported in the Table 31. Doc ID 17713 Rev 1 A2DType 0 A2DType 1 Conversion Address 0 Selected A2DType 81/139 AD converter Table 31. Channel addresses Converted channel VSupply scaled VSupplyInt scaled Vref_2_5V Temp Sensor1 Temp Sensor2 V3v3 scaled Not used Not used GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] clamp GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] MuxRefOpAmp1 MuxRefOpAmp2 OutStripStepperPhA OutStripStepperPhB Not used ST reserved ST reserved ST reserved See current DAC circuit Temperature sensor1 Temperature sensor2 Note L6460 A2DChannelX[4:0] (bin.) 00000 00001 00010 00011 00100 00101 0011X 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 See voltage divider specification. See voltage divider specification. See voltage divider specification. References AUX1 switching reg. 0.8V reference voltage 1.65V reference voltage The sample time can be changed by modifying the A2DSampleX[2:0] bits in the A2DConfigX register; depending on which is the A2DType bit, the available sample times are reported in Table 32 and Table 33. 82/139 Doc ID 17713 Rev 1 L6460 Table 32. ADC sample times when working as a 8-bit ADC Sample time A2DSampleX[2:0] (binary) Typ 000 001 010 011 100 101 110 111 16*Tosc 32*Tosc 64*Tosc 128*Tosc 256*Tosc 512*Tosc 1024*Tosc 2048*Tosc AD converter Unit µs µs µs µs µs µs µs µs Table 33. ADC sample time when working as a 9-bit ADC Sample time A2DSampleX[2:0] (binary) Typ 000 001 010 011 100 101 110 111 32*Tosc 64*Tosc 128*Tosc 256*Tosc 512*Tosc 1024*Tosc 2048*Tosc 4096*Tosc Unit µs µs µs µs µs µs µs µs A conversion on channel 1 can be triggered by writing a logic ‘1’ in the A2DTrig1 bit in the A2DConfigX register and a conversion on channel 2 can be triggered writing a logic ‘1’ in the A2DTrig2 bit in the same register. While a request on a channel is pending but not yet completed L6460 will force to logic ‘0’ the corresponding A2DdoneX bit in the A2DResultX registers and L6460 will not accept other conversion request on that channel. Continuous conversion on one channel can be accomplished by setting to logic ‘1’ the A2DcontinuousX bit in the A2DConfigX register. When A2DcontinuousX bit is set, other conversions can be accomplished on the other channel; these conversions will be inserted between two conversions of the other channel and the end of the conversion will be signaled using A2DdoneX bit. Of course when a channel is in continuous mode its sample time and channel address cannot be changed. Continuous conversions on both 2 channels can be also accomplished by setting to logic ‘1’ the A2Dcontinuous1 and A2Dcontinuous2 bits; the conversions are made in sequence. Doc ID 17713 Rev 1 83/139 AD converter L6460 15.1 Voltage divider specifications As can be seen in the A2D block diagram, in order to report some voltages in the A2D working range, they are scaled with a resistor divider before the conversion. Here below are reported the resistor voltage divider specifications: Table 34. Parameter RSupply_ratio Voltage divider specification Description VSupply divider ratio Notes Min Typ 1/15 1/15 1/2 Max Unit RSupplyInt_ratio VSupply Int divider ratio RV3V3_ratio V3v3 divider ratio 84/139 Doc ID 17713 Rev 1 L6460 Current DAC circuit 16 Current DAC circuit L6460 includes a multiple range 6-bit current sink DAC. The LSB value of this DAC can be selected using the DacRange[1:0] bits in the CurrDacCtrl register. The output of this circuit is connected to GPIO[8] that is a 5 V tolerant pin. The value of this pin can be converted using ADC. The pin value can be scaled before being converted by enabling the internal resistor divider connected to this pin. If the current sunk by resistor divider is not acceptable the pin voltage can be converted without scaling its value. When the conversion without scaling resistor is chosen a clamping connection is used to avoid voltage compatibility of the pin to the ADC system. The clamping circuit will sink a typical current of half microampere from the pin during the sampling time. Figure 25. Current DAC block diagram Va3 Reference Current Generator DacRange [1:0] EnDac DacValue[5:0] DacRange[1:0] Current Sink DAC RCurrDac Gpio[8] Gpio8 Clamp (to ADC) Clamp circuit EnDac A2DChannel1: [40] Combinatorial Mask Address Recognized Address Recognized EnDacScale Gpio[8] Digital Driver A2DChannel2: [40] Combinatorial Mask The circuit is enabled by setting to logic ‘1’ the EnDac bit in the CurrDacCtrl register then the desired sunk current value is chosen by changing the value of the DacValue[5:0] bits in the same register being DacValue[0] the least significant bit and DacValue[5] the most significant bit. Doc ID 17713 Rev 1 85/139 Current DAC circuit L6460 The current DAC has three possible current ranges that can be selected using the DacRange[1:0] bits in the CurrDacCtrl register. The DAC range selection table is shown in Table 35. Table 35. Current DAC truth table DacRange[0] 0 1 0 1 LSB typical current ILSB typ Disabled 10 µA 100 µA 1 mA Full scale typical current IFULL typ Disabled 0.63 mA 6.3 mA 63 mA DacRange[1] 0 0 1 1 By changing LSB current value, all steps will change following this relation: Istep(N) = N * ILSB where N is the value of DacValue[5:0] bits. 86/139 Doc ID 17713 Rev 1 L6460 Operational amplifiers 17 Operational amplifiers L6460 contains two rail to rail output, high bandwidth internally compensated operational amplifiers supplied by VGPIO_SPI pin. The operative supply range is 3.3 V ± 4.5% Each operational amplifier can have all pin accessible or, to save pins, can be internally configured as a buffer. They can also be used as comparators; to do that the user must disable internal compensation by writing a logic level “1” in the OpXCompMode bit in the OpAmpXCtrl register. in Figure 26 are reported the block diagrams of the two operational amplifiers. Figure 26. Configurable 3.3 V operational amplifiers GPIO[11] Op1Ref[1:0] Op1EnIntRef Op1Plus Ref V GPIO_SPI Op1CompMode To A/D System Op1EnPlusPin GPIO[9] GPIO[10] Op1BufConf Op1EnMinusPin + OpAmp 1 EnOp1 EnOp2 + + Op2CompMode Op2BufConf Op2EnMinusPin GPIO[13] GPIO[12] Op2EnPlusPin V GPIO_SPI Op2Plus Ref Op2EnIntRef Op2Ref[1:0] GPIO[14] Note: Op1EnPlusRef and Op2EnPlusRef cannot be used to drive external pin so the user must be sure not to enable the path between one of these voltage references and the external pin. Doc ID 17713 Rev 1 87/139 Operational amplifiers L6460 The operational amplifiers are capable to drive a capacitive load in buffer configuration up to a maximum of 100 pF; for higher capacitance it is necessary to add resistive loads to increase the OP output current, and/or to add a low resistor (10 Ω) in series to the load capacitance. To use the operational amplifiers as comparators the user must disable internal compensation writing a logic one in the OpXDisComp bit in the OpAmpXCtrl register. 88/139 Doc ID 17713 Rev 1 L6460 Low voltage power switches 18 Low voltage power switches Low voltage power switches are analog switches designed to operate from a single +2.4 V to +3.6 V VGPIO_SPI supply. They are intended to provide and remove power supply to low voltage devices. When switched on, they connect the VGPIO_SPI pin to their output pin (GPIO[6] for low voltage power switch 1 or GPIO[7] for low voltage power switch 2) thus powering the device connected to it. The turning on and off of each switch can be controlled through serial interface. L6460 provides 2 low voltage power switches, each of them has current limitation to minimum 150mA to limit inrush current when charging a capacitive load. When the limit current has been reached, for more than a Tfilter time, then a flag is activated; this flag is latched in the central logic and can be cleared by the firmware. Please note that, in case of capacitive load, the current limit is reached the first time the low power switch is turned on: therefore the user will find a limit flag that must be cleared. The 2 low voltage power switches can be externally paralleled to obtain a single super low voltage power switch. Low voltage pass switches sink current needed for their functionality from pin VGPIO_SPI, they never inject current on this pin. Figure 27. Low power switch block diagram V GPIO_SPI EnLowVSw[x] Driving Circuit GPIO[6] (LPS 1) or GPIO[7] (LPS 2) Current Limit Sensor LowVSwIlim[x] To SPI S LowVSwIlimLth[x] R GPIO[6]/GPIO[7] Driver ClrLowVrSwLth Reset State Doc ID 17713 Rev 1 89/139 General purpose PWM L6460 19 General purpose PWM L6460 includes three general purpose PWM generators that can be redirected on GPIO pins (see Chapter 22). Two of these generators (Aux_PWM_1 and Aux_PWM_2) work with a fixed period FOSC/512 and have a programmable duty cycle; the other one (GP_PWM) has a programmable base time clock and a programmable time for both high and low levels. 19.1 General purpose PWM generators 1 and 2 (AuxPwm1 and AuxPwm2) The Duty cycle of these PWM generators can be changed by writing the AuxPwmXCtrl bits (where X can be 1 or 2) in the AuxPwm1Ctrl and AuxPwm2Ctrl registers. Their positive duty cycle will change according to the equation: PWM_X_DUTY = AuxPwmXCtrl [ 9:0 ] /512 According to this equation a programmed “0” value will cause a 0% duty cycle (output always at logic level 0). 19.2 Programmable PWM generator (GpPwm) GpPWM has a programmable base clock that can be changed by programming the GpPwmBase[6:0] bits in the GpPwmBase register. The clock will change according to the equation: PWM_BASE_PERIOD = ( GpPwmBase [ 6:0 ] + 1 ) × Tosc The high and low level duration (expressed in base clock periods), can be programmed writing the GpPwmHigh[7:0] and GpPwmLow[7:0] bits in the GpPwmCtrl register so they will change according to following equations: High_level_Time = GpPwmHigh [ 7:0 ] × PWM_BASE_PERIOD Low_level_Time = GpPwmLow [ 7:0 ] × PWM_BASE_PERIOD The resulting period of the PWM will be: Period = ( GpPwmHigh [ 7:0 ] + GpPwmLow [ 7:0 ] ) + PWM_BASE_PERIOD and the positive duty cycle will result: High_level_Time GpPwmHigh [ 7:0 ] DutyCycle = ---------------------------------------------------------------------------------------------- = -------------------------------------------------------------------------------------------------------High_level_Time + Low_level_Time GpPwmHigh [ 7:0 ] + GpPwmLow [ 7:0 ] A programmed value of 0 in GpPwmHigh[7:0] and GpPwmLow[7:0] bits will force the PWM generator output to be always at logic level “0”. 90/139 Doc ID 17713 Rev 1 L6460 Interrupt controller 20 Interrupt controller L6460 contains one programmable interrupt controller that can be used to advice the firmware, through the serial interface, when a certain event happens inside the IC. The output of the interrupt circuit can be also redirected on a GPIO pin therefore the event can be signaled directly to the external circuits. Figure 28. Interrupt controller diagram IntCtrlAutoDisable EnIntCtrlPulse DisableMonitor Disable Pulse DisableSignals Generation log ic Decode logic Monitored signals Pulse Gen erator To Gpio Enable signals EnIntCtrl The Table 36 contains the events that can be monitored by the interrupt controller. Table 36. Interrupt controller event Event description Bridge 1 fault (Ilimit event) Bridge 2 fault (Ilimit event) Bridge 3 fault (Ilimit event) Bridge 4 fault (Ilimit event) nAWAKE pin low Switching regulator controller Ilimit event. Main switching regulator Ilimit event. Low voltage power switch 1 Ilimit event. Low voltage power switch 2 Ilimit event Warming event Notes Event Mtr1Fault Mtr2Fault Mtr3Fault Mtr4Fault nAWAKE SwRegCtrl Ilimit VMainSW Ilimit LowPowSw 1 LowPowSw 2 Warm Doc ID 17713 Rev 1 IntCtrlPolarity EnIntCtrlPulse 91/139 Interrupt controller Table 36. Interrupt controller event (continued) Event description Watch dog warning event Watch dog event Digital comparator ADC conversion done 1 ADC conversion done 2 AUX1 Ilimit event. (1) (1) L6460 Event WDWarn WD DigCmp ADCDone1 ADCDone2 Vloop1Ilim Notes 1. This event is disabled if the related ADC channel is configured in continuous mode. Any event detection can be enabled and disabled by setting at logic level 1 the relative enable bit in the interrupt controller configuration register (IntCrtlCfg). The interrupt controller can be programmed to give a pulse when a monitored event happens or to continuously maintaining the output active until the interrupt condition is finished. When programmed to signal the enabled events by giving pulses, the interrupt controller can be configured to disable the event that caused the interrupt request until the firmware reenables it writing the relative bit in the control register (IntCrtlCtrl) or to continue to monitor the event. The GPIO output of this circuit can be programmed to be active high or active low. 92/139 Doc ID 17713 Rev 1 L6460 Digital comparator 21 Digital comparator L6460 includes one digital comparator that can be used to signal, through serial interface, that a channel converted by the ADC is greater, greater-equal, lesser, lesser equal, or equal than a fixed value set by serial interface or than the value converted by the other ADC channel. This circuit can be used to monitor the temperature of the IC advising the firmware when it reaches a certain value decided by the firmware by setting one ADC channel to do continuous conversions of the temperature sensor. The circuit operation can be enabled or disabled changing the EnDigCmp bit in the configuration register DigCmpCfg. By setting the DigCmpUpdate[1:0] bits in the configuration register, the comparator can be programmed to update its output in one of the following ways: ● ● ● ● DigCmpUpdate[1:0]=00 – – – – Continuously (each clock). Each time a conversion is performed on ADC channel 0. Each time a conversion is performed on ADC channel 1. ADC state machine driven. DigCmpUpdate[1:0]=01 DigCmpUpdate[1:0]=10 DigCmpUpdate[1:0]=11 When the last option is selected, the digital comparator will update its output in two different ways depending on the configuration of the ADC converter. If ADC converter is configured to do continuous conversions on both channels, the output of the comparator will be updated when the double conversion is completed. If ADC converter is not configured to do continuous conversions on both channels, the output of the comparator will be updated each time a conversion is completed. The comparator output can be digitally filtered so that the programmed condition has to be found for three consecutive checks before to be signaled. The Figure 29 shows the block diagram of digital comparator. Doc ID 17713 Rev 1 93/139 Digital comparator Figure 29. Digital comparator block diagram L6460 A2DDone0 DigCmpValue[9:0] A2DDone1 DigCmpSelCh0[1] Logic ‘1’ ADC FSM Update Signal A2DResult0[8:0] DigCmpUpdate[1:0] A2DResult1[8:0] Three check s filter DigCmpSelCh0[0] Data0[9:0] DigCmpSelCh1[0] CmpOut COMPARATOR Data1 [9:0] DigCmpSelCh1[1] In Table 37 is reported the comparison type truth table. Table 37. Comparison type truth table SelCmpType[1] X 0 0 1 1 SelCmpType[0] X 0 1 0 1 Comparison type Disabled Data0[9:0] ≤1³1÷Data1[9:0] Data0[9:0] = Data1[9:0] Data0[9:0] > Data1[9:0] Data0[9:0] ≤= Data1[9:0] EnDigCmp 0 1 1 1 1 In Table 38 is reported the Data0/Data1 selection truth table. Table 38. DataX selection truth table DigCmpSelChX[0] X 0 1 DataX[9:0] DigCmpValue[9:0] A2DResult1[8:0] A2DResult1[8:0] DigCmpSelChX[1] 0 1 1 94/139 Doc ID 17713 Rev 1 SelCmpType[ 1:0] EnDigCmp L6460 GPIO pins 22 GPIO pins Some of the pins of L6460 are indicated as GPIO (General purpose I/O). These pins can be configured to be used in different ways depending on customer application. All GPIOs can be used as digital input/output pins with digital value settable/readable using serial interface or as analog input pins that can be converted using the A2D system. Some of the pins can be used for special purposes: i.e. two of them can be used to access to the pass switch function, other two are used as feedback pins for the auxiliary synchronous switching regulators. All input Schmitt triggers and output circuitry used for start-up purposes are powered by the internally generated V3v3, while the digital output buffers are powered by VGPIO_SPI pin. To ensure independency between V3v3 and VGPIO_SPI the GPIOs output drivers are open-drain driver or the high side MOS is in back-to-back configuration to avoid the presence of the body diode between output and supply. All digital output signals can be inverted before being provided on the relative GPIO pins. Here below is reported the table with GPIO functions. Table 39. Pin Name GPIO functions description Function(1) Input Analog Digital Analog Output Special Digital - SPI OUT - Interrupt ctrl. - AuxPwm1 - AuxPwm2 - SPI OUT - Interrupt ctrl. - AuxPwm1 - AuxPwm2 - SPI OUT - Interrupt ctrl. - AuxPwm2 - AuxPwm3 - SPI OUT - AuxPwm2 - AuxGpPwm3 - SPI OUT - Interrupt ctrl. - AuxPwm1 - AuxPwm3 - SPI OUT - Reg. loop 1 - Comp1 out - AuxPwm3 Start-up Open drain configuration output pin Notes GPIO[0] - ADC input - SPI IN GPIO[1] - ADC input - Comp1 In- Vaux1 F.B. - ADC input - Comp2 In- Vaux2 F.B. - SPI IN Open drain output GPIO[2] - SPI IN - IN PWM Open drain output GPIO[3] - ADC input - SPI IN Start-up Open drain configuration output pin Start-up configuration Open drain output pin GPIO[4] - ADC input - SPI IN GPIO[5] - ADC input - SPI IN Full driver BB Slave Control powered by V3v3 Doc ID 17713 Rev 1 95/139 GPIO pins Table 39. Pin Name Analog L6460 GPIO functions description (continued) Function(1) Input Digital Analog Output Special Digital - SPI OUT - A2DGpo - AuxPwm2 - Comp2 out - SPI OUT - AuxPwm1 - AuxPwm3 - Comp1 out - SPI OUT - AuxPwm1 - AuxPwm3 - Comp2 out - SPI OUT - Interrupt contr. - AuxPwm1 - Reg. loop 3 - SPI OUT - Interrupt ctrl. - AuxPwm2 - AuxPwm3 - SPI OUT - A2DGpo - AuxPwm1 - AuxPwm2 - SPI OUT - Interrupt ctrl - Comp2 out - Reg. loop 2 - SPI OUT - AuxPwm1 - Reg. loop 3 - AuxPwm3 - SPI OUT - Interrupt ctrl. - AuxPwm2 - AuxPwm3 Full driver connected to VGPIO_SPI Notes GPIO[6] - ADC input - SPI IN - Low Pow Sw 1 GPIO[7] - ADC input - SPI IN - Low Pow Sw 2 Full driver connected to VGPIO_SPI GPIO[8] - ADC input - SPI IN(2) - CurrDAC 5 volt input tolerant Open drain output GPIO[9] - SPI IN - ADC input - ID 1 - OpAmp1 in+ - IN PWM Full driver connected to VGPIO_SPI - SPI IN - ADC input GPIO[10] - ID 2 - OpAmp1 in- IN PWM Full driver connected to VGPIO_SPI GPIO[11] - ADC input - SPI IN - IN PWM - OpAmp1 Out Full driver connected to VGPIO_SPI Full driver BB (can be powered by V3v3 with a metal change) Full driver connected to VGPIO_SPI GPIO[12] - ADC input - SPI IN - OpAmp2 in+ - STEP_REQ - ADC input GPIO[13] - SPI IN - OpAmp2 in- GPIO[14] - ADC input - SPI IN - OpAmp2 Out Full driver connected to VGPIO_SPI 1. In this table are used the abbreviations of the following In Table 40. 2. GPIO[8] input Schmitt trigger is disabled by default (after a reset) to be able to read the digital value from this pin it needs to be enabled writing a logic ‘1’ in the EnGpio8DigIn in CurrDacCtrl register. 96/139 Doc ID 17713 Rev 1 L6460 Table 40. Abbreviations Meaning Input to the ADC system. Digital state of this pin is readable through SPI. Digital state of this pin can be set through SPI. Back to back high side driver. This pin can be used as minus input for comparator 1. This pin can be used as minus input for comparator 2. GPIO pins Abbreviation ADC input SPI IN SPI OUT BB Comp1 IN Comp2 IN Vaux1 FB A2DGpo Reg. Loop 3 STEP_REQ Interrupt Ctrl Vaux2 FB IN PWM Reg. Loop 1 Comp1 OUT AuxPwm1 Low Volt. Pow. Sw. 1 Reg. Loop 2 Comp2 OUT AuxPwm2 Low Volt. Pow. Sw. 2 Reg. Loop 3 AuxPwm3 CurrDAC AuxPwm4 OpAmp1 in+ OpAmp1 inOpAmp1 Out OpAmp2 in+ OpAmp2 in- This pin can be used as feedback input for AUX1 regulator obtained by using bridge 3. This pin can be used to carry out the A2DGpo value related to the ADC conversion L6460 is doing. This pin can be used as output of the regulation loop used by AUX3 regulator obtained by using bridge 4. This pin can be used to request a stepper sequencer evolution step. This pin can be used to carry out the interrupt controller circuit output. This pin can be used as feedback pin by AUX2 regulator obtained by using bridge 3 This pin can be used to provide an external PWM to bridges. This pin can be used as output of the regulation loop used by AUX1 regulator. This pin can be used as output of the comparator 1. This pin can be used to carry out the PWM generated by AuxPwm1 circuit. This pin can be used as output of low voltage power switch 1. This pin can be used as output of the regulation loop used by AUX2 regulator. This pin can be used as output of the comparator 2. This pin can be used to carry out the PWM generated by AuxPwm2 circuit. This pin can be used as output of low voltage power switch 2. This pin can be used as output of the regulation loop used by AUX3 regulator. This pin can be used to carry out the PWM generated by AuxPwm3 circuit. This pin can be used to carry out the output of the current DAC circuit. This pin can be used to carry out the PWM generated by AuxPwm4 circuit. This pin can be used as operational amplifier 1 non-inverting input. This pin can be used as operational amplifier 1 inverting input. This pin can be used as operational amplifier 1 output. This pin can be used as operational amplifier 2 non-inverting input. This pin can be used as operational amplifier 2 inverting input. Doc ID 17713 Rev 1 97/139 GPIO pins Table 40. Abbreviations (continued) Meaning This pin can be used as operational amplifier 2 output. This pin is used to determine the SPI ID1 bit value. This pin is used to determine the SPI ID2 bit value. L6460 Abbreviation OpAmp2 Out ID 1 ID 2 Slave Control This pin is used as slave control when the IC is configured as master. Hereafter are reported the detailed specifications for each GPIO. To enable the functionality of the GPIO as output pin, the relative GpioOutEnable[14:0] bit must be enabled in GpioOutEnable register. Each GPIO could be configured by setting the appropriate GpioXMode[2:0] in the GpioCtrlX register. 98/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.1 GPIO[0] The GPIO[0] truth table is (for the abbreviation list please refer to Table 40). Table 41. State at StartUp GPIO[0] truth table GPIO[0] SPI BITS GpioOut Enable [0] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 1 Mode[0] X X 0 1 0 1 0 1 0 1 Detection of StartUp config HiZ (SPI_IN) SPI OUT InterruptCtrl AuxPwm1 AuxPwm2 SPI OUT inverted InterruptCtrl inverted AuxPwm1 inverted AuxPwm2 inverted (1) (1) (1) (1) (1) (1) (1) (1) Note 1 0 0 0 0 0 0 0 0 0 See Chapter 8 1. In all configurations in which GPIO[0] is enabled as output: a) the GPIO[0] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[0] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[0] pin is an open drain output. Doc ID 17713 Rev 1 99/139 GPIO pins Figure 30. GPIO[0] block diagram L6460 V 3v3 To Serial Interface To ADC V 3v3 To Control Logic Start up pin State Detect circuit V 3v3 V 3v3 GPIO[0] From Serial Interface EnStartUpDtc From Power Up FSM Logic Decode GPIO[0] Driver 100/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.2 GPIO[1] The GPIO[1] truth table is (for the abbreviation list please refer to Table 40). Table 42. GPIO[1] truth table GPIO[1] SPI BITS GpioOut Enable [1] X 0 0 1 1 1 1 1 1 1 1 Function Mode[2] X 0 1 0 0 0 0 1 1 1 1 Mode[1] X X X 0 0 1 1 0 0 1 1 Mode[0] X X X 0 1 0 1 0 1 0 1 AUX1 FB HiZ (SPI_IN) Comp1 IN SPI OUT AuxPwm1 AuxPwm2 InterruptCtrl SPI OUT inverted AuxPwm1 inverted AuxPwm2inverted IntCtrlinverted (2) (2) (2) (2) (2) (2) (2) (2) (2) (1) AUX1Enable or AUX1System 1 0 0 0 0 0 0 0 0 0 0 Note 1. AUX1Enable or AUX1System bit =1 represent the case in which AUX1 is used as a system or not system regulator. 2. In all configurations in which GPIO[1] is enabled as output: a) the GPIO[1] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[1] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[1] pin is an open drain output. Doc ID 17713 Rev 1 101/139 GPIO pins Figure 31. GPIO[1] block diagram L6460 V 3v3 To Serial Interface To ADC To AUX1 Feedback comparator GPIO[1] V 3v3 From Serial Interface Logic Decode V 3v3 Gpio[1] Driver 102/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.3 GPIO[2] The GPIO[2] truth table is (for the abbreviation list please refer to Table 40). Table 43. GPIO[2] truth table GPIO[1] SPI BITS GpioOut Enable [1] X 0 0 1 1 1 1 1 1 1 1 Function Mode[2] X 0 1 0 0 0 0 1 1 1 1 Mode[1] X X X 0 0 1 1 0 0 1 1 Mode[0] X X X 0 1 0 1 0 1 0 1 AUX2 FB HiZ (SPI_IN) Comp1 IN SPI OUT AuxPwm2 AuxPwm3 InterruptCtrl SPI OUT inverted AuxPwm2 inverted AuxPwm3 inverted IntCtrlinverted (2) (2) (2) (2) (2) (2) (2) (2) (2) (1) AUX2Enable or AUX2System 1 0 0 0 0 0 0 0 0 0 0 Note 1. AUX2Enable or AUX2System bit =1 represent the case in which AUX1 is used as a System or Not System regulator. 2. In all configurations in which GPIO[2] is enabled as output: a) the GPIO[2] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[2] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[2] output is directly connected to ExtPWM3 input for Bridge 3 or 4 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM3 is selected for bridge 3 or 4; d) the GPIO[2] pin is an open drain output. Doc ID 17713 Rev 1 103/139 GPIO pins Figure 32. GPIO[2] block diagram L6460 To ExtPWM3 To Serial Interface V 3v3 To ADC To AUX2 Feedback comparator GPIO[2] V 3v3 From Serial Interface Logic Decode V 3v3 Gpio[2] Driver 104/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.4 GPIO[3] The GPIO[3] truth table is (for the abbreviation list please refer to Table 40). Table 44. State at StartUp GPIO[3] truth table GPIO[3] SPI BITS GpioOut Enable [3] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] Mode[0] X X 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 Detection of StartUp config HiZ (SPI_IN) SPI OUT AuxPwm1 AuxPwm2 AuxPwm2 SPI OUT inverted AuxPwm1 inverted AuxPwm2 inverted AuxPwm3 inverted (1) (1) (1) (1) (1) (1) (1) (1) Note 1 0 0 0 0 0 0 0 0 0 See Chapter 8 1. In all configurations in which GPIO[3] is enabled as output: a) the GPIO[3] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[3] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[3] pin is an open drain output. Doc ID 17713 Rev 1 105/139 GPIO pins Figure 33. GPIO[3] block diagram L6460 V 3v3 To Serial Interface To ADC V 3v3 To Control Logic Start up pin State Detect circuit GPIO[3] V 3v3 From Serial Interface EnStartUpDtc From Power Up FSM Logic Decode V 3v3 Gpio[3] Driver 106/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.5 GPIO[4] The GPIO[4] truth table is (for the abbreviation list please refer to Table 40). Table 45. State at StartUp GPIO[4] truth table GPIO[4] SPI BITS GpioOut Enable [4] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 1 Mode[0] X X 0 1 0 1 0 1 0 1 Detection of StartUp config HiZ (SPI_IN) SPI OUT Interrupt Ctrl AuxPwm1 AuxPwm3 SPI OUT inverted Interrupt Ctrl AuxPwm1 inverted AuxPwm3 inverted (1) (1) (1) (1) (1) (1) (1) (1) Note 1 0 0 0 0 0 0 0 0 0 See Chapter 8 1. In all configurations in which GPIO[4] is enabled as output: a) the GPIO[4] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[4] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[4] pin is an open drain output. Doc ID 17713 Rev 1 107/139 GPIO pins Figure 34. GPIO[4] block diagram L6460 V 3v3 To Serial Interface To ADC V 3v3 To Control Logic Start up pin State Detect circuit V 3v3 GPIO[4] V 3v3 From Serial Interface EnStartUpDtc From PowerUp FSM Logic Decode Gpio[4] Driver 108/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.6 GPIO[5] The GPIO[5] truth table is (for the abbreviation list please refer to Table 40). Table 46. GPIO[5] truth table GPIO[5] SPI BITS GpioOut enable[5] X X 0 1 1 1 1 1 1 1 1 Function Mode[2] Mode[1] Mode[0] X X X 0 0 0 0 1 1 1 1 X X X 0 0 1 1 0 0 1 1 X X X 0 1 0 1 0 1 0 1 Slave control Reg Loop1 OUT HiZ (SPI_IN) SPI OUT Comp1OUT Reg Loop1 OUT AuxPwm3 SPI OUT inverted Comp1OUT inverted Reg Loop1 OUT inverted AuxPwm3 inverted (3) (3) (3) (3) (3) (3) (3) (3) (3) AUX1 system Master(1) and Vloop1 external(2) 1 0 0 0 0 0 0 0 0 0 0 X 1 0 0 0 0 0 0 0 0 0 Note 1. Master bit is at logic level “1” when L6460 is used as a master device (seeChapter 8) 2. This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized (and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in CoreConfigReg register. 3. In all configurations in which GPIO[5] is enabled as output: a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[5] pin is a rail to rail, back to back output supplied by V3v3. Doc ID 17713 Rev 1 109/139 GPIO pins Figure 35. GPIO[5] block diagram L6460 To internal Logic & SPI V 3v3 To ADC V 3V3 V 3v3 GPIO[5] Logic Decode From Control logic Back to Back Driver 110/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.7 GPIO[6] The GPIO[6] truth table is (for the abbreviation list please refer to Table 40): Table 47. StdByMode GPIO[6] truth table GPIO[6] SPI BITS AEnLow VSw[1] X 1 0 0 0 0 0 0 0 0 GpioOut Mode[2] Mode[1] Mode[0] enable[6] X X 0 1 1 1 1 1 1 1 X X X 0 0 0 0 1 1 1 X X X 0 0 1 1 0 0 1 X X X 0 1 0 1 0 1 1 Function Note 1 0 0 0 0 0 0 0 0 0 Low Volt. Pow. Sw. 1 Low Volt. Pow. Sw. 1 HiZ (SPI_IN) SPI OUT A2DGpo AuxPwm2 Comp2OUT A2DGpo inverted AuxGpPwm2 inverted Comp2OUT inverted (2) (2) (2) (2) (2) (2) (2) (1) 1. When EnLowVSw[1]= ‘1’ the GpioOutEnable[6] bit is forced to 0. 2. In all configurations in which GPIO[6] is enabled as output: a) the GPIO[6] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[6] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[6] pin is a rail to rail output supplied by VGPIO_SPI. Doc ID 17713 Rev 1 111/139 GPIO pins Figure 36. GPIO[6] block diagram V GPIO_SPI L6460 Power Switch 1 To internal Logic & SPI V 3v3 To ADC EnPass1 V 3v3 From Serial Interface Stand By mode V 3v3 GPIO[6] Logic Decode Gpio[6] Driver 112/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.8 GPIO[7] The GPIO[7] truth table is (for the abbreviation list please refer to Table 40). Table 48. GPIO[7] truth table GPIO[7] SPI BITS EnLowVSw[2] GpioOut enable[7] X 0 1 1 1 1 1 1 1 Function Mode[2] Mode[1] Mode[0] X X 0 0 0 0 1 1 1 X X 0 0 1 1 0 0 1 X X 0 1 0 1 0 1 1 Low Volt. Pow. Sw. 2 HiZ (SPI_IN) SPI OUT AuxPwm1 AuxPwm3 Comp1OUT AuxPwm1 inverted AuxPwm3 inverted Comp1OUT inverted (2) (2) (2) (2) (2) (2) (2) (1) Note 1 0 0 0 0 0 0 0 0 1. When EnLowVSw[2] = ‘1’ the GpioOutEnable[7] bit is forced to 0. 2. In all configurations in which GPIO[7] is enabled as output: a) the GPIO[7] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[7] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[7] pin is a rail to rail output supplied by VGPIO_SPI. Doc ID 17713 Rev 1 113/139 GPIO pins Figure 37. GPIO[7] block diagram L6460 V GPIO_SPI Power Switch 2 To internal Logic & SPI V 3v3 To ADC EnPass2 V GPIO_SPI V 3v3 From Serial Interface GPIO[7] Logic Decode 114/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.9 GPIO[8] The GPIO[8] truth table is (for the abbreviation list please refer to Table 40). Table 49. EnDac GPIO[8] truth table GPIO[8] SPI bits (1) GpioOut enable[8] X 0 1 1 1 1 1 1 1 Function (2) Mode[2] X X 0 0 0 0 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 Mode[0] X X 0 1 0 1 0 1 1 CurrDAC HiZ (SPI_IN) SPI OUT AuxPwm1 AuxPwm3 Comp2OUT AuxPwm1 inverted AuxPwm3 inverted Comp2OUT inverted Note 1 0 0 0 0 0 0 0 0 (3) (4) (4) (4) (4) (4) (4) (4) (4) 1. The EnDAC bit in the CurrDacCtrl register enables the Current DAC (seeChapter 17) 2. This pin is 5 volt input tolerant. 3. When EnDAC = ‘1’ the GpioOutEnable[8] bit is forced to 0. The current DAC circuit is directly connected to GPIO[8] pin so as soon as it is enabled it will sink current from pin. 4. The GPIO[8] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function). To avoid affecting the precision of CurrDAC when this is used to sink very low currents, it is necessary to enable the digital input functionality of GPIO[8]. Therefore to read their values through SPI interface (SPI_IN function), it is necessary to enable the EnGpio8DigIn bit in the CurrDacCtrl register. Doc ID 17713 Rev 1 115/139 GPIO pins Figure 38. GPIO[8] block diagram L6460 V 3v3 To internal Logic & SPI EnGpio8 DigIn To ADC V 3v3 From Serial Interface Logic Decode V 3v3 GPIO[8] Gpio[8] Driver From Serial Interface Current Sink Circuit 116/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.10 GPIO[9] The GPIO[9] truth table is (for the abbreviation list please refer to Table 40). Table 50. GPIO[9] truth table GPIO[9] SPI bits Op1EnPlusPin (1) GpioOut enable[9] X 0 1 1 1 1 1 1 1 Function (2) Mode[2] X X 0 0 0 0 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 Mode[0] X X 0 1 0 1 0 1 1 OpAmp1 in+ HiZ (SPI_IN) SPI OUT Interrupt Ctrl AuxPwm2 Reg Loop 3 Interrupt Ctrl inverted AuxPwm2 inverted Reg Loop 3 inverted Note 1 0 0 0 0 0 0 0 0 (3) (4) (4) (4) (4) (4) (4) (4) 1. The Op1EnPlusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to GPIO[9] pin. 2. The GPIO[9] pin is used by the system when firmware requires the ID read action (Chapter 25) 3. When Op1EnPlusPin = ‘1’ the GpioOutEnable[9] bit is forced to 0. 4. In all configurations in which GPIO[9] is enabled as output: a)the GPIO[9] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[9] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c)please note that GPIO[9] output is directly connected to ExtPWM1 input for Bridge 1 or 2 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM1 is selected for bridge 1 or 2; d)the GPIO[9] pin is a rail to rail output supplied by VGPIO_SPI. Doc ID 17713 Rev 1 117/139 GPIO pins Figure 39. GPIO[9] block diagram L6460 To internal Logic & SPI ID1 SampleID Pin State Sample Circuit V 3v3 To ADC V GPIO_SPI GPIO[9] V 3v3 From SPI Logic Decode Gpio[9] Driver To OpAmp1 In+ 118/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.11 GPIO[10] The GPIO[10] truth table is (for the abbreviation list please refer to Table 40). Table 51. GPIO[10] truth table GPIO[10] SPI bits Op1EnPlusPin (1) GpioOut enable[10] X 0 1 1 1 1 1 1 1 Function (2) Mode[2] X X 0 0 0 0 1 1 0 Mode[1] X X 0 0 1 1 0 0 0 Mode[0] X X 0 1 0 1 0 1 0 OpAmp1 inHiZ (SPI_IN) SPI OUT Interrupt Ctrl AuxPwm2 AuxPwm3 Interrupt Ctrl inverted AuxPwm2 inverted AuxPwm3 inverted Note 1 0 0 0 0 0 0 0 0 (3) (4) (4) (4) (4) (4) (4) (4) 1. The Op1EnMinusPin bit in the OpAmp1Ctrl register enables the connection of the positive input of Op1 to GPIO[10] pin. 2. The GPIO[10] pin is used by the system when firmware requires the ID read action (Chapter 25) 3. When Op1EnPlusPin = ‘1’ the GpioOutEnable[10] bit is forced to 0. 4. In all configurations in which GPIO[10] is enabled as output: a) the GPIO[10] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[10] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[10] output is directly connected to ExtPWM2 input for bridge 1 or 2 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM2 is selected for bridge 1 or 2; d) the GPIO[10] pin is a rail to rail output supplied by VGPIO_SPI. Doc ID 17713 Rev 1 119/139 GPIO pins Figure 40. GPIO[10] block diagram L6460 To internal Logic & SPI ID2 SampleID Pin State Sample Circuit V 3v3 To ADC V GPIO_SPI GPIO[10] V 3v3 From SPI Logic Decode Gpio[10] Driver To OpAmp1 In - 120/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.12 GPIO[11] The GPIO[11] truth table is (for the abbreviation list please refer to Table 40). Table 52. EnOpl GPIO[11] truth table GPIO[11] SPI bits (1) GpioOut enable[11] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 1 Mode[0] X X 0 1 0 1 0 1 0 1 OpAmp1 Out HiZ (SPI_IN) SPI OUT A2DGpo AuxPwm1 AuxPwm2 SPI OUT inverted A2DGpo inverted AuxPwm1 inverted AuxPwm2 inverted Note 1 0 0 0 0 0 0 0 0 0 (2) (3) (3) (3) (3) (3) (3) (3) (3) 1. The EnOp1 bit in the OpAmp1Ctrl register enables the operational amplifier 1. 2. When EnOp1 = ‘1’ the GpioOutEnable[11] bit is forced to 0. 3. In all configurations in which GPIO[11] is enabled as output: a) the GPIO[11] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[11] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[11] output is directly connected to ExtPWM4 input for bridge 3 or 4 and therefore particular care must be taken in order to avoid wrong PWM signals when ExtPWM4 is selected for bridge 3 or 4; d) the GPIO[11] pin is a rail to rail output supplied by VGPIO_SPI. Doc ID 17713 Rev 1 121/139 GPIO pins Figure 41. GPIO[11] block diagram L6460 To internal Logic & SPI V 3v3 To ADC V GPIO_SPI V 3v3 GPIO[11] From Central Logic Logic Decode OpAmp 1 122/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.13 GPIO[12] The GPIO[12] truth table is (for the abbreviation list please refer to Table 40. Table 53. AUX2enable or AUX2syste m (1) 1 0 0 0 0 0 0 0 0 0 Op2En PlusPin GpioOut Mode[2] Mode[1] Mode[0] enable[12] X X 0 1 1 1 1 1 1 1 X X X 0 0 0 0 1 1 1 X X X 0 0 1 1 0 0 1 X X X 0 1 0 1 0 1 1 GPIO[12] truth table GPIO[12] SPI bits Function Note X 1 0 0 0 0 0 0 0 0 RegLoop2 OpAmp2 in+ HiZ (SPI_IN) SPI OUT Interrupt Ctrl Comp2OUT RegLoop2 Interrupt Ctrl inverted Comp2OUT inverted RegLoop2 inverted (3) (3) (3) (3) (3) (3) (3) (2) 1. AUX2Enable or AUX2System bit =1 represent the case in which AUX2 is used as a regulator (system or not system). 2. When Op2EnPlusPin = ‘1’ the GpioOutEnable[11] bit is forced to 0. 3. In all configurations in which GPIO[12] is enabled as output: a) the GPIO[12] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[12] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) please note that GPIO[12] output is directly connected to StepCmd input for stepper driver and therefore particular care must be taken in order to avoid wrong PWM signals when StepCmd is selected for stepper driver (STEP_REQUEST function) d) the GPIO[12] pin is a rail to rail, back to back output supplied by VGPIO_SPI. Doc ID 17713 Rev 1 123/139 GPIO pins Figure 42. GPIO[12] block diagram L6460 To internal Logic & SPI V 3v3 To ADC V 3v3 From SPI Logic Decode V GPIO_SPI GPIO[12] To OpAmp2 In+ Back to Back Driver 124/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.14 GPIO[13] The GPIO[13] truth table is (for the abbreviation list please refer to Table 40). Table 54. GPIO[13] truth table GPIO[13] SPI BITS Op2En mimusPin(1) 1 0 0 0 0 0 0 0 0 GpioOut enable[13] X 0 1 1 1 1 1 1 1 Mode[2] X X 0 0 0 0 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 Mode[0] X X 0 1 0 1 0 1 1 OpAmp2 inHiZ (SPI_IN) SPI OUT AuxPwm1 Reg Loop 3 AuxPwm3 AuxPwm1 inverted Reg Loop 3 inverted AuxPwm3 inverted (3) (3) (3) (3) (3) (3) (3) (2) Function Note 1. The Op2EnMinusPin bit in the OpAmp2Ctrl register enables the connection of the positive input of Op1 to GPIO[13] pin. 2. When Op2EnMinusPin = ‘1’ the GpioOutEnable[13] bit is forced to 0. 3. In all configurations in which GPIO[9] is enabled as output: a) the GPIO[13] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[13] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[13] pin is a rail to rail output supplied by VGPIO_SPI. Doc ID 17713 Rev 1 125/139 GPIO pins Figure 43. GPIO[13] block diagram L6460 To internal Logic &SPI V 3v3 To ADC GPIO[13] V 3v3 From SPI Logic Decode V GPIO_SP Gpio[13] Driver To OpAmp2 In - 126/139 Doc ID 17713 Rev 1 L6460 GPIO pins 22.15 GPIO[14] The GPIO[14] truth table is (for the abbreviation list please refer to Table 40). Table 55. EnOp2 (1) GPIO[14] truth table GPIO[14] SPI bits GpioOut enable[14] X 0 1 1 1 1 1 1 1 1 Function Mode[2] X X 0 0 0 0 1 1 1 1 Mode[1] X X 0 0 1 1 0 0 1 1 Mode[0] X X 0 1 0 1 0 1 0 1 OpAmp2 Out HiZ (SPI_IN) SPI OUT Interrupt Ctrl AuxPwm2 AuxPwm3 SPI OUT inverted Interrupt Ctrl inverted AuxPwm2 inverted AuxPwm3 inverted (3) (3) (3) (3) (3) (3) (3) (3) (2) Note 1 0 0 0 0 0 0 0 0 0 1. The EnOp2 bit in the OpAmp2Ctrl register enables the operational amplifier 2. 2. When EnOp2 = ‘1’ the GpioOutEnable[14] bit is forced to 0. 3. In all configurations in which GPIO[14] is enabled as output: a) the GPIO[14] pin can be always used as an analog input to the ADC system (ADC function) by writing its address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion; b) the GPIO[14] pin can be always used as a digital input so its value can be always read through SPI interface (SPI_IN function); c) the GPIO[14] pin is a rail to rail output supplied by VGPIO_SPI. Doc ID 17713 Rev 1 127/139 GPIO pins Figure 44. GPIO[14] block diagram L6460 To internal Logic & SPI V 3v3 To ADC V GPIO_SP V 3v3 GPIO[14] From Central Logic Logic Decode Gpio[14] Driver OpAmp 2 128/139 Doc ID 17713 Rev 1 L6460 Serial interface 23 Serial interface L6460 can communicate with an external microprocessor by using an integrated slave SPI (serial protocol interface). Through this interface almost all L6460 functionalities can be controlled and all the ICs can be seen as a register map made by 128 register of 16-bit each. The SPI is a simple industry standard communications interface commonly used in embedded systems and it has the following four I/O pins: – – – – MISO (master input slave output) MOSI (master output slave input) SCLK (serial clock [controlled by the master]) nSS (slave select active low [controlled by the master]) The “MISO” (master in, slave out) signal carries synchronous data from the slave to the master device. The MOSI (master out, slave in) signal carries synchronous data from the master to the slave device. The SCLK signal is driven by the master, synchronizing all data transfers. Each SPI slave device has one nSS signal that is an active-low slave input/master output pin. Slave devices do not respond to transactions unless their nSS input signal is driven low. Master device interfacing with multiple SPI slave devices has an nSS signal for each slave device. L6460 will maintain its MISO pin in high impedance until it does not recognize its address in serial frame. 23.1 Read transaction A read transaction (see Figure 45) is always started by the master device that lowers the nSS pin. The other bits are then sent on the MOSI pin with this order: 1. 2. 3. 4. 7-bit representing the address of the register that must be read (MSB first [A6…A0]); 2-bit that must be “10” for a read transaction; 2-bit representing L6460 IC address; 1-bit reserved for future use that must be set at “0”. At this point the data stored in the register at the selected address will be shifted out on the MISO pin. The read operation is terminated by raising the signal on nSS pin. Doc ID 17713 Rev 1 129/139 Serial interface Figure 45. SPI read transaction L6460 nSS SCLK Register Address field MOSI MISO A6 A0 Control IC Field address Data Field High Impedance D15 D0 23.2 Write transaction A write transaction (see Figure 46) is always started by the master lowering the signal on nSS pin. The other bits are then sent on the MOSI pin with this order: 1. 2. 3. 4. 7-bit representing the address of the register that must be written (MSB first [A6…A0]); 2-bit that must be “01” for a read transaction; 2-bit representing L6460 IC address; 1-bit reserved for future use that must be set at “0”. The data to be written (MSB first D15…D0) are then read from MOSI pin. The length of data field can be 16 or 20 bits, but only the first 16-bit are accepted as valid data. Data is latched on rising edge of the nSS line. Figure 46. SPI write transaction nSS SCLK Register Address field Control IC Field addres A0 D15 Data Field D0 MOSI MISO A6 High Impedance The SPI input and output timing definitions are shown in the Table 5 on page 17 130/139 Doc ID 17713 Rev 1 L6460 Figure 47. SPI input timing diagram Serial interface T nss nSS setup T sclk period T nss hold T nss min V IH V IL T sclk hig T sclk low SCLK V IH V IL V IH V IL T mosi T mosi T sclk rise MOSI T sclk fall setup hold Figure 48. SPI output timing diagram T sclk T nss nSS setup period T nss hold T nss min V IH V IL T sclk high T sclk low SCLK V IH V IL MOSI T sclk rise T sclk fall MISO T miso V OH V OL valid T miso disable Doc ID 17713 Rev 1 131/139 Registers list L6460 24 Registers list Many of the L6460 functionalities are controlled or can be supervised by accessing to the relative register through serial interface. All these registers can be seen from the user (microcontroller) point of view as a register table. Each register is one word wide (16-bit) and can be read using a 7-bit address Table 56. Register address map Name DevName CoreConfigReg ICTemp ICStatus EnTestRegs SampleID WatchDogCfg WatchDogStatus SoftResReg Comment Read only Address[6:0] (binary) 100_0000 100_0001 100_0010 100_0011 100_0100 100_0101 100_0110 100_0111 100_1000 100_1001 100_1010 100_1011 HibernateStatus HibernateCmd 100_1100 100_1101 100_1110 Mtr1_2PwrCtrl MainVSwCfg 100_1111 101_0000 101_0001 MainlinCfg 101_0010 101_0011 SwCtrCfg 101_0100 101_0101 101_0110 101_0111 StdByMode 101_1000 101_1001 101_1010 101_1011 GpioOutEnable GpioCtrl1 GpioCtrl2 GpioCtrl3 A2DControl A2DConfig1 A2DResult1 A2DConfig2 A2DResult2 IntCtrlCfg IntCtrlCtrl DigCmpCfg DigCmpValue Name AuxPwm1Ctrl AuxPwm2Ctrl GpPwm3Base GpPwm3Ctrl Comment Address[6:0] (binary) 000_0000 000_0001 000_0010 000_0011 000_0100 000_0101 000_0110 000_0111 000_1000 000_1001 000_1010 000_1011 000_1100 000_1101 000_1110 000_1111 001_0000 001_0001 001_0010 001_0011 001_0100 001_0101 001_0110 001_0111 001_1000 001_1001 001_1010 001_1011 132/139 Doc ID 17713 Rev 1 L6460 Table 56. Register address map (continued) Name Comment Address[6:0] (binary) 101_1100 101_1101 101_1110 101_1111 Mtrs1_2Cfg Mtr1Cfg Mtr1Ctrl Mtr1Limit Mtr2Cfg Mtr2Ctrl Mtr2Limit 110_0000 110_0001 110_0010 110_0011 110_0100 110_0101 110_0110 110_0111 Mtrs3_4Cfg Mtr3Cfg Mtr3Ctrl Mtr3ILimit Mtr4Cfg Mtr4Ctrl Mtr4ILimit 110_1000 110_1001 110_1010 110_1011 110_1100 110_1101 110_1110 110_1111 StpCfg1 StpCfg2 StpCtrl StpCmd StpTest Aux1SwCfg Aux2SwCfg Aux3SwCfg1 Aux3SwCfg2 Power Mode Control 111_0000 111_0001 111_0010 111_0011 111_0100 111_0101 111_0110 111_0111 111_1000 111_1001 111_1010 111_1011 CurrDacCtrl 111_1100 REV_MFCT RESERVED OpAmpCtrl1 OpAmpCtrl2 LowVSwitchCtrl Name GpioPadVal GpioOutVal Registers list Address[6:0] (binary) 001_1100 001_1101 001_1110 001_1111 010_0000 010_0001 010_0010 010_0011 010_0100 010_0101 010_0110 010_0111 010_1000 010_1001 010_1010 010_1011 010_1100 010_1101 010_1110 010_1111 011_0000 011_0001 011_0010 011_0011 011_0100 011_0101 011_0110 011_0111 011_1000 011_1001 011_1010 011_1011 011_1100 Comment Read only Doc ID 17713 Rev 1 133/139 Registers list Table 56. Register address map (continued) Name Comment Address[6:0] (binary) 111_1101 111_1110 111_1111 Name RESERVED RESERVED RESERVED L6460 Address[6:0] (binary) 011_1101 011_1110 011_1111 Comment 134/139 Doc ID 17713 Rev 1 25 L6460 Start up configuration JP2 JP3 JP4 R17 CON3 100nF J4 R12 Vsupply R42 0.047 1W D6 Q5 STD12NF06L U1 L2 C2 1uF D7 6CWQ06 Vsupply C7 C3 1uF 1210 +3_3VS Gpio6 +3_3VS Gpio7 C11 C9 100nF nRESET C8 100nF C10 100nF R14 1K V3v 3 100nF R21 1K C26 330uF 25V + C14 100nF C15 100pF R43 22K R44 39K R37 Gpio8 C18 1nF JP8 1nF C17 330 LED D4 1 2 DC2_plus DC2_minus Gpio13 Gpio14 1K 1 2 DC1_plus DC1_minus 1 C31 R16 1nF 1K 1nF J3 1 2 3 Gpio6 Gpio7 Gpio11 Gpio12 1 +3_3VS R15 GND 1K C19 C20 Gpio1 Gpio2 1 2 3 4 5 6 7 8 9 10 CON10 1 V3v 3 J11 J2 R1 R2 D1 Vsupply GND 1 2 Vsupply 4.7K 4.7K LED 3 2 3 2 3 2 J7 VSWMAIN GND 3.3V 2.5A 1 2 nSS Gpio0 Gpio1 Gpio2 J1 nAWAKE nSS R18 1K 12 34 56 78 9 10 Schematic examples CON5X2 C1 1uF Vsupply MISO MOSI D5 R13 D C1_plus VSWDRV_sns VSWDRV_FB Gpio4 Gpio3 DC1_minus DC1_minus GND1 GND2 DC2_minus DC2_minus Gpio2 Gpio1 Gpio0 nSS DC2_plus +3_3VS 3 Q3 BC846B Gpio8 C5 680nF SCLK LED 1 330 2 J8 R10 4.7K Q4 BSP51 VLINMAIN GND 1.2V 0.5A + C27 10uF 10V 1 2 C29 DC3_sense Gpio5 Gpio9 Gpio10 Gpio11 N.C. DC3_minus DC3_sense DC4_sense DC4_minus N.C. Gpio14 Gpio13 Gpio12 nAWAKE DC4_sense R41 1K C16 680uF 50V C4 1uF 2 Gpio12 Gpio13 Gpio14 Gpio11 Gpio10 Gpio9 Gpio5 3 2 Figure 49. Application with 2 DC motors, 1 stepper motor and 3 power supplies Doc ID 17713 Rev 1 TAB TAB TAB TAB 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DC2_plus Vsupply MISO MOSI VLINmain_FB VLINmain_OUT Gpio8 VSWmain_SW Vsupply VSWmain_FB VREF_FB IREF_FB SCLK Vsupply N.C DC4_plus TAB TAB TAB TAB TAB DC1_plus Vsupply CPL CPH Vpump VSWDRV_gate VSWDRV_SW Gpio6 VGPIO_SPI Gpio7 Vsupply Int V3v 3 nRESET Vsupply DC3_plus N.C 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 nRESET MISO MOSI SCLK 33uH 3A Coilcraf t DO5010H-333MLD +3_3VS L1 C12 C13 100pF 100nF + C25 470uF 16V D3 STPS3L60U 100nF 3 R39 Open R40 560 C28 330nF 73 72 71 70 3 2 1 Gpio5 Gpio3 Gpio4 Slave Master R38 Open R36 2.2K LED 2.2K J9 1 2 VSWDRV GND 12V 3A 33uH 4.5A Coilcraf t DO5040H-333MLD JP1 L6460 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Q1 BC846B 100nF 1 RESET R5 4.7K R8 4.7K + 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 J10 V3v 3 +3_3VS nAWAKE R7 4.7K D2 +3_3VS R19 R20 1K 1K Device ID 3 2 3 2 1 JP5 1 JP6 ID2 1nF 1nF J5 1 2 J6 1 2 C22 1nF C21 1nF Phase B Phase A ID1 C23 C24 Stepper nRESET JP7 R11 330 nSS nSS SCLK Close on Master AWAKE C6 100nF JP9 4.7K R9 4.7K R6 Q2 BC846B 1 LED R3 4.7K MISO MOSI AWAKE 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 JP11 JP12 JP13 JP14 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 RESET CON17X2 JP15 JP16 R22 1 R23 2.2 R24 3.9 R25 3.9 R26 2.2 R27 1 Schematic examples 135/139 3 2 3 4 2 R15 1K C20 470uF 63V 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 C21 1uF 2 R12 R13 4.7K 3 Q4 BSP51 + L3 33uH 2A Coilcraf t DO3316P-333MLD J9 1 2 D4 STPS1L60U +3_3VS R18 R22 1K 1K Device ID 1 JP6 3 2 1 JP7 L5 33uH 2A Coilcraf t DO3316P-333MLD J11 1 2 VSWDC3GND 5V 1A ID2 R21 1K Gpio1 3 2 ID1 C24 470uF 16V + C25 100nF C26 100pF R16 820 VDC3+ GND 1.8V 1A 3 D3 BZX284C15 Gpio14 Gpio13 Gpio12 Gpio5 Gpio9 Gpio10 Gpio11 C22 22uF 16V +Vop J10 R17 L4 R20 10K 0.1% + D6 STPS3L60U U2A LM358 R23 10K 0.1% V3v 3 R26 4.7K nAWAKE 3 C23 100nF 0.1 1W 33uH 2A Coilcraf t DO3316P-333MLD D5 ES3B BATTERY + GND 12V 1.5A max R43 1K C27 470uF 16V C28 100nF 1 2 2 R19 10K 1 C32 100pF 8 3 Q9 R44 2.2K BC857B 3 2 R25 150K 0.1% R28 150K 0.1% Close on Master AWAKE JP9 R31 4.7K 4.7K 2 R24 10K + 4 R45 1K D16 Y ELLOW LED Charge in progress 1 +Vop 8 R48 330 C5 10pF R29 Q5 BC846B 1 D7 STPS1L60U U2B 5 C14 100nF R49 1K 4 C29 470uF 16V + C30 100nF C31 100pF Gpio2 + 6 7 LM358 R6 4.7K R27 1K R42 680 D17 RED LED Disconnect the battery Figure 50. Application with 2 DC motors, a battery charger and 5 power supplies R30 1K D15 LED GREEN 2 136/139 J2 Vsupply R1 JP8 1 2 3 CON3 R2 R3 J4 R35 Vsupply R4 0.047 1W D11 R36 C3 1nF 1nF C4 D10 1 2 D20 LED RED DC2_plus DC2_minus 1K 1 2 DC1_plus DC1_minus 1K 1nF 1nF J3 1K C1 C2 10K 1W JP3 1 D18 LED GREEN D19 LED RED JP2 1 LED GREEN Vsupply GND 1 2 +3_3VS 4.7K 330 JP1 1 R46 10K 1W V3v 3 J12 R32 D8 Start up configuration 3 2 3 2 3 2 Gpio6 Gpio7 Gpio8 Gpio11 Gpio12 +3_3VS 1 2 3 4 5 6 7 8 CON8 330 J5 1 2 Gpio2 Gpio1 Gpio0 nSS Gpio4 Gpio3 Schematic examples To PractiSpin J1 nRESET JP4 D9 R33 nSS nSS SCLK LED GREEN R34 MISO MOSI AWAKE 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 D21 LED GREEN 10K 1W R47 Q1 STD12NF06L U1 R5 2.2K 2.2K 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 RESET CON34A VSWMAIN GND 3.3V 3A Slave Master LED GREEN J6 33uH 4.5A Coilcraf t DO5040H-333MLD L2 C9 330uF 25V + C10 100pF C11 100pF R8 15K 1 2 J7 nAWAKE nSS 12 34 56 78 9 10 70 71 72 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nRESET MISO MOSI SCLK R7 1K TAB TAB TAB TAB 3 2 1 Gpio5 JP5 LED GREEN 33uH 3A Coilcraf t DO5010H-333MLD +3_3VS L1 C6 100pF C7 100nF + C8 470uF 16V D1 STPS3L60U L6460 VSWDRV GND 12.8V 3A CON10A R37 +3_3VS Vsupply MISO MOSI C13 1uF C12 100nF Vsupply DC1_plus VSWDRV_sns VSWDRV_FB Gpio4 Gpio3 DC1_minus DC1_minus GND1 GND2 DC2_minus DC2_minus Gpio2 Gpio1 Gpio0 nSS DC2_plus D12 D2 6CWQ06 R9 1K +3_3VS Gpio6 +3_3VS Gpio7 C16 C17 V3v 3 100nF R10 1K 100nF nRESET Q3 BC846B ResetOn RED LED 1 4.7K RESET R40 +3_3VS 270 D14 D13 R39 680 Q6 BC846B Q2 BSP51 C15 680nF LED 1 GREEN330 J8 R38 4.7K VLINMAIN GND 1.2V 0.5A C18 330nF + C19 10uF 10V 1 2 Doc ID 17713 Rev 1 17 18 19 20 21 22 Gpio8 23 24 25 26 27 28 SCLK 29 30 31 32 DC2_plus Vsupply MISO MOSI VLINmain_FB VLINmain_OUT Gpio8 VSWmain_SW Vsupply VSWmain_FB VREF_FB IREF_FB SCLK Vsupply N.C. DC4_plus TAB TAB TAB TAB TAB DC1_plus Vsupply CPL CPH Vpump VSWDRV_gate VSWDRV_SW Gpio6 VGPIO_SPI Gpio7 Vsupply Int V3v 3 nRESET Vsupply DC3_plus N.C. 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 + DC3_sense Gpio5 Gpio9 Gpio10 Gpio11 N.C. DC3_minus DC3_sense DC4_sense D C4_minus N.C. Gpio14 Gpio13 Gpio12 nAWAKE DC4_sense Vsupply R11 560 R14 4.7K 1W LED GREEN 1 R41 1K Q7 BC846B 1 L6460 L6460 Package mechanical data 26 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 51. TQFP64 mechanical data an package dimensions mm DIM. MIN. A A1 A2 b c D D1 D2 D3 E E1 E2 E3 e L L1 k ccc 0˚ 0.45 11.80 9.80 2.00 7.50 0.50 0.60 1.00 3.5˚ 7˚ 0.080 0˚ 0.75 0.05 0.95 0.17 0.09 11.80 9.80 2.00 7.50 12.00 10.00 12.20 10.20 0.464 0.386 0.787 0.295 0.0197 0.0177 0.0236 0.0295 0.0393 3.5˚ 7˚ 0.0031 12.00 10.00 1.00 0.22 TYP. MAX. 1.20 0.15 1.05 0.27 0.20 12.20 10.20 0.002 MIN. TYP. MAX. 0.0472 0.006 inch OUTLINE AND MECHANICAL DATA 0.0374 0.0393 0.0413 0.0066 0.0086 0.0086 0.0035 0.464 0.386 0.787 0.295 0.472 0.394 0.480 0.401 0.472 0.394 0.0078 0.480 0.401 TQFP64 (10x10x1.0mm) Exposed Pad Down 7278840 B Doc ID 17713 Rev 1 137/139 Revision history L6460 27 Revision history Table 57. Date 02-Jul-2010 Document revision history Revision 1 Initial release. Changes 138/139 Doc ID 17713 Rev 1 L6460 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2010 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 17713 Rev 1 139/139