L6730B

L6730 L6730B Adjustable step-down controller with synchronous rectification Features ■ ■ ■ Input voltage range from 1.8 V to 14 V Supply voltage range from 4.5 V to 14 V Adjustable output voltage down to 0.6 V with ±0.8% accuracy over line voltage and temperature (0°C~125°C) Fixed frequency voltage mode control tON lower than 100 ns 0% to 100% duty cycle Selectable 0.6 V or 1.2 V internal voltage reference External input voltage reference Soft-start and inhibit High current embedded drivers Predictive anti-cross conduction control Selectable uvlo threshold (5 V or 12 V BUS) Programmable high-side and low-side RDS(on) sense overcurrent protection Switching frequency programmable from 100 kHz to 1 MHz Master/slave synchronization with 180° phase shift Pre-bias start up capability (L6730) Selectable source/sink or source only capability after soft-start (L6730) Selectable constant current or hiccup mode overcurrent protection after soft-start (L6730B) Power Good output with programmable delay Overvoltage protection with selectable latched/not-latched mode Thermal shut-down Package: HTSSOP20 Table 1. Device summary Package HTSSOP20 HTSSOP20 HTSSOP20 HTSSOP20 Packing Tube Tape and reel Tube Tape and reel Order codes L6730 L6730TR L6730B L6730BTR ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HTSSOP20 Applications ■ High performance / high density DC-DC modules Low voltage distributed DC-DC niPOL converters DDR memory supply DDR memory bus termination supply December 2009 Doc ID 11938 Rev 3 1/52 www.st.com 52 Contents L6730 - L6730B Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 5 Pin connections and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Internal LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bypassing the LDO to avoid the voltage drop with low Vcc . . . . . . . . . . . 15 Internal and external references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Monitoring and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Adjustable masking time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Multifunction pin (S/O/U L6730) (CC/O/U L6730B) . . . . . . . . . . . . . . . . . 27 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Minimum ON-time TON(MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Bootstrap anti-discharging system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.14.1 5.14.2 Fan power supply failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 No-sink at zero current operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 Application details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2/52 Doc ID 11938 Rev 3 L6730 - L6730B Contents 6.2 6.3 6.4 6.5 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Two quadrant or one quadrant operation mode (L6730) . . . . . . . . . . . . . 37 7 L6730 demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.1 7.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 9 10 I/O Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 POL demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 11 12 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Doc ID 11938 Rev 3 3/52 Summary description L6730 - L6730B 1 Summary description The controller is an integrated circuit designed using BiCMOS-DMOS, v5 (BCD5) technology that provides complete control logic and protection for high performance, stepdown DC/DC and niPOL converters. It is designed to drive N-Channel MOSFETs in a synchronous rectified buck converter topology. The output voltage of the converter can be precisely regulated down to 600 mV, with a maximum tolerance of ±0.8%, or to 1.2 V, when one of the internal references is used. It is also possible to use an external reference from 0 V to 2.5 V. The input voltage can range from 1.8 V to 14 V, while the supply voltage can range from 4.5 V to 14 V. High peak current gate drivers provide for fast switching to the external power section and the output current can be in excess of 20 A, depending on the number of the external MOSFETs used. The PWM duty cycle can range from 0% to 100% with a minimum on-time (TON(MIN)) lower than 100 ns, making conversions with a very low duty cycle and very high switching frequency possible. The device provides voltage-mode control. It includes a 400 kHz free-running oscillator that is adjustable from 100 kHz to 1 MHz. The error amplifier features a 10 MHz gain-bandwidthproduct and 5 V/µs slew-rate that permits to realize high converter bandwidth for fast transient response. The device monitors the current by using the RDS(ON) of both the highside and low-side MOSFET(s), eliminating the need for a current sensing resistor and guaranteeing an effective over current-protection in all the application conditions. When necessary, two different current limit protections can be externally set through two external resistors. A leading edge adjustable blanking time is also available to avoid false overcurrent-protection (OCP) intervention in every application condition. It is possible to select the HICCUP mode or the constant current protection (L6730B) after the soft-start phase. During this phase constant current protection is provided. It is possible to select the sinksource or the source-only mode capability (before the device powers on) by acting on a multifunction pin (L6730). The L6730 disables the sink mode capability during the soft-start in order to allow a proper start-up also in pre-biased output voltage conditions. The L6730B can always sink current and, so it can be used to supply the DDR memory BUS termination. Other features include Master-Slave synchronization (with 180° phase shift), Power-Good with adjustable delay, over voltage-protection, feed back disconnection, selectable UVLO threshold (5 V and 12 V Bus), and thermal shutdown. The HTSSOP20 package allows the realization for very compact DC/DC converters. 4/52 Doc ID 11938 Rev 3 L6730 - L6730B Summary description 1.1 Figure 1. Functional description Block diagram VCC=4.5V to14V Vin=1.8V to14V OCL PGOOD OCH VCCDR LDO SS/INH SYNCH OSC EAREF BOOT Monitor Protection and Ref OSC HGATE Vo PHASE L6730/B PGOOD SINK/OVP/UVLO* + 0.6V - 1.2V + LGATE PWM E/A PGND TMASK MASKING TIME ADJUSTMENT + - GND FB COMP Note: In the L6730B the multifunction pin is: CC/OVP/UVLO. Doc ID 11938 Rev 3 5/52 Summary description L6730 - L6730B 1.2 Application circuit Figure 2. Application circuit VCC = 4.5V to 14V CDEC RFILT VCC GND OCH SYNCH SYNCH SS/INH PGOOD DELAY VCCDR RBOOT COCH ROCH VIN = 1.8V to 14V VCCDR CIN_BULK CSS CPGdelay VCCDR BOOT L6730 HGATE RPG RH_OSC RH_SOU RH_MASK RH_EAREF PGOOD OSC SOU/COU TMASK EAREF COMP PHASE CBOOT RHS CIN_HF HS L Vout CVCCDR LGATE THERMAL PAD PGND ROCL RLS LS RSN COUT CSN OCL FB RL_OSC RL_SOU RL_MASK RL_EAREF CEAREF COCL CF SHORT PIN1 RF CP ROS CS RS RFB NOTE 1: In module application it is recommended to place the short pin on the module where device is mounted. 6/52 Doc ID 11938 Rev 3 L6730 - L6730B Electrical data 2 2.1 Electrical data Maximum rating Table 2. Symbol VCC Absolute maximum ratings Parameter VCC to GND and PGND, OCH, PGOOD Value -0.3 to 18 0 to 6 0 to VBOOT - VPHASE BOOT PHASE -0.3 to 24 -1 to 18 -3 +24 -0.3 to 6 ±1500 ±1000 ±2000 V V V Unit V V V V VBOOT - VPHASE Boot voltage VHGATE - VPHASE VBOOT VPHASE PHASE spike, transient < 50ns (FSW = 500kHz) SS, FB, EAREF, SYNC, OSC, OCL, LGATE, COMP, S/O/U, TMASK, PGOODELAY, VCCDR OCH Pin PGOOD Pin OTHER PINS Maximum withstanding voltage range test condition: CDF-AEC-Q100-002 “human body model” acceptance criteria: “normal performance” 2.2 Thermal data Table 3. Symbol RthJA(1) TSTG TJ TA Thermal data Description Max. thermal resistance junction to ambient Storage temperature range Junction operating temperature range Ambient operating temperature range Value 50 -40 to +150 -40 to +125 -40 to +85 Unit °C/W °C °C °C 1. Package mounted on demonstration board Doc ID 11938 Rev 3 7/52 Pin connections and functions L6730 - L6730B 3 Pin connections and functions Figure 3. Pins connection (top view) PGOOD DELAY SYNCH 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PGOOD VCC VCCDR LGATE PGND BOOT HGATE PHASE OCH OCL SINK/OVP/UVLO TMASK GND FB COMP SS/INH EAREF OSC HTSSOP20 Note: In the L6730B the multifunction pin is: CC/OVP/UVLO. Table 4. Pin n. Pin connection Name Description 1 A capacitor connected between this pin and GND introduces a delay between the internal PGOOD comparator trigger and the external signal rising edge. No delay can be introduced on the falling edge of the PGOOD DELAY PGOOD signal. The delay can be calculated with the following formula: PGDelay = 0.5 ⋅ C ( pF ) [μs] 2 SYNCH Two or more devices can be synchronized by connecting the SYNCH pins together. The device operating with the highest FSW will be the Master device. The Slave devices will operate at 180° phase shift from the Master. The best way to synchronize devices is to set their FSW at the same value. If it is not used, the SYNCH pin can be left floating. 3 With this pin it is possible: SINK/OVP/UVLO To enable-disable the sink mode current capability after SS (L6730); L6730 To enable-disable the constant current OCP after SS (L6730B); To enable-disable the latch mode for the OVP; CC/OVP/UVLO To set the UVLO threshold for the 5 V BUS and 12 V BUS. L6730B The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. 8/52 Doc ID 11938 Rev 3 L6730 - L6730B Table 4. Pin n. Pin connections and functions Pin connection (continued) Name Description The user can select two different values for the leading edge blanking time on the peak overcurrent protection by connecting this pin to VCCDR or GND. The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. All the internal references are referenced to this pin. Connect to the PCB signal ground. This pin is connected to the error amplifier inverting input. Connect it to Vout through the compensation network. This pin is also used to sense the output voltage in order to manage the over voltage conditions and the PGood signal. This pin is connected to the error amplifier output and used to compensate the voltage control loop. The soft-start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces a current of 10mA through the capacitor. This pin is also used to inhibit the device: when the voltage at this pin is lower than 0.5V the device is disabled. It is possible to set two internal references 0.6V / 1.2V or provide an external reference from 0V to 2.5V: VEAREF from 0% to 80% of VCCDR -> external reference VEAREF from 80% to 95% of VCCDR -> VREF=1.2V VEAREF from 95% to 100% of VCCDR -> VREF=0.6V An internal clamp limits the maximum VEAREF at 2.5V (typ.). The device captures the analog value present at this pin at the start-up when VCC meets the UVLO threshold. Connecting an external resistor from this pin to GND, the external frequency can be increased according with the following equation: 4 TMASK 5 GND 6 FB 7 COMP 8 SS/INH 9 EAREF Fsw = 400 KHz + 9.88 ⋅106 ROSC ( KΩ) 10 OSC Connecting a resistor from this pin to VCCDR (5V), the switching frequency can be lowered according with the following equation: Fsw = 400 KHz − 3.01 ⋅107 ROSC ( KΩ) If the pin is left open, the switching frequency is 400 KHz. Normally this pin is at a voltage of 1.2V. In OVP the pin is pulled up to 4.5V (only in latched mode). Don’t connect a capacitor from this pin to GND. Doc ID 11938 Rev 3 9/52 Pin connections and functions Table 4. Pin n. L6730 - L6730B Pin connection (continued) Name Description A resistor connected from this pin to ground sets the valley- current-limit. The valley current is sensed through the low-side MOSFET(s). The internal current generator sources a current of 100μA (IOCL) from this pin to ground through the external resistor (ROCL). The over-current threshold is given by the following equation: 11 OCL I VALLEY = IOCL ⋅ R OCL 2 ⋅ RDSonLS Connecting a capacitor from this pin to GND helps in reducing the noise injected from VCC to the device, but can be a low impedance path for the high-frequency noise related to the GND. Connect a capacitor only to a “clean” GND. A resistor connected from this pin and the high-side MOSFET(s) drain sets the peak-current-limit. The peak current is sensed through the highside MOSFET(s). The internal 100μA current generator (IOCH) sinks a current from the drain through the external resistor (ROCH). The overcurrent threshold is given by the following equation: IPEAK = IOCH ⋅ R OCH RDSonHS 12 OCH 13 PHASE This pin is connected to the source of the high-side MOSFET(s) and provides the return path for the high-side driver. This pin monitors the drop across both the upper and lower MOSFET(s) for the current limit together with OCH and OCL. This pin is connected to the high-side MOSFET(s) gate. The high-side driver is supplied through this pin. Connect a capacitor from this pin to the PHASE pin, and a diode from VCCDR to this pin (cathode versus BOOT). This pin has to be connected closely to the low-side MOSFET(s) source in order to reduce the noise injection into the device. Connect to the PCB power ground plane. This pin is connected to the low-side MOSFET(s) gate. 5V internally regulated voltage. It is used to supply the internal drivers and as a voltage reference. Filter it to GND with at least a 1µF ceramic cap. Supply voltage pin. The operative supply voltage range is from 4.5V to 14V. This pin is an open collector output and it is pulled low if the output voltage is not within the specified thresholds (90%-110%). If not used it may be left floating. Pull up this pin to VCCDR with a 10K resistor to obtain a logical signal. Thermal Pad connects the silicon substrate and makes good thermal contact with the PCB. Connect to the PCB power ground plane. 14 15 HGATE BOOT 16 17 18 PGND LGATE VCCDR 19 VCC 20 PGOOD - Thermal PAD 10/52 Doc ID 11938 Rev 3 L6730 - L6730B Electrical characteristics 4 Electrical characteristics VCC = 12 V, TA = 25°C unless otherwise specified Table 5. Symbol Electrical characteristics Parameter Test condition Min. Typ. Max. Unit VCC supply current VCC stand by current ICC VCC quiescent current OSC = open; SS to GND OSC= open; HG = open, LG = open, PH=open 7 8.5 9 mA 10 Power-ON 5V BUS Turn-ON VCC threshold Turn-OFF VCC threshold 12V BUS Turn-ON VCC threshold Turn-OFF VCC threshold VIN OK Turn-ON VOCH threshold Turn-OFF VOCH threshold VOCH = 1.7V VOCH = 1.7V VOCH = 1.7V VOCH = 1.7V 4.0 3.6 8.3 7.4 1.1 0.9 4.2 3.8 8.6 7.7 1.25 1.05 4.4 4.0 8.9 V 8.0 1.47 1.27 VCCDR regulation VCCDR voltage Soft start and inhibit ISS Oscillator fOSC fOSC,RT ΔVOSC Initial accuracy Total accuracy Ramp amplitude OSC = OPEN RT = 390KΩ to VCCDR RT = 18KΩ to GND 380 -15 2.1 400 420 15 kHz % V SS = 2V Soft start current SS = 0 to 0.5V 20 30 45 7 10 13 µA VCC =5.5V to 14V IDR = 1mA to 100mA 4.5 5 5.5 V Output voltage (1.2V MODE) VFB Output voltage 1.190 1.2 1.208 V Output voltage (0.6 MODE) VFB Error amplifier REAREF EAREF input resistance Vs. GND 70 100 150 kΩ Output voltage 0.597 0.6 0.603 V Doc ID 11938 Rev 3 11/52 Electrical characteristics Table 5. Symbol IFB Ext Ref Clamp VOFFSET GV GBWP SR Gate drivers RHGATE_ON RHGATE_OFF RLGATE_ON RLGATE_OFF Protections IOCH IOCL OCH current source OCL current source VFB rising OVP Over voltage trip (VFB / VEAREF) VEAREF = 0.6V VFB falling VEAREF = 0.6V IOSC Power Good Upper threshold (VFB / VEAREF) Lower threshold (VFB / VEAREF) VPGOOD PGOOD voltage low VFB rising VFB falling IPGOOD = -5mA 108 OSC sourcing current VFB > OVP Trip VOSC = 3V VOCH = 1.7V 90 90 High side source resistance High side sink resistance Low side source resistance Low side sink resistance VBOOT - VPHASE = 5V VBOOT - VPHASE = 5V VCCDR = 5V VCCDR = 5V Error amplifier offset Open loop voltage gain Gain-bandwidth product Slew-rate Vref = 0.6V Guaranteed by design Guaranteed by design COMP = 10pF Guaranteed by design L6730 - L6730B Electrical characteristics (continued) Parameter I.I. bias current VFB = 0V 2.3 -5 100 10 5 +5 Test condition Min. Typ. 0.290 Max. 0.5 Unit μA V mV dB MHz V/μs 1.7 1.12 1.15 0.6 Ω Ω Ω Ω 100 100 120 110 110 μA μA % % mA 117 30 110 112 % % V 88 90 0.5 92 12/52 Doc ID 11938 Rev 3 L6730 - L6730B Electrical characteristics Table 6. Symbol Oscillator fOSC Thermal characterizations (VCC = 12 V) Parameter Test condition Min Typ Max Unit Initial accuracy OSC = OPEN; TJ = 0°C~ 125°C 376 400 424 kHz Output voltage (1.2V MODE) VFB Output voltage TJ = 0°C~ 125°C TJ = -40°C~ 125°C 1.188 1.185 1.2 1.2 1.212 1.212 V V Output voltage (0.6V MODE) VFB Output voltage TJ = 0°C~ 125°C TJ = -40°C~ 125°C 0.596 0.593 0.6 0.6 0.605 0.605 V V Doc ID 11938 Rev 3 13/52 Device description L6730 - L6730B 5 5.1 Device description Oscillator The switching frequency is internally fixed to 400 kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging an internal capacitor (FSW = 400 kHz). This current can be varied using an external resistor (RT) connected between OSC pin and GND or VCCDR in order to change the switching frequency. Since the OSC pin is maintained at fixed voltage (typ. 1.2 V), the frequency is increased (or decreased) proportionally to the current sunk (sourced) from (into) the pin. In particular by connecting RT versus GND the frequency is increased (current is sunk from the pin), according to the following relationship: Fsw = 400 KHz + 9.88 ⋅106 ROSC ( KΩ) (1) Connecting RT to VCCDR reduces the frequency (current is sourced into the pin), according to the following relationship: Fsw = 400 KHz − 3.01⋅107 (2) ROSC ( KΩ) Switching frequency variation vs. RT is shown in Figure 4. Figure 4. Switching frequency variation versus RT 1500 1400 1300 1200 1100 1000 Fsw (KHz) 900 800 700 600 500 400 300 200 100 0 100 200 300 400 500 600 700 800 900 1000 Rosc (KOHM) Rosc connected to GND Rosc connected to Vccdr 14/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description 5.2 Internal LDO An internal LDO supplies the internal circuitry of the device. The input of this stage is the VCC pin and the output (5 V) is the VCCDR pin (see Figure 5). Figure 5. LDO block diagram 4.5V÷14V LDO 5.3 Bypassing the LDO to avoid the voltage drop with low Vcc The LDO can be by passed by providing 5 V voltage directly to VCCDR. In this case Vcc and VCCDR pins must be shorted together as shown in Figure 6. VCCDR pin must be filtered with at least 1 μF capacitor to sustain the internal LDO during the recharge of the bootstrap capacitor. VCCDR also represents a voltage reference for Tmask pin, S/O/U pin (L6730) or CC/O/U pin (L6730B) and PGOOD pin (see Table 4: Pin connection). If Vcc ≈ 5 V the internal LDO works in dropout with an output resistance of about 1 Ω. The maximum LDO output current is about 100 mA, and so the output voltage drop can be 100 mV. The LDO can be bypassed to avoid this. Doc ID 11938 Rev 3 15/52 Device description L6730 - L6730B Figure 6. Bypassing the LDO 5.4 Internal and external references It is possible to set two internal references, 0.6 V and 1.2 V, or provide an external reference from 0 V to 2.5 V. The maximum value of the external reference depends on the VCC: with VCC = 4 V the clamp operates at about 2 V (typ.), while with VCC greater than 5 V the maximum external reference is 2.5 V (typ). ● ● ● VEAREF from 0% to 80% of VCCDR −> External reference VEAREF from 80% to 95% of VCCDR −> VREF = 1.2 V VEAREF from 95% to 100% of VCCDR −> VREF = 0.6 V Providing an external reference from 0V to 450 mV the output voltage will be regulated but some restrictions must be considered: ● ● ● The minimum OVP threshold is set at 300 mV. The under-voltage-protection doesn’t work. The PGOOD signal remains low. To set the resistor divider it must be considered that a 100 kΩ pull-down resistor is integrated into the device (see Figure 7.). Finally it must be taken into account that the voltage at the EAREF pin is captured by the device at the start-up when Vcc is about 4 V. 16/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description 5.5 Error amplifier Figure 7. Error amplifier reference VCCDR 0.6V EAREF 100K 2.5V 1.2V EXT Error Amplifier Ref. 5.6 Soft-start When both VCC and VIN are above their turn-on thresholds (VIN is monitored by the OCH pin) the start-up phase takes place. Otherwise the SS pin is internally shorted to GND. At start-up, a ramp is generated charging the external capacitor CSS with an internal current generator. The initial value for this current is 35 µA and charges the capacitor up to 0.5 V. After that it becomes 10 µA until the final charge value of approximately 4 V (see Figure 5). Figure 8. Device start-up: voltage at the SS pin Vcc Vcc Vin 4.2V 4.2V or 8.6V 1.25V 1.25V Vss Vss Vin t 4V 4V 0.5V 0.5V 0.5V t Doc ID 11938 Rev 3 17/52 Device description L6730 - L6730B The output of the error amplifier is clamped with this voltage (Vss) until it reaches the programmed value. No switching activity is observable if VSS is lower than 0.5 V and both MOSFETs are off. When Vss is between 0.5 V and 1.1 V the low-side MOSFET is turned on because the output of the error amplifier is lower than the valley of the triangular wave and so the duty-cycle is 0%. As VSS reaches 1.1 V (i.e. the oscillator triangular wave inferior limit) even the high-side MOSFET begins to switch and the output voltage starts to increase. The L6730 - L6730B can only source current during the soft-start phase in order to manage the pre-bias start-up applications. This means that when the startup occurs with output voltage greater than 0V (pre-bias startup), even when Vss is between 0.5 V and 1.1 V the low-side MOSFET is kept OFF (see Figure 9 and Figure 10). Figure 9. Start-up without pre-bias LGate VOUT IL VSS Figure 10. Start-up with pre-bias LGate VOUT IL VSS The L6730B can always sink current and so it can be used to supply the DDR memory termination BUS. If overcurrent is detected during the soft-start phase, the device provides constant current-protection. In case there is short soft-start time and/or small inductor value and/or high output capacitors value and thus, in case of high ripple current during the softstart, the converter can start-up in anyway and limit the current (Chapter 5.8: Monitoring and 18/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description protection on page 21) but not enter into HICCUP mode. The soft-start phase ends when VSS reaches 3.5 V. After that the over current-protection triggers the HICCUP mode (L6730). With the L6730B there is the possibility to set the HICCUP mode or the constant current mode after the soft-start acting on the multifunction pin CC/O/U. With the L6730 the low-side MOSFET(s) management after soft-start phase depends on the S/O/U pin state (see related section). If the sink mode is enabled the converter can sink current after softstart (see Figure 11) while, if the sink mode is disabled the converter never sinks current (see Figure 12). Figure 11. Sink mode enabled: Inductor current during and after soft-start (L6730) VOUT VSS VCC IL During normal operation, if any under voltage is detected on one of the two supplies (VCC, VIN), the SS pin is internally shorted to GND by an internal switch so the SS capacitor is rapidly discharged. Two different turn-on UVLO thresholds can be set: 4.2 V for 5 V BUS and 8.6 V for 12 V BUS. Doc ID 11938 Rev 3 19/52 Device description L6730 - L6730B Figure 12. Sink mode disabled: Inductor current during and after soft-start (L6730) Vout Vss Vcc IL 5.7 Driver section The high-side and low-side drivers allow for the use of different types of power MOSFETs (also multiple MOSFETs to reduce the RDSON), maintaining fast switching transitions. The low-side driver is supplied by VCCDR while the high-side driver is supplied by the BOOT pin. A predictive dead time control avoids MOSFETs cross-conduction maintaining very short dead time duration (see Figure 13.). The control monitors the phase node in order to sense the low-side body diode recirculation. If the phase node voltage is less than a certain threshold (–350 mV typ.) during the dead time, it will be reduced in the next PWM cycle. The predictive dead time control does not work when the high-side body diode is conducting because the phase node does not go 20/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description negative. This situation happens when the converter is sinking current for example and, in this case, an adaptive dead time control operates. Figure 13. Dead times 5.8 Monitoring and protection The output voltage is monitored by the FB pin. If it is not within ±10% (typ.) of the programmed value, the Power-Good (PGOOD) output is forced low. The PGOOD signal can be delayed by adding an external capacitor on PGDelay pin (see Table 4: Pin connection and Figure 14.); this can be useful to perform cascade sequencing. The delay can be calculated with the following formula: PGDelay = 0.5 ⋅ C ( pF ) The device provides over voltage protection: when the voltage sensed on FB pin reaches a value 20% (typ) greater than the reference, the low-side driver is turned on. If the OVP notlatched mode has been set the low-side MOSFET is kept on as long as the overvoltage is detected (see Figure 15.).The OVP latched-mode has been set the low-side MOSFET is Doc ID 11938 Rev 3 21/52 Device description L6730 - L6730B turned on until VCC is toggled (see Figure 16). In case of latched-mode OVP the OSC pin is forced high (4.5 V typ) if an over voltage is detected. Figure 14. PGOOD signal FB PGOOD 2ms/Div. Figure 15. OVP not latched LGate FB OSC 22/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description Figure 16. OVP latched LGate OSC FB There is an electrical network between the output terminal and the FB pin and therefore the voltage at this pin is not a perfect replica of the output voltage. If the converter can sink current, in the most of cases the low-side will be turned on before the output voltage exceeds the over-voltage threshold because the error amplifier will throw off balance in advance. Even if the device does not report an overvoltage event, the behavior is the same because the low-side is turned on immediately. Instead, if the sink mode is disabled, the low-side will be turned on only when the overvoltage protection (OVP) operates and not before because the current can not be reversed. In this case, a delay between the output voltage rising and FB voltage rising can appear and the OVP can turn on late. Figure 17 and Figure 18 show an overvoltage event in the cases of the sink being enabled or disabled. The output voltage rises with a slope of 100 mVµs, emulating the breaking of the high-side MOSFET as an overvoltage occurs. Doc ID 11938 Rev 3 23/52 Device description L6730 - L6730B Figure 17. OVP with sink enabled: the low-side MOSFET is turned-on in advance VOUT 109% VFB LGate Figure 18. OVP with sink disabled: delay on the OVP operation 126% VOUT VFB LGate The L6730B can always sink current and so the OVP will operate always in advance. The device realizes the over-current-protection (OCP) sensing the current both on the high-side MOSFET(s) and the low-side MOSFET(s) and so 2 current limit thresholds can be set (see OCH pin and OCL pin in Table 4: Pin connection): ● ● Peak current limit Valley current limit The peak current protection is active when the high-side MOSFET(s) is turned on, after an adjustable masking time (see Chapter 5.10 on page 27). The valley-current-protection is enabled when the low-side MOSFET(s) is turned on after a fix masking time of about 400 ns. If, when the soft-start phase is completed, an over current event occurs during the on time (peak-current-protection) or during the off time (valley-current-protection) the device 24/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description enters in HICCUP mode (L6730): the high-side and low-side MOSFET(s) are turned off, the soft-start capacitor is discharged with a constant current of 10 µA and when the voltage at the SS pin reaches 0.5 V the soft-start phase restarts. During the soft-start phase the OCP provides a constant-current-protection. If during the TON the OCH comparator triggers an over current the high-side MOSFET(s) is immediately turned-off (after the masking time and the internal delay) and returned-on at the next pwm cycle. The limit of this protection is that the Ton can’t be less than masking time plus propagation delay (see Chapter 5.9: Adjustable masking time on page 27) because during the masking time the peak-current-protection is disabled. In case of very hard short circuit, even with this short TON, the current could escalate. The valley-current-protection is very helpful in this case to limit the current. If during the off-time the OCL comparator triggers an over current, the high-side MOSFET(s) is not turned-on until the current is over the valley-current-limit. This implies that, if it is necessary, some pulses of the high-side MOSFET(s) will be skipped, guaranteeing a maximum current due to the following formula: I MAX = IVALLEY + Vin − Vout ⋅ TON , MIN (4) L In constant current protection a current control loop limits the value of the error amplifier’s output (comp), in order to avoid its saturation and thus recover faster when the output returns in regulation. Figure 19 shows the behaviour of the device during an over current condition that persists also in the soft-start phase. Figure 19. Constant current and hiccup mode during an OCP (L6730) VSS VCOMP IL Using the L6730B there is the possibility to set the constant-current-protection also after the soft-start. The following figures show the behaviour of the L6730B during an overcurrent event. Figure 20 shows the intervention of the peak OCP: the high-side MOSFET(s) is turned-off when the current exceeds the OCP threshold. In this way the duty-cycle is reduced, the VOUT is reduced and so the maximum current can be fixed even if the output current is escalating. Figure 21 shows the limit of this protection: the on-time can be reduced only to the masking time and, if the output current continues to increase, the maximum current can increase too. Notice how the Vout remains constant even if the output current increases because the on-time cannot be reduced anymore. Doc ID 11938 Rev 3 25/52 Device description L6730 - L6730B Figure 20. Peak overcurrent-protection in constant-current-protection (L6730B) VOUT Peak th IL IOUT TON Figure 21. Peak OCP in case of heavy overcurrent (L6730B) VOUT IL IOUT If the current is higher than the valley OCP threshold during the off-time, the high-side MOSFET(s) will not be turned ON. In this way the maximum current can be limited (Figure 22). During the constant-current-protection if the Vout becomes lower than 80% of the programmed value an UV (under-voltage) is detected and the device enters in HICCUP mode. The under-voltage-lock-out (UVLO) is adjustable by the multifunction pin (see Chapter 5.10 on page 27). It’s possible to set two different thresholds: ● ● 4.2 V for 5 V bus 8.6 V for 12 V bus 26/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description Working with a 12 V BUS, setting the UVLO at 8.6 V can be very helpful to limit the input current in case of BUS fall. Figure 22. Valley OCP (L6730B) VOUT Valley th IL TOFF TOFF 5.9 Adjustable masking time By connecting the masking time pin to VCCDR or GND it is possible to select two different values for the peak current protection leading edge blanking time. This is useful to avoid any false OCP trigger due to spikes and oscillations generated at the turn-on of the high-side MOSFET(s). The amount of this noise depends very much on the layout, MOSFETs, freewheeling diode, switched current, and input voltage. When good layout and medium current are used, the minimum masking time can be chosen, while in case of higher noise, it is better to select the maximum masking time. By connecting the tMASK pin to VCCDR the masking time is about 400 ns, while connecting it to GND results in about 260 ns masking time. 5.10 Multifunction pin (S/O/U L6730) (CC/O/U L6730B) With this pin it is possible: ● ● ● To enable disable the sink mode current capability (L6730) or the constant current protection (L6730B) at the end of the soft-start To enable or disable the latch-mode for the OVP To set the UVLO threshold for 5 V BUS and 12 V busses Doc ID 11938 Rev 3 27/52 Device description L6730 - L6730B Table 7 shows how to set the different options through an external resistor divider: Figure 23. External resistor VCCDR R1 L6730/B S/O/U CC/O/U R2 Table 7. R1 N.C 11KΩ 6.2KΩ 4.3KΩ 2.7KΩ 1.8KΩ 1.2KΩ 0Ω S/O/U and CC/O/U pin R2 0Ω 2.7KΩ 2.7KΩ 2.7KΩ 2.7KΩ 2.7KΩ 2.7KΩ N.C VSOU/VCCDR 0 0.2 0.3 0.4 0.5 0.6 0.7 1 UVLO 5V BUS 5V BUS 5V BUS 5V BUS 12V BUS 12V BUS 12V BUS 12V BUS OVP Not latched Not latched Latched Latched Not latched Not latched Latched Latched SINK CC Not Yes Not Yes Not Yes Not Yes 5.11 Synchronization The presence of many converters on the same board can generate beating frequency noise. To avoid this it is important to make them operate at the same switching frequency. Moreover, a phase shift between different modules helps to minimize the RMS current on the common input capacitors. Figure 24 shows the results of two modules in synchronization. Two or more devices can be synchronized simply connecting together the SYNCH pins. The device with the higher switching frequency will be the Master while the other one will be the slave. The slave controller will increase its switching frequency reducing the ramp amplitude proportionally and then the modulator gain will be increased. To avoid a huge variation of the modulator gain, the best way to synchronize two or more devices is to make them work at the same switching frequency and, in any case, the switching frequencies can differ for a maximum of 50% of the lowest one. If, during synchronization between two (or more) L6730, it’s important to know in advance which the master is, it’s timely to set its switching frequency at least 15% higher than the slave. Using an external clock signal (fEXT) to synchronize one or more devices that are working at a different switching frequency (fSW) it is recommended to follow the below formula: f SW ≤ f EXT ≤ 1,3 ⋅ f SW 28/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description The phase shift between master and slaves is approximately done 180°. Figure 24. Synchronization PWM SIGNALS INDUCTOR CURRENTS 5.12 Thermal shutdown When the junction temperature reaches 150°C ±10°C, the device enters in thermal shutdown. Both MOSFETs are turned OFF and the soft-start capacitor is rapidly discharged with an internal switch. The device does not restart until the junction temperature goes down to 120°C and, in any case, until the voltage at the soft-start pin reaches 500 mV. 5.13 Minimum ON-time TON(MIN) The device can manage minimum ON times lower than 100 ns. This feature comes from the control topology as well as from the particular L6730/B overcurrent protection system. In a voltage mode controller, the current does not have to be sensed to perform regulation and, in the case of L6730/B, it does not have to be sensed for the overcurrent protection either because valley current protection can operate during the OFF time. The first advantage related of this feature is the achievement of extremely low conversion ratios. Figure 25 shows a conversion from 14 V to 0.5 V at 820 kHz with a tON of about 50 ns. The ON time is limited by the MOSFET turn-on and turn-off times. Doc ID 11938 Rev 3 29/52 Device description L6730 - L6730B Figure 25. 14 V -> 0.5 V@820 kHz, 5 A 50ns 5.14 Bootstrap anti-discharging system This built-in anti-discharging system keeps the voltage going across the bootstrap capacitor from going below 3.3 V. An internal comparator senses the voltage across the external bootstrap capacitor and helps to keep it charged, eventually turning on the low-side MOSFET for approximately 200 ns. If the bootstrap capacitor is not charged up enough, the high-side MOSFET cannot be effectively turned on and it will present a higher RDS(on). In some cases, the OCP can be also triggered. There are up to two conditions during which the bootstrap capacitor can be discharged: ● ● fan power supply failure, and no sink at zero current operation. 30/52 Doc ID 11938 Rev 3 L6730 - L6730B Device description 5.14.1 Fan power supply failure In many applications the fan is driven by a DC motor that uses a DC/DC converter. Often only the speed of the motor is controlled by varying the voltage applied to the input terminal and there is no control on the torque because the current is not directly controlled. The current has to be limited in case of overload or short-circuit, but without stopping the motor. With the L6730B, the current can be limited without shutting down the system because constant current protection is provided. In order to vary the motor speed, the output voltage of the converter must be varied. Both L6730 and L6730B have a dedicated EAREF pin (see Figure 4) which provides an external reference to the non-inverting input of the erroramplifier. In these applications the duty cycle depends on the motor’s speed and sometimes a 100% duty cycle setting has to be used to attain the maximum speed. In these conditions, the bootstrap capacitor can not be recharged and the system cannot work properly. Some PWM controllers limit the maximum duty cycle to 80 or 90% in order to keep the bootstrap capacitor charged, but this makes performance during the load transient worse. The “bootstrap anti-discharging system” allows the L6730x to work at 100% without any problem. Figure 26.: 100% duty cycle operation on page 31 shows the following picture illustrates the device behavior when the input voltage is 5 V and a 100% duty cycle is set by an external reference. Figure 26. 100% duty cycle operation TOFF≈200ns Vout=5V Vin=5V LGate ≈ Fsw?6.3KHz 5.14.2 No-sink at zero current operation The L6730 can work in no-sink mode. If output current is zero the converter skip some pulses and works with a lower switching frequency. Between two pulses can pass a relatively long time (say 200-300 µs) during which there’s no switching activity and the current into the inductor is zero. In this condition the phase node is at the output voltage and in some cases this is not enough to keep the bootstrap cap charged. For example, if Vout is 3.3 V the voltage across the bootstrap cap is only 1.7 V. The high-side MOSFET cannot be Doc ID 11938 Rev 3 31/52 Device description L6730 - L6730B effectively turned-on and the regulation can be lost. Thanks to the “bootstrap antidischarging system” the bootstrap cap is always kept charged. The following picture shows the behaviour of the device in the following conditions: 12 V -> 3.3 V@0 A. It can be observed that between two pulses trains the low-side is turned-on in order to keep the bootstrap cap charged. Figure 27. 12 V -> 3.3 V@0 A in no-sink IL VBOOT Minimum Bootstrap Voltage Pulse train VPHASE 32/52 Doc ID 11938 Rev 3 L6730 - L6730B Application details 6 6.1 Application details Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to maintain the ripple current (ΔIL) between 20% and 30% of the maximum output current. The inductance value can be calculated with the following relationship: L≅ Vin − Vout Vout ⋅ (6) Fsw ⋅ ΔI L Vin Where FSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 28 shows the ripple current vs. the output voltage for different values of the inductor, with VIN = 5 V and VIN = 12 V at a switching frequency of 400 kHz. Increasing the value of the inductance reduces the current ripple but, at the same time, increases the converter response time to a load transient. If the compensation network is well designed, during a load transient the device is able to set the duty cycle to 100% or to 0%. When one of these conditions is reached, the response time is limited by the time required to change the inductor current. During this time the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitor size. Figure 28. Inductor current ripple INDUCT O R CURRE NT RIP P L 8 7 6 5 4 3 2 1 0 0 1 2 3 4 O UT P UT V O L T AG E (V ) Vin=12V, L=1uH Vin=12V, L=2uH Vin=5V, L=500nH Vin=5V, L=1.5uH Doc ID 11938 Rev 3 33/52 Application details L6730 - L6730B 6.2 Output capacitors The output capacitors are basic components for the fast transient response of the power supply. They depend on the output voltage ripple requirements, as well as any output voltage deviation requirement during a load transient. During a load transient, the output capacitors supply the current to the load or absorb the current stored into the inductor until the converter reacts. In fact, even if the controller recognizes immediately the load transient and sets the duty cycle at 100% or 0%, the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): ΔVout ESR = ΔIout ⋅ ESR (7) Moreover, there is an additional drop due to the effective capacitor discharge or charge that is given by the following formulas: ΔVoutCOUT = ΔIout 2 ⋅ L (8) 2 ⋅ Cout ⋅ (Vin, min⋅ D max − Vout ) ΔIout 2 ⋅ L 2 ⋅ Cout ⋅ Vout ΔVoutCOUT = (9) Formula (8) is valid in case of positive load transient while the formula (9) is valid in case of negative load transient. DMAX is the maximum duty cycle value that in the L6730/B is 100%. For a given inductor value, minimum input voltage, output voltage and maximum load transient, a maximum ESR, and a minimum COUT value can be set. The ESR and COUT values also affect the static output voltage ripple. In the worst case the output voltage ripple can be calculated with the following formula: ΔVout = ΔI L ⋅ ( ESR + 1 ) 8 ⋅ Cout ⋅ Fsw (10) Usually the voltage drop due to the ESR is the biggest one while the drop due to the capacitor discharge is almost negligible. 6.3 Input capacitors The input capacitors have to sustain the RMS current flowing through them, that is: Irms = Iout ⋅ D ⋅ (1 − D) (11) Where D is the duty cycle. The equation reaches its maximum value, IOUT/2 with D = 0.5. The losses in worst case are: P = ESR ⋅ (0.5 ⋅ Iout ) 2 (12) 34/52 Doc ID 11938 Rev 3 L6730 - L6730B Application details 6.4 Compensation network The loop is based on a voltage mode control (Figure 29). The output voltage is regulated to the internal/external reference voltage and scaled by the external resistor divider. The error amplifier output VCOMP is then compared with the oscillator triangular wave to provide a pulse-width modulated (PWM) with an amplitude of VIN at the PHASE node. This waveform is filtered by the output filter. The modulator transfer function is the small signal transfer function of VOUT/VCOMP. This function has a double pole at frequency FLC depending on the L-Cout resonance and a zero at FESR depending on the output capacitor’s ESR. The DC Gain of the modulator is simply the input voltage VIN divided by the peak-to-peak oscillator voltage: VOSC. Figure 29. Compensation network ZFB ZIN The compensation network consists in the internal error amplifier, the impedance networks ZIN (R3, R4 and C20) and ZFB (R5, C18 and C19). The compensation network has to provide a closed loop transfer function with the highest 0dB crossing frequency to have fastest transient response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the load regulation error. A stable control loop has a gain crossing the Doc ID 11938 Rev 3 35/52 Application details L6730 - L6730B 0 dB axis with -20 dB/decade slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation networks, the following suggestions may be used: ● Modulator singularity frequencies: ω LC = ● 1 L ⋅ Cout (13) ω ESR = 1 ESR ⋅ Cout (14) Compensation network singularity frequencies: ω P1 = 1 (15) ⎛ C18 ⋅ C19 ⎞ R5 ⋅ ⎜ ⎜C +C ⎟ ⎟ 19 ⎠ ⎝ 18 1 R5 ⋅ C19 (17) ωP 2 = 1 R4 ⋅ C20 (16) ωZ 1 = ωZ 2 = 1 C20 ⋅ (R3 + R4 ) (18) ● Compensation network design: – Put the gain R5/R3 in order to obtain the desired converter bandwidth R5 Vin ⋅ ⋅ϖ LC R3 ΔVosc ϖC = – – – – – (18) Place ωZ1 before the output filter resonance ωLC; Place ωZ2 at the output filter resonance ωLC; Place ωP1 at the output capacitor ESR zero ωESR; Place ωP2 at one half of the switching frequency; Check the loop gain considering the error amplifier open loop gain. Figure 30. Asymptotic bode plot of converter's open loop gain 36/52 Doc ID 11938 Rev 3 L6730 - L6730B Application details 6.5 Two quadrant or one quadrant operation mode (L6730) After the soft-start phase the L6730 can work in source only (one quadrant operation mode) or in sink/source (two quadrant operation mode), depending on the setting of the multifunction pin (see Chapter 5.10 on page 27). The choice of one or two quadrant operation mode is related to the application. One quadrant operation mode permits to have a higher efficiency at light load, because the converter works in discontinuous mode (see Figure 31). Nevertheless in some cases, in order to maintain a constant switching frequency, it’s preferable to work in two quadrants, even at light load. In this way the reduction of the switching frequency due to the pulse skipping is avoided. To parallel two or more modules is requested the one quadrant operation in order not to have current sinking between different converters. Finally the two quadrant operation allows faster recovers after negative load transient. For example, let’s consider that the load current falls down from IOUT to 0A with a slew rate sufficiently greater than L/VOUT (where L is the inductor value). Even considering that the converter reacts instantaneously setting to 0% the duty-cycle, the energy ½*L*IOUT2 stored in the inductor will be transferred to the output capacitors, increasing the output voltage. If the converter can sink current this overvoltage can be faster eliminated. Figure 31. Efficiency in discontinuous-current-mode and continuous-current-mode E FFIC IENCY: D C M vs. C CM 0.7 0.6 EFF. (% 0.5 0.4 0.3 0.2 0.1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 OUTP UT CURRENT (A) E FFICIENCY DCM E FFICIENCY CCM Doc ID 11938 Rev 3 37/52 L6730 demonstration board L6730 - L6730B 7 7.1 L6730 demonstration board Description L6730 demonstration board realizes in a four layer PCB a step-down DC/DC converter and shows the operation of the device in a general purpose application. The input voltage can range from 4.5 V to 14 V and the output voltage is at 3.3 V. The module can deliver an output current in excess of 30 A. The switching frequency is set at 400 kHz (controller freerunning FSW) but it can be increased up to 1 MHz. A 7 positions dip-switch allows to select the UVLO threshold (5 V or 12 V bus), the OVP intervention mode and the sink-mode current capability. Figure 32. Demonstration board picture Top Side Bottom Side 38/52 Doc ID 11938 Rev 3 L6730 - L6730B L6730 demonstration board 7.2 PCB layout Figure 34. Power ground layer Figure 33. Top layer Figure 35. Signal ground layer Figure 36. Bottom layer Doc ID 11938 Rev 3 39/52 L6730 demonstration board L6730 - L6730B Figure 37. Demonstration board schematic Table 8. Demonstration board part list Value 820Ω 0Ω N.C. 10Ω 1% 100mW 11K 1% 100mW 6K2 1% 100mW 4K3 1% 100mW 2K7 1% 100mW 1K8 1% 100mW 1K2 1% 100mW 2K7 1% 100mW 1K 2K7 1% 100mW Reference R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 Manufacturer Neohm Neohm Package SMD 0603 SMD 0603 Supplier IFARCAD IFARCAD Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm Neohm SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD 40/52 Doc ID 11938 Rev 3 L6730 - L6730B Table 8. Demonstration board part list (continued) Value 1K 1% 100mW 1K 1% 100mW 4K7 1% 100mW N.C. 2.2Ω 2.2Ω 10K 1% 100mW N.C. N.C. 0Ω 220nF 100nF 1nF. 100uF 20V 4.7uF 20V 10nF N.C. 47nF 1.5nF 4.7nF 330uF 6.3V N.C. 1.8uH 1N4148 STS1L30M STS12NH3LL STSJ100NH3LL L6730 L6730 demonstration board Reference R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 C1 C3-C7-C9-C15-C21 C2 C4-C6 C8 C10 C11 C12 C13 C14 C18-C19 C20 L1 D1 D2 Q1-Q2 Q4-Q5 U1 SWITCH Manufacturer Neohm Neohm Neohm Package SMD 0603 SMD 0603 SMD 0603 Supplier IFARCAD IFARCAD IFARCAD Neohm Neohm Neohm SMD 0603 SMD 0603 SMD 0603 IFARCAD IFARCAD IFARCAD Neohm Kemet Kemet Kemet OSCON 20SA100M AVX Kemet SMD 0603 SMD 0603 SMD 0603 SMD 0603 RADIAL 10X10.5 SMA6032 SMD 0603 IFARCAD IFARCAD IFARCAD IFARCAD SANYO IFARCAD IFARCAD Kemet Kemet Kemet POSCAP 6TPB330M SMD 0603 SMD 0603 SMD 0603 SMD IFARCAD IFARCAD IFARCAD SANYO Panasonic ST ST ST ST ST SMD SOT23 DO216AA SO8 SO8 HTSSOP20 ST IFARCAD ST ST ST ST ST DIP SWITCH 7 POS. Doc ID 11938 Rev 3 41/52 L6730 demonstration board L6730 - L6730B Table 9. Other inductor manufacturer Series 744318180 CDEP134-2R7MC-H HPI_13 T640 SPM12550T-1R0M220 FDA1254 HCF1305-1R0 Inductor value (µH) 1.8 2.7 1.4 1 2.2 1.15 1.3 Saturation current (A) 20 15 22 22 14 22 27 Manufacturer WURTH ELEKTRONIC SUMIDA EPCOS TDK TOKO COILTRONICS HC5-1R0 Table 10. Other capacitor manufacturer Series C4532X5R1E156M TDK C3225X5R0J107M 100 100 100 6.3 25 6.3 Capacitor value (µF) 15 Rated voltage (V) 25 Manufacturer NIPPON CHEMI-CON PANASONIC 25PS100MJ12 ECJ4YB0J107M 42/52 Doc ID 11938 Rev 3 L6730 - L6730B I/O Description 8 I/O Description Figure 38. Demonstration board Table 11. I/O functions Function The input voltage can range from 1.8V to 14V. If the input voltage is between 4.5V and 14V it can supply also the device (through the VCC pin) and in this case the pin 1 and 2 of the jumper G1 must be connected together. The output voltage is fixed at 3.3V but it can be changed by replacing the resistor R14 of the output resistor divider: Symbol Input (Vin-Gin) Vo = VREF ⋅ (1 + Output (VOUT-GOUT) R16 ) R14 The over-current-protection limit is set at 15A but it can be changed by replacing the resistors R1 and R12 (see OCL and OCH pin in Table 4: Pin connection). Using the input voltage to supply the controller no power is required at this input. However the controller can be supplied separately from the power stage through the VCC input (4.5-14V) and, in this case, jumper G1 must be left open. An internal LDO provides the power into the device. The input of this stage is the VCC pin and the output (5V) is the VCCDR pin. The LDO can be bypassed, providing directly a 5V voltage from VCCDR and Gndcc. In this case the pins 1 and 3 of the jumper G1 must be shorted. This pin can be used as an input or as a test point. If all the jumper G2 pins are shorted, TP1 can be used as a test point of the voltage at the EAREF pin. If the pins 2 and 3 of G2 are connected together, TP1 can be used as an input to provide an external reference for the internal error amplifier (see section 4.3. Internal and external references). VCC-GNDCC VCCDR TP1 Doc ID 11938 Rev 3 43/52 I/O Description Table 11. I/O functions (continued) Function L6730 - L6730B Symbol TP2 TP3 SYNCH PWRGD DIP SWITCH This test point is connected to the Tmask pin (see Table 4: Pin connection). This test point is connected to the S/O/U pin (see Chapter 5.10 on page 27). This pin is connected to the synch pin of the controller (see Chapter 5.11 on page 28). This pin is connected to the PGOOD pin of the controller. Different positions of the dip switch correspond to different settings of the multifunction pin (S/O/U) (CC/O/U). Table 12. UVLO 5V 5V 5V 5V 12V 12V 12V 12V Dip switch OVP Not latched Not latched Latched Latched Not latched Not latched Latched Latched SINK CC Not Yes Not Yes Not Yes Not Yes Vsou/VCCDR 0 0.2 0.3 0.4 0.5 0.6 0.7 1 DIP switch S7 S1-S7 S2-S7 S3-S7 S4-S7 S5-S7 S6-S7 S1 State A B C D E F G H 44/52 Doc ID 11938 Rev 3 L6730 - L6730B Efficiency 9 Efficiency The following figures show the demo board efficiency versus load current for different values of input voltage and switching frequency: Figure 39. Demonstration board efficiency 400 kHz Fsw=400KHz 95.00% EFFICIENCY 90.00% 85.00% 80.00% 75.00% 1 3 5 7 Iout (A) 9 11 VO = 3.3V VIN = 5V VIN = 12V 13 15 Figure 40. Demonstration board efficiency 645 kHz Fsw=645KHz 95.00% EFFICIENCY 90.00% 85.00% 80.00% 75.00% 70.00% 1 3 5 7 Iout (A) 9 11 VO = 3.3V VIN = 5V VIN = 12V 13 15 Doc ID 11938 Rev 3 45/52 Efficiency Figure 41. Demonstration board efficiency 1 MHz L6730 - L6730B Fsw=1MHz VO = 3.3V 95.00% 90.00% EFFICIENCY 85.00% 80.00% 75.00% 70.00% 65.00% 60.00% 1 3 5 7 Iout (A) 9 11 13 15 VIN = 5V VIN = 12V Figure 42. Efficiency with 2xSTS12NH3LL+2XSTSJ100NH3LL 12V-->3.3V 0.96 0.95 0.94 0.93 0.92 0.91 0.9 0.89 0.88 0.87 3 5 7 9 11 13 15 17 19 OUTPUT CURRENT (A) EFFICIENCY (%) 400KHz 700KHz 1MHz 46/52 Doc ID 11938 Rev 3 L6730 - L6730B POL demonstration board 10 10.1 POL demonstration board Description A compact demonstration board has been designed to manage currents in the range of 1015 A. Figure 39 shows the schematic and Table 10 the part list. Multi-layer-ceramiccapacitors (MLCCs) have been used on the input and the output in order to reduce the overall size. Figure 43. Pol demonstration board schematic Table 13. Pol demonstration board part list Value 1K8Ω 10KΩ N.C. 10Ω 11K 1% 100mW 2K7 1% 100mW N.C. 0Ω 3K 1% 100mW 4K7 1% 100mW Reference R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 Manufacturer Neohm Neohm Package SMD 0603 SMD 0603 Supplier IFARCAD IFARCAD Neohm Neohm Neohm Neohm Neohm Neohm Neohm SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD Doc ID 11938 Rev 3 47/52 POL demonstration board Table 13. Pol demonstration board part list (continued) Value 15Ω 1% 100mW 4K7 1% 100mW 1K 1% 100mW 2.2Ω 2.2Ω 220nF 100nF 1nF N.C. 68nF 220pF 4.7uF 20V 6.8nF 15uF 100uF 1.8uH STS1L30M STS12NH3LL STSJ100NH3LL L6730 L6730 - L6730B Reference R11 R12 R13 R14 R15 C1-C7 C6- C19-C20-C9 C2 C11 C12 C13 C8 C14 C3-C4-C5 C15-C16-C17-C18 L1 D1 Q1 Q2 U1 Manufacturer Neohm Neohm Neohm Neohm Neohm Kemet Kemet Kemet Package SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 SMD 0603 Supplier IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD Kemet Kemet AVX Kemet TDK MLC C4532X5R1E156M PANASONIC MLC P/N ECJ4YBOJ107M Panasonic ST ST ST ST SMD 0603 SMD0603 SMA6032 SMD 0603 SMD1812 SMD 1210 SMD DO216AA POWER SO8 POWER SO8 HTSSOP20 IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD IFARCAD ST ST ST ST ST Figure 44. Pol demonstration board efficiency 12V-->3.3V@400KHz 0.94 0.92 EFFICIENCY 0.9 0.88 0.86 0.84 0.82 1 3 5 7 9 11 OUTPUT CURRENT (A) 48/52 Doc ID 11938 Rev 3 L6730 - L6730B Package mechanical data 11 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 14. Dim. Min. A A1 A2 b c D(1) D1(3) HTSSOP20 mechanical data mm Typ. Max. 1.200 0.150 0.800 0.190 0.090 6.400 2.200 6.200 4.300 1.500 0.650 0.450 0.600 1.000 0° min., 8° max. 0.100 0.004 0.750 0.018 6.400 4.400 6.600 4.500 6.500 1.000 1.050 0.300 0.200 6.600 0.031 0.007 0.003 0.252 0.087 0.244 0.170 0.059 0.025 0.024 0.039 0.030 0.252 0.173 0.260 0.177 0.256 0.039 Min. inch Typ. Max. 0.047 0.006 0.041 0.012 0.008 0.260 E E1(2) E2(3) e L L1 k aaa 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension “E1” does not include interlead flash or protrusions. Intelead flash or protrusions shall not exceed 0.25mm per side. 3. The size of exposed pad is variable depending of leadframe design pad size. End user should verify “D1” and “E2” dimensions for each device application. Doc ID 11938 Rev 3 49/52 Package mechanical data Figure 45. Package dimensions L6730 - L6730B 50/52 Doc ID 11938 Rev 3 L6730 - L6730B Revision history 12 Revision history Table 15. Date 21-Dec-2005 29-May-2006 07-Dec-2009 Document revision history Revision 1 2 3 Initial release New template, thermal data updated Updated Table 4 on page 8 and added Section 1.2 on page 6 Changes Doc ID 11938 Rev 3 51/52 L6730 - L6730B Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 52/52 Doc ID 11938 Rev 3