L6751B
Digitally controlled dual PWM for Intel VR12 and AMD SVI
Datasheet − production data
Features
■
VR12 compliant with 25 MHz SVID bus rev1.5
– SerialVID with programmable IMAX,
TMAX, VBOOT, ADDRESS
■
AMD SVI compliant
■
Second generation LTB Technology®
■
Flexible driver/DrMOS support
■
JMode support
■
Fully configurable through PMBus™
■
Dual controller:
– up to 6 phases for CORE and memory
– 1 phase for graphics (GFX), system agent
(VSA) or Northbridge (VDDNB)
■
Single NTC design for TM, LL and Imon
thermal compensation (for each section)
■
VFDE and GDC - gate drive control for
efficiency optimization
■
DPM - dynamic phase management
■
Dual remote sense; 0.5% Vout accuracy
■
Full-differential current sense across DCR
■
AVP - adaptive voltage positioning
■
Dual independent adjustable oscillator
■
Dual current monitor
■
Pre-biased output management
■
Average and per-phase OC protection
■
OV, UV and FB disconnection protection
■
Dual VR_RDY
■
VFQFPN68 8x8 mm package
QFN68 8x8 mm
Description
The device is available in VFQFPN68 8x8 mm
package.
Order code
Device summary
Package
L6751B
Packaging
Tray
VFQFPN68 8x8 mm
■
High-current VRM / VRD for desktop / server /
workstation Intel / AMD CPUs
■
DDR3 memory supply
This is information on a product in full production.
The device features up to 6-phase programmable
operation for the multi-phase section and a singlephase with independent control loops. When
configured for memory supply, single-phase
(VTT) reference is always tracking multi-phases
(VDDQ) scaled by a factor of 2. The L6751B
supports power state transitions featuring VFDE,
programmable DPM and GDC maintaining the
best efficiency over all loading conditions without
compromising transient response. The device
assures fast and independent protection against
load overcurrent, under/overvoltage and feedback
disconnections.
Table 1.
Applications
December 2012
The L6751B is a universal digitally controlled dual
PWM DC-DC designed to power Intel’s VR12 and
AMD SVI processors and memories: all required
parameters are programmable through dedicated
pinstrapping and PMBus interface.
L6751BTR
Doc ID 024028 Rev 1
Tape and reel
1/58
www.st.com
58
Contents
L6751B
Contents
1
2
3
4
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 6
1.1
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description and connection diagram . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device configuration and pinstrapping tables . . . . . . . . . . . . . . . . . . . 20
4.1
JMode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2
Programming HiZ level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5
Device description and operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6
Output voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1
Multi-phase section - phase # programming . . . . . . . . . . . . . . . . . . . . . . 29
6.2
Multi-phase section - current reading and current sharing loop . . . . . . . . 29
6.3
Multi-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.4
Single-phase section - disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.5
Single-phase section - current reading . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.6
Single-phase section - defining load-line . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.7
Dynamic VID transition support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.7.1
6.8
7
DVID optimization: REF/SREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Output voltage monitoring and protection . . . . . . . . . . . . . . . . . . . . . . 34
7.1
Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2
Overcurrent and current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2.1
2/58
LSLESS startup and pre-bias output . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Multi-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Doc ID 024028 Rev 1
L6751B
8
9
Contents
7.2.2
Overcurrent and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.3
Single-phase section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Single NTC thermal monitor and compensation . . . . . . . . . . . . . . . . . 39
8.1
Thermal monitor and VR_HOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.2
Thermal compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.3
TM/STM and TCOMP/STCOMP design . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1
Dynamic phase management (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.2
Variable frequency diode emulation (VFDE) . . . . . . . . . . . . . . . . . . . . . . 42
9.2.1
9.3
VFDE and DrMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Gate drive control (GDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10
Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11
System control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
12
11.1
Compensation network guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
11.2
LTB Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PMBus support (preliminary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
12.1
Enabling the device through PMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.2
Controlling Vout through PMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12.3
Input voltage monitoring (READ_VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.4
Duty cycle monitoring (READ_DUTY) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
12.5
Output voltage monitoring (READ_VOUT) . . . . . . . . . . . . . . . . . . . . . . . . 54
12.6
Output current monitoring (READ_IOUT) . . . . . . . . . . . . . . . . . . . . . . . . 54
12.7
Temperature monitoring (READ_TEMPERATURE) . . . . . . . . . . . . . . . . . 54
12.8
Overvoltage threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Doc ID 024028 Rev 1
3/58
List of tables
L6751B
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
4/58
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Phase number programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
IMAX, SIMAX pinstrapping (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
ADDR pinstrapping (Note 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
BOOT / TMAX pinstrapping (Note 1, 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
DPM pinstrapping (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
GDC threshold definition (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
L6751B protection at a glance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Multi-phase section OC scaling and power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Efficiency optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Supported commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
OV threshold setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
L6751B VFQFPN68 8x8 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Doc ID 024028 Rev 1
L6751B
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Typical 6-phase application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
L6751B pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
JMode: voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Voltage positioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SLESS startup: enabled (left) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
LSLESS startup: disabled (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DVID optimization circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Thermal monitor connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Output current vs. switching frequency in PSK mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Efficiency performance with and without enhancements (DPM, GDC). . . . . . . . . . . . . . . . 44
ROSC vs. FSW per phase (ROSC to GND - left; ROSC to 3.3 V - right) . . . . . . . . . . . . . . . . 45
Equivalent control loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Control loop bode diagram and fine tuning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Device initialization: PMBus controlling Vout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
L6751B VFQFPN68 8x8 mm drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Doc ID 024028 Rev 1
5/58
Typical application circuit and block diagram
L6751B
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1.
Typical 6-phase application circuit
+12V
+5V
+12V
CDEC
EN
EN
RSOSC
SOSC
OSC
ROSC
PMBus(tm)
+12V
VCC
GND x2 VCC5 GDC
(+PAD)
IMAX / SIMAX
BOOT / TMAX
ADDR
DPM1-3
DPM4-6
TCOMP
STCOMP
BOOT
CHF
EN
L6747
VDRV
HS1
L1
PHASE
LGATE
PWM
SMCLK
SMAL#
SMDATA
VIN
UGATE
LS1
R
C
GND
RG
+12V
VR_RDY
SVR_RDY
VR_HOT
PHASE
VCC5
NTC (NTHS0805N02N6801)
(Close to the hot spot)
CDEC
VCC
BOOT
VR_HOT
ENDRV
PWM1
CS1P
CS1N
TM
VCC5
VRRDY
SVRRDY
CHF
EN
L6747
PHASE1
UGATE
LGATE
PWM
HS2
L2
PHASE
LS2
R
C
GND
STM
PWM2
CS2P
CS2N
NTC (NTHS0805N02N6801)
(Close to the hot spot)
RG
+12V
PWM3
CS3P
CS3N
SIMON
RSIMON
CDEC
VCC
BOOT
EN
L6747
CHF
PWM4
CS4P
CS4N
ILIM
RILIM
UGATE
HS3
L3
PHASE
IMON
RIMON
PWM
PWM4
CS4P
CS4N
SREF
CSREF
RSREF
LGATE
LS3
R
C
GND
RG
SCOMP
PWM4
CS4P
CS4N
CSF
CSP
RSF
+12V
CDEC
SFB
VCC
BOOT
CSI
CHF
SVSEN
SFBR
SRGND
EN
L6747
RSFB
RSI
HS4
L4
PHASE
LGATE
PWM
REF
UGATE
LS4
R
C
GND
CREF RREF
RG
COMP
CF
CP
RF
+12V
FB
CDEC
VCC
CI
BOOT
RFB
EN
SCSN
SCSP
SPWM
SENDRV
UGATE
HS4
L4
PHASE
LGATE
LS4
R
C
GND
RG
+12V
CDEC
CDEC
SHS
SLS
BOOT
UGATE
L6747
VCC
BOOT
VCC
PHASE
EN
CHF
EN
L6747
VR12
SVID Bus
PWM
+12V
CHF
SL
L6747
CHF
VSEN
FBR
RGND
LTB
SVCLK
ALERT#
SVDATA
RI
HS4
L4
PHASE
LGATE
PWM
LGATE PWM
GND
UGATE
LS4
R
C
GND
RG
RG
CSMLCC
CORE
CSOUT
UNCORE
VR12 uP LOAD
ST L6751 (6+1) Reference Schematic
6/58
CMLCC
COUT
VR12 SVID Bus
Doc ID 024028 Rev 1
AM14834v1
L6751B
Block diagram
VR12 Bus Manager
& PinStrapping Manager
SVCLK
ALERT#
SVDATA
To SinglePhase
FLT Manager
FLT
SImon
Imon
TempZone
DPM
BOOT / TMAX
IMAX / SIMAX
DPM1-3
DPM4-6
ADDR
GDC
EN
OSC
GND (PAD)
Block diagram
VR_RDY
Figure 2.
S_EN
VCC5
VDRV
Start-up Logic
& GDC Control
EN
VR12 Registers
VSEN
MultiPhase
Fault Manager
Ramp & Clock Generator
with VFDE
DPM Control
DPM
FLT
LTB Technology
Modulator
& Frequency Limiter
LTB
ENDRV
Dual DAC & Ref
Generator
PWM1
OV
S
PWM1
SREF
PWM2
REF
S
FBR
RGND
PWM2
PWM3
+175mV
S
IREF
PWM3
PWM4
REF
REMOTE
BUFFER
S
PWM4
PWM5
REF
S
PWM5
VSEN
PWM6
S
COMP
PWM6
OC
Chan #
Voc_tot
Current Balance
& Peak Curr Limit
ILIM
IMON
IDROOP
ILIM
N
IMON
Differential Current Sense
IREF
ERROR
AMPLIFIER
REF
FB
DPM
SMCLK
SMAL#
SMDATA
Chan #
VSEN, SVSEN
VID, SVID
PMBus(TM) Decodification Engine
& Control Logic
PHASE
Thermal
Compensation
and Gain adjust
VIN
TempZone
SFBR
SRGND
ISREF
SREF
CS1P
CS1N
CS2P
CS2N
CS3P
CS3N
CS4P
CS4N
CS5P
CS5N
CS6P
CS6N
TCOMP
Thermal Sensor
and Monitor
SOV
TM
VR_HOT
STM
+175mV
SPWM / SEN
SPWM
SENDRV
SREF
SVSEN
SCOMP
S_EN
Ramp & Clock
Generator
withVFDE
SFLT
ISREF
ERROR
AMPLIFIER
LTB Technology
Modulator
& Frequency Limiter
SREF
SOSC
SFB
Voc_tot
SOC
SIMON
SinglePhase
Fault Manager
To MultiPhase FLT Manage
SFLT
ISMON
Differential
Current Sense
VR_HOT
SCSP
L6751B
SCSN
SVR_RDY
ISDROOP
Thermal
Compensation
and Gain adjust
STCOMP
1.2
Typical application circuit and block diagram
AM14835v1
Doc ID 024028 Rev 1
7/58
Pin description and connection diagram
L6751B
SFBR
DPM1-3
SRGND
DPM4-6
SIMON
SCSN
SCSP
TCOMP
VR_HOT
ILIM
SENDRV
SPWM
TM
SREF
SOSC
CS1N
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
L6751B pin connections (top view)
SVSEN
Figure 3.
33
Pin description and connection diagram
34
2
SFB
35
17
CS1P
SCOMP
36
16
CS2P
IMAX/SIMAX
37
15
CS2N
GND
38
14
CS3N
SMDATA
39
13
CS3P
SMAL#
40
12
CS4P
SMCLK
41
11
CS4N
NC
42
10
CS5N
ADDR
43
9
CS5P
STM
44
8
CS6P
STCOMP
45
7
CS6N
OSC
46
6
GND
VIN
47
5
VR_RDY
EN
48
4
PHASE
SVCLK
49
3
PWM1
ALERT#
50
2
PWM2
SVDATA
51
1
PWM3
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
BOOT / TMAX
VCC5
GDC
VDRV
COMP
FB
VSEN
FBR
LTB
RGND
REF
IMON
SVR_RDY
ENDRV
PWM6
PWM5
PWM4
L6751
2.1
Pin description
Table 2.
Pin description
Name
Type
Function
PWM output.
Connect to multi-phase channel 3 external driver PWM input. During normal operation the device is able to manage HiZ status by setting and holding the PWMx pin to the predefined fixed voltage. See Table 7 for phase
number programming.
1
PWM3
D(1)
2
PWM2
D
3
PWM1
D
4
PHASE
A
n/a
NC
-
5
8/58
VR_RDY
D
MULTI-PHASE SECTION
Pin#
AM14833v1
PWM output.
Connect to multi-phase external drivers PWM input. These pins are also
used to configure HiZ levels for compatibility with drivers and DrMOS. During normal operation the device is able to manage HiZ status by setting
and holding the PWMx pin to the predefined fixed voltage.
Connect through resistor divider to multi-phase channel1 switching node.
Not internally bonded
VR Ready. Open drain output set free after SS has finished in multi-phase
section and pulled low when triggering any protection on multi-phase section. Pull up to a voltage lower than 3.3 V (typ.), if not used it can be left
floating.
Doc ID 024028 Rev 1
L6751B
Table 2.
Pin description and connection diagram
Pin description (continued)
Pin#
Name
Type
Function
6
GND
A
GND connection. All internal references and logic are referenced to this
pin. Filter to VCC5 with proper MLCC capacitor and connect to the PCB
GND plane.
CS6N
A
8
CS6P
A
Channel 6 current sense positive input. Connect through an R-C filter to
the phase-side of the channel 6 inductor. When working at < 6 phases,
short to the regulated voltage.
9
CS5P
A
10
CS5N
A
MULTI-PHASE SECTION
7
Channel 6 current sense negative input. Connect through an Rg resistor to
the output-side of the channel inductor. When working at 0, from pinstrapping; multiphase section
5
mV/μS
Vboot > 0, from pinstrapping; singlephase section
2.5
mV/μS
Vboot > 0, from pinstrapping; singlephase section, JMode ON
2.5
mV/μS
Vboot > 0, from pinstrapping; multiphase section
2.5
mV/μS
Vboot > 0, from pinstrapping; singlephase section
1.25
mV/μS
Soft-start
SS time - Intel DDR mode
EN
SS time - AMD mode
Vboot > 0, from pinstrapping; both
sections
Turn-ON
VEN rising
Turn-OFF
VEN falling
6.25
mV/μS
0.6
0.4
Leakage current
V
V
μA
1
SVI serial bus
SVCLCK,
SVDATA
SVDATA,
ALERT#
Input high
0.65
Input low
Voltage low (ACK)
ISINK = -5 mA
V
0.45
V
50
mV
PMBus
SMDATA,
SMCLK
Input high
SMAL#
Voltage low
1.75
Input low
ISINK = -4 mA
V
1.45
V
13
Ω
Reference and DAC
kVID
kSVID
VOUT accuracy (MPhase)
VOUT accuracy (SPhase)
kVID, kSVID
VOUT accuracy
kVOUT
VOUT accuracy - AMD
mode
IOUT = 0 A; N = 6; RG = 540 Ω; RFB
= 1.108 kΩ; VID >1.000 V
-0.5
0.5
%
IOUT = 0 A; RG = 1.3 kΩ ; VID
>1.000 V
-0.5
0.5
%
IOUT = 0 A; RG = 1.3 kΩ; VID >1.000
V; JMODE = ON
-5
5
mV
VID = 0.8 V to 1 V
-5
5
mV
VID 500
mV
-525
-375
mV
FBR DISC
FB disconnection
VCS- rising, above VSEN/SVSEN
650
750
mV
18/58
Doc ID 024028 Rev 1
700
L6751B
Table 5.
Electrical specifications
Electrical characteristics (continued)
(VCC5 = 5 V ± 5%, TJ = 0 °C to 70 °C unless otherwise specified.)
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
FBG DISC
FBG disconnection
FBR input wrt VID
950
1000
1050
mV
VR_RDY,
SVR_RDY
Voltage low
ISINK = -4 mA
0.4
V
VOC_TOT
OC threshold, MPhase
VILIM rising, to GND
2.5
V
VSOC_TOT
OC threshold, SPhase
VSIMON rising, to GND
1.55
V
IOC_TH
Constant current(1)
MPhase only
35
μA
VR_HOT
Voltage low
ISINK = -4mA
13
Ω
Gate drive control
Max. current
GDC
Any PS.
200
mA
PS00h (GDC=VCC12)
6
Ω
> PS00h; (GDC=VCC5)
6
Ω
Impedance
1. Guaranteed by design, not subject to test.
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Device configuration and pinstrapping tables
4
L6751B
Device configuration and pinstrapping tables
The L6751B features a universal serial data bus fully compliant with Intel VR12/IMVP7
Protocol rev1.5, document #456098 and AMD SVI specifications, document #40182. To
guarantee proper device and CPU operation, refer to these documents for bus design,
layout guidelines and any additional information required for the bus architecture. Different
platforms may require different pull-up impedance on the SVI bus. Impedance matching and
spacing among SVI bus lines must be followed.
The controller configures itself automatically upon detection of different pinstrappings which
are monitored at the IC power-up. See Table 6, 8, 9, 10 e 11 for details.
4.1
JMode
When enabled, multi-phase acts as if in DDR mode, while single-phase is an independent
regulator with 0.75 V fixed reference (load-line disabled - TM can be used as enable for the
single-phase).
Output voltage higher than the internal reference may be achieved by adding a proper
resistor divider (RA, RB - see Figure 4). To maintain precision in output voltage regulation, it
is recommended to provide both SFBR and SRGND with the same divider.
Equation 1
RA + RB
VOUT = 0.750V ⋅ ----------------------RB
Figure 4.
JMode: voltage positioning
Protection
Monitor
0.750 V
SFB
SCOMP
RF
SVSEN
SFBR
SRGND
RA
CF
To Vout
(Remote Sense)
RFB
RA
RB
RB
AM14836v1
20/58
Doc ID 024028 Rev 1
L6751B
Device configuration and pinstrapping tables
4.2
Programming HiZ level
The L6751B is able to manage different levels for HiZ on PWMx guaranteeing flexibility in
driving different external drivers as well as DrMOS ICs.
After EN assertion and before soft-start, the device uses PWM1 and PWM2 to detect the
driver/DrMOS connected in order to program the suitable Hiz level of PWMx signals. During
regulation, the Hiz level is used to force the external MOSFETs in high-impedance state.
–
PWM1 sources a constant 10 μA current, if its voltage results higher than 2.8 V,
HiZ level used during the regulation is 1.4 V, if lower, PWM2 information is used.
–
PWM2 is kept in HiZ, if its voltage results higher than 2 V, HiZ level used during the
regulation is 2 V, if lower, 1.6 V.
An external resistor divider can be placed on PWM1 and PWM2 to force the detection of the
correct HiZ level. They must be designed considering the external driver/DrMOS selected
and the HiZ level requested.
Table 6.
Device configuration
SVI
address
DROOP (see Table 8)
IMAX /
SIMAX
VR12
0000b
Enabled.
VR12
(Note 2)
0010b
0100b
MPhase: as per Table 9. Table 8
SPhase: disabled
AMD
n/a
BOOT /
TMAX
DPM
Table 10
Supported
TMAX
(Note 1)
supported
MPhase: enabled.
Ignored
SPhase: as per Table 9.
1
Refer to Table 10 and choose any of the resistor combinations leading to the desired TMAX.
Other settings are ignored.
2
In DDR mode, single-phase reference is multi-phase Vout/2 (JMode disabled).
Table 7.
Phase number programming
PHASE #
PWM1 to PWM3
3
to driver
4
5
PWM4
PWM5
PWM6
1 kΩ to VCC5
to driver
1 kΩ to VCC5
to driver
6
1 kΩ to VCC5
to driver
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Device configuration and pinstrapping tables
Table 8.
L6751B
IMAX, SIMAX pinstrapping (Note 1)
IMAX / SIMAX
Rdown
Rup
[kΩ]
[kΩ]
Note 2
22/58
SIMAX [A]
IMAX [A]
GFX
VSA/DDR
40
29
35
21
30
13
10
1.5
10
2.7
22
6.8
10
3.6
25
5
27
11
40
29
12
5.6
35
21
82
43
30
13
13
7.5
25
5
56
36
40
29
18
13
35
21
15
12
30
13
18
16
25
5
15
14.7
40
29
10
11
35
21
18
22
30
13
56
75
25
5
10
15
40
29
12
20
35
21
12
22.6
30
13
39
82
25
5
47
110
40
29
10
27
35
21
22
68
30
13
10
36
25
5
18
75
40
29
15
75
35
21
10
59
30
13
10
75
25
5
10
100
40
29
10
150
35
21
10
220
30
13
10
Open
25
5
N ⋅ 25 + 56
N ⋅ 25 + 48
N ⋅ 25 + 40
N ⋅ 25 + 32
N ⋅ 25 + 24
N ⋅ 25 + 16
N ⋅ 25 + 8
N ⋅ 25
Doc ID 024028 Rev 1
L6751B
Note:
Device configuration and pinstrapping tables
1
Recommended values, divider needs to be connected between VCC5 pin and GND.
2
N is the number of phases programmed for the multi-phase section.
Table 9.
ADDR pinstrapping (Note 1, 2)
ADDR
Rdown
Rup
[kΩ]
[kΩ]
10
1.5
ADDR
Note 3
PMBADDR
Note 4
JMode
DROOP
multi-phase
DROOP
single-phase
ON
CCh
10
2.7
22
6.8
OFF
ON
C8h
10
3.6
OFF
AMD mode
27
n/a
ON
11
ON
C4h
12
5.6
82
43
OFF
ON
C0h
13
7.5
56
36
OFF
ON
EEh
18
13
15
12
OFF
ON
EAh
18
16
15
14.7
10
11
18
22
OFF
0100b
(VR12)
n/a
OFF
ON
E6h
OFF
ON
E2h
56
75
10
15
OFF
ON
ECh
12
20
12
22.6
OFF
ON
E8h
39
82
47
110
10
27
22
68
OFF
0010b
(VR12)
n/a
OFF
ON
E4h
OFF
ON
E0h
10
36
OFF
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Device configuration and pinstrapping tables
Table 9.
L6751B
ADDR pinstrapping (Note 1, 2) (continued)
ADDR
Rdown
Rup
[kΩ]
[kΩ]
18
75
ADDR
Note 3
PMBADDR
Note 4
JMode
DROOP
multi-phase
DROOP
single-phase
ON
15
75
10
59
OFF
ON
C8h / 88h
10
75
10
100
10
150
10
220
OFF
0000b
(VR12)
ON
ON
C4h / 84h
OFF
ON
According to VBOOT
settings (GFX / VSA)
CCh / 8Ch
C0h / 80h
10
Note:
Open
OFF
1
Recommended values, divider needs to be connected between VCC5 pin and GND.
2
In DDR mode, when enabled, droop has 1/4th scaling factor.
3
SVI address for multi-phase. Single-phase is further offset by 0001b. In AMD mode, SVI
address defaults according to AMD specifications.
4
PMBus address for multi-phase (read/write). Single-phase is further offset by 02 h. When in
VR12 CPU mode, RCOMP = 12.5 kΩ to GND, select between Cxh (Open) and 8xh (if
installed) PMBus address.
Table 10.
.
BOOT / TMAX pinstrapping (Note 1, 2)
BOOT - Intel address 0000b (Note 3)
Rdown
Rup
[kΩ]
[kΩ]
10
1.5
10
2.7
Multiphase
6.8
10
3.6
TMAX [C]
Link-rest
JMode
0.000 V
VSA
11
12
5.6
43
13
7.5
24/58
120
110
100
1.500 V
130
1.000 V
82
Link rest
32 μsec
(debug)
32 μsec
(debug)
ON
27
VBOOT
130
1.000 V
22
Singlephase
Intel address 0010b, 0100b (Note 3)
1.000 V
VSA
32 μsec
(debug)
10 μsec
(functional)
120
110
100
Doc ID 024028 Rev 1
L6751B
Device configuration and pinstrapping tables
Table 10.
BOOT / TMAX pinstrapping (Note 1, 2) (continued)
BOOT - Intel address 0000b (Note 3)
Rdown
Rup
[kΩ]
[kΩ]
56
36
18
13
Multiphase
12
18
16
TMAX [C]
Link-rest
JMode
1.100 V
VSA
10 μsec
(functional)
14.7
10
11
Link rest
32 μSec
(debug)
120
110
100
ON
15
VBOOT
130
0.000 V
15
Singlephase
Intel address 0010b, 0100b (Note 3)
1.350 V
130
0.000 V
1.000 V
VSA
10 μsec
(functional)
10 μSec
(functional)
120
18
22
56
75
100
10
15
130
12
20
0.000 V
12
22.6
39
82
0.900 V
VSA
32 μSec
(debug)
10 μsec
(functional)
110
10
27
120
110
100
OFF
47
110
1.500 V
130
0.000 V
1.000 V
GFX
32 μsec
(debug)
10 μSec
(functional)
120
22
68
10
36
100
18
75
130
15
75
1.000 V
10
59
10
75
1.000 V
GFX
32 μsec
(debug)
32 μSec
(debug)
100
10
150
220
10
Open
Note:
110
1.350 V
130
0.000 V
10
120
100
OFF
10
110
0.000 V
GFX
10 μsec
(functional)
10 μSec
(functional)
120
110
100
1
Recommended values, divider needs to be connected between VCC5 pin and GND.
2
BOOT is ignored in AMD mode, only TMAX is operative.
3
Operative mode defined by ADDR pin. See Table 9 for details.
Doc ID 024028 Rev 1
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Device configuration and pinstrapping tables
Table 11.
L6751B
DPM pinstrapping (Note 1)
Rdown
Rup
[kΩ]
[kΩ]
10
1.5
DPM1-3 (Note 3, 4)
DPM12
DPM23
DPM4-6 (Note 3, 4)
GDC0
DPM34
2.7
22
6.8
+22A
0
0
1
1
+16A
10
3.6
+14A
0
0
+30A
16A
27
11
1
1
+10A
12
5.6
82
43
+8A
0
0
1
1
+6A
13
7.5
56
36
DPM OFF
0
0
1
1
+22A
+20A
18
13
15
12
0
0
1
1
+16A
18
16
+14A
0
0
+22A
12A
15
14.7
1
1
+10A
10
11
18
22
+8A
0
0
1
1
+6A
56
75
10
15
DPM OFF
0
0
1
1
+22A
+20A
12
20
12
22.6
0
0
1
1
+16A
39
82
+14A
0
0
+14A
8A
47
110
1
1
+10A
10
27
22
68
+8A
0
0
1
1
+6A
10
36
18
75
DPM OFF
0
0
1
1
+22A
+20A
15
75
10
59
0
0
1
1
+16A
10
10
75
100
+14A
0
OFF (12A)
(Note 2)
150
10
220
1
26/58
Open
1
+8A
0
1
+6A
10
0
+8A
+10A
10
GDC1
1
1
+20A
10
DPM46
0
Doc ID 024028 Rev 1
0
DPM OFF
(Note 5)
1
0
L6751B
Note:
Device configuration and pinstrapping tables
1
Suggested values, divider needs to be connected between VCC5 pin and GND.
2
Transition between 1Phase and 2Phase operation is set to 12 A but disabled in PS00h.
3
Transition threshold specified as delta with respect to previous step (DPM23 is wrt DPM12).
4
GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two
different pinstrappings DPM1-3 and DPM4-6. See Table 12 for details.
5
Dynamic phase management disabled, IC always working at maximum possible number of
phases except when in >PS00h when transitioning between 1Phase and 2Phase at 12 A.
Table 12.
GDC threshold definition (Note 1)
GDC1
GDC0
Threshold [A] (Note 2)
1
N ⋅ 17A
0
N ⋅ 13A
1
N ⋅ 9A
0
GDC OFF
1
0
Note:
1
GDC threshold is defined by combining GDC0 and GDC1 bits defined between the two
different pinstrappings DPM1-3 and DPM4-6. See Table 11 for details.
2
N is the number of phases programmed for the multi-phase section.
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Device description and operation
5
L6751B
Device description and operation
The L6751B is a programmable 4/5/6-phase PWM controller that provides complete control
logic and protection to realize a high performance step-down DC-DC voltage regulator
optimized for advanced microprocessor and memory power supply. The device features 2nd
generation LTB Technology: through a load transient detector, it is able to turn on all the
phases simultaneously. This allows the output voltage deviation to be to minimized and, in
turn, also the system costs by providing the fastest response to a load transition.
The L6751B implements current reading across the inductor in fully differential mode. A
sense resistor in series to the inductor can also be considered to improve reading precision.
The current information read corrects the PWM output in order to equalize the average
current carried by each phase.
The controller supports Intel and AMD SVI bus and all the required registers. The platform
may configure and program the defaults for the device through dedicated pinstrapping.
A complete set of protections is available: overvoltage, undervoltage, overcurrent (perphase and total) and feedback disconnection guarantee the load to be safe in all
circumstances.
Special power management features like DPM, VFDE(a) and GDC modify phase number,
gate driving voltage and switching frequency to optimize efficiency over the load range.
The L6751B is available in VFQFPN68 8x8 mm package.
Figure 5.
VCC5
VDRV
Device initialization
UVLO
2μSec POR
UVLO
UVLO
VIN
50μsec
EN
ENVTT
SVI BUS
PMBus
Command ACK but not executed
SVI Packet
SVI Packet
Command rejected
V_SinglePhase
64μsec
SVRRDY
V_MultiPhase
64μsec
VRRDY
AM14837v1
a. VFDE feature can be enabled using dedicated PMBus command. See Section 12 for details.
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Doc ID 024028 Rev 1
L6751B
6
Output voltage positioning
Output voltage positioning
Output voltage positioning is performed by selecting the controller operative-mode, as per
Table 6 for the two sections and by programming the droop function effect (see Figure 6).
The controller reads the current delivered by each section by monitoring the voltage drop
across the DCR inductors. The current (IDROOP / ISDROOP) sourced from the FB / SFB pins,
directly proportional to the read current, causes the related section output voltage to vary
according to the external RFB / RSFB resistor, therefore implementing the desired load-line
effect.
The L6751B embeds a dual remote-sense buffer to sense remotely the regulated voltage of
each section without any additional external components. In this way, the output voltage
programmed is regulated compensating for board and socket losses. Keeping the sense
traces parallel and guarded by a power plane results in common mode coupling for any
picked-up noise.
Figure 6.
Voltage positioning
Protection
Monitor
IDROOP
Ref. from DAC
FB
COMP
RF
VSEN
FBR
To VddCORE
CF
(Remote Sense)
RFB
6.1
RGND
AM14838v1
Multi-phase section - phase # programming
The multi-phase section implements a flexible 3 to 6 interleaved-phase converter. To program the desired number of phases, simply short to VCC5 the PWMx signal that is not
required, according to Table 7.
Caution:
For the disabled phase(s), the current reading pins need to be properly connected to avoid
errors in current-sharing and voltage-positioning: CSxP needs to be connected to the
regulated output voltage while CSxN needs to be connected to CSxP through the same RG
resistor used for the active phases.
6.2
Multi-phase section - current reading and current sharing
loop
The L6751B embeds a flexible, fully-differential current sense circuitry that is able to read
across inductor parasitic resistance or across a sense resistor placed in series to the inductor element. The fully-differential current reading rejects noise and allows sensing element
to be placed in different locations without affecting measurement accuracy. The trans-con-
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Output voltage positioning
L6751B
ductance ratio is issued by the external resistor RG placed outside the chip between the
CSxN pin toward the reading points. The current sense circuit always tracks the current
information; the CSxP pin is used as a reference keeping the CSxN pin to this voltage. To
correctly reproduce the inductor current, an R-C filtering network must be introduced in parallel to the sensing element. The current that flows from the CSxN pin is then given by the
following equation (see Figure 7):
Equation 2
DCR 1 + s ⋅ L ⁄ DCR
I CSxN = ------------- ⋅ -------------------------------------------- ⋅ I
1+s⋅ R⋅ C
RG
PHASEx
Considering now the matching of the time constant between the inductor and the R-C filter
applied (time constant mismatches cause the introduction of poles into the current reading
network causing instability. In addition, it is also important for the load transient response
and to let the system show resistive equivalent output impedance), it results:
Equation 3
L
------------- = R ⋅ C
DCR
Figure 7.
⇒
RL
ICSxN = -------- ⋅ IPHASEx = I INFOx
RG
Current reading
IPHASEx
Lx
ICSxN=IINFOx
DCRx
VOUT
R
C
CSxP
CSxN
RG
Inductor DCR Current Sense
AM14839v1
The current read through the CSxP / CSxN pairs is converted into a current IINFOx proportional to the current delivered by each phase and the information about the average current
IAVG = ΣIINFOx / N is internally built into the device (N is the number of working phases). The
error between the read current IINFOx and the reference IAVG is then converted into a voltage
that, with a proper gain, is used to adjust the duty cycle whose dominant value is set by the
voltage error amplifier in order to equalize the current carried by each phase.
6.3
Multi-phase section - defining load-line
The L6751B introduces a dependence of the output voltage on the load current recovering
part of the drop due to the output capacitor ESR in the load transient. Introducing a dependence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current.
30/58
Doc ID 024028 Rev 1
L6751B
Output voltage positioning
Figure 7 shows the current sense circuit used to implement the load-line. The current flowing across the inductor(s) is read through the R-C filter across the CSxP and CSxN pins. RG
programs a trans-conductance gain and generates a current ICSx proportional to the current
of the phase. The sum of the ICSx current, with proper gain eventually adjusted by the
PMBus commands, is then sourced by the FB pin (IDROOP). RFB gives the final gain to program the desired load-line slope (Figure 6).
Time constant matching between the inductor (L / DCR) and the current reading filter (RC)
is required to implement a real equivalent output impedance of the system, therefore avoiding over and/or undershoot of the output voltage as a consequence of a load transient. The
output voltage characteristic vs. load current is then given by:
Equation 4
DCR
V OUT = VID – R FB ⋅ I DROOP = VID – RFB ⋅ ------------- ⋅ I OUT = VID – RLL ⋅ I OUT
RG
where RLL is the resulting load-line resistance implemented by the multi-phase section.
The RFB resistor can be then designed according to the RLL specifications as follows:
Equation 5
RG
R FB = R LL ⋅ ------------DCR
Caution:
When in DDR mode, and enabled, droop current has a scaling factor equal to 1/4. All the
above equations must be scaled accordingly.
6.4
Single-phase section - disable
The single-phase section can be disabled by pulling high the SPWM pin. The related
command is rejected.
6.5
Single-phase section - current reading
The single-phase section performs the same differential current reading across DCR as the
multi-phase section. According to Section 6.2, the current that flows from the SCSN pin is
then given by the following equation (see Figure 7):
Equation 6
DCR
I SCSN = ------------- ⋅ ISOUT = ISDROOP
R SG
6.6
Single-phase section - defining load-line
This method introduces a dependence of the output voltage on the load current recovering
part of the drop due to the output capacitor ESR in the load transient. Introducing a depen-
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Output voltage positioning
L6751B
dence of the output voltage on the load current, a static error, proportional to the output current, causes the output voltage to vary according to the sensed current.
Figure 7 shows the current sense circuit used to implement the load-line. The current flowing across the inductor DCR is read through RSG. RSG programs a trans-conductance gain
and generates a current ISDROOP proportional to the current delivered by the single-phase
section that is then sourced from the SFB pin with proper gain eventually adjusted by the
PMBus commands. RSFB gives the final gain to program the desired load-line slope
(Figure 6).
The output characteristic vs. load current is then given by:
Equation 7
V SOUT = VID – RSFB ⋅ I SDROOP
DCR
VID – R SFB ⋅ ------------- ⋅ I SOUT = VID – R SLL ⋅ I SOUT
RSG
where RSLL is the resulting load-line resistance implemented by the single-phase section.
R
DCR
SG
RSFB resistor can be then designed according to the RSLL as follows: R SFB = R SLL ⋅ ------------
6.7
Dynamic VID transition support
The L6751B manages dynamic VID transitions that allow the output voltage of both sections
to be modified during normal device operation for power management purposes. OV, UV
and OC signals are masked during every DVID transition and they are re-activated with
proper delay to prevent from false triggering.
When changing dynamically the regulated voltage (DVID), the system needs to charge or
discharge the output capacitor accordingly. This means that an extra-current IDVID needs to
be delivered (especially when increasing the output regulated voltage) and it must be considered when setting the overcurrent threshold of both the sections. This current results:
Equation 8
dV OUT
I DVID = C OUT ⋅ -----------------dT VID
where dVOUT / dTVID depends on the specific command issued (20 mV/μsec. for
SetVID_Fast and 5 mV/μsec. for SetVID_Slow). Overcoming the total OC threshold during
the dynamic VID causes the device to latch and disable. Set proper filtering on ILIM to prevent from false total-OC tripping.
As soon as the controller receives a new valid command to set the VID level for one (or
both) of the two sections, the reference of the involved section steps up or down according
to the target-VID with the programmed slope until the new code is reached. If a new valid
command is issued during the transition, the device updates the target-VID level and
performs the dynamic transition up to the new code. OV, UV are masked during the
transition and re-activated with proper delay after the end of the transition to prevent from
false triggering.
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L6751B
6.7.1
Output voltage positioning
LSLESS startup and pre-bias output
Any time the device resumes from an “OFF” code and at the first power-up, in order to avoid
any kind of negative undershoot on the load side, the L6751B performs a special sequence
in enabling the drivers: during the soft-start phase, the LS driver results as being disabled
(LS=OFF - PWMx set to HiZ and ENDRV = 0) until the first PWM pulse. After the first PWM
pulse, PWMx outputs switch between logic “0” and logic “1” and ENDRV is set to logic “1”.
This particular sequence avoids the dangerous negative spike on the output voltage that
can occur if starting over a pre-biased output.
Low-side MOSFET turn-on is masked only from the control loop point of view: protection is
still allowed to turn on the low-side MOSFET if overvoltage is needed.
Figure 8.
SLESS startup: enabled (left) Figure 9.
AM14840v1
6.8
LSLESS startup: disabled
(right)
AM14841v1
DVID optimization: REF/SREF
High slew rate for dynamic VID transitions causes undershoot on the regulated voltage,
causing violation in the microprocessor requirement. To compensate this behavior and to
remove any undershoot in the transition, each section features DVID optimization circuit.
The reference used for the regulation is available on the REF/SREF pin (see Figure 10).
Connect an RREF/CREF to GND (RSREF/CSREF for the single-phase) to optimize the DVID
behavior. Components may be designed as follows (multi-phase, same equations apply to
single-phase):
Equation 9
ΔVOSC ⎞
C REF = C F ⋅ ⎛ 1 – ---------------------⎝
k ⋅ V ⎠
V
IN
RF ⋅ CF
R REF = --------------------C REF
where ΔVosc is the PWM ramp and kV the gain for the voltage loop (see Section 11).
During a falling DVID transition, the REF pin moves according to the DVID command issued;
the current requested to charge/discharge the RREF/CREF network is mirrored and added to
the droop current compensating for undershoot on the regulated voltage.
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Output voltage monitoring and protection
L6751B
IDROOP
Figure 10. DVID optimization circuit
Ref. from DAC
VCOMP
Ref
COMP
FB
REF
RREF
RF
CREF
CF
FBR
RGND
VSEN
Ref
To VddCORE
(Remote Sense)
ZF(s)
ZFB(s)
RFB
AM14842v1
7
Output voltage monitoring and protection
The L6751B monitors the regulated voltage of both sections through pin VSEN and SVSEN
in order to manage OV and UV. The device shows different thresholds when in different
operative conditions but the behavior in response to a protection event is still the same as
described below.
Protection is active also during soft-start while it is properly masked during DVID transitions
with an additional delay to avoid false triggering. OV protection is active during DVID with
threshold modified to 1.8 V unless offset has been commanded by SVI or PMBus: in this
case the fixed threshold is 2.4 V.
Table 13.
L6751B protection at a glance.
Section
Multi-phase
Overvoltage
(OV)
VSEN, SVSEN = +175 mV above reference.
Action: IC latch; LS = ON & PWMx = 0 (if applicable); other section: HiZ.
VR_READY of the latched section resets (only).
Undervoltage
(UV)
VSEN, svsen = 400 mv below reference. active after ref > 500 mv
action: ic latch; both sections HiZ. VR_READY of the latched section resets
(only).
Overcurrent (OC)
Current monitor across inductor DCR. Dual protection, per-phase and total.
Action: UV-Like. VR_READY of the latched section resets (only).
Dynamic VID
34/58
Single-phase
Protection masked with additional delay to prevent from false triggering.
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L6751B
7.1
Output voltage monitoring and protection
Overvoltage
When the voltage sensed by VSEN and/or SVSEN surpasses the OV threshold, the controller acts in order to protect the load from excessive voltage levels avoiding any possible
undershoot. To reach this target, a special sequence is performed as per the following list:
–
The reference performs a DVID transition down to 250 mV on the section which
triggered the OV protection.
–
The PWMs of the section which triggered the protection are switched between HiZ
and zero (ENDRV is kept high) in order to follow the voltage imposed by the DVID
on-going. This limits the output voltage excursion, protects the load and assures
no undershoot is generated (if Vout < 250 mV, the section is HiZ).
–
The PWMs of the non-involved section are set permanently to HiZ (ENDRV is kept
low) in order to realize a HiZ condition.
–
OSC/ FLT pin is driven high.
–
Power supply or EN pin cycling is required to restart operation.
If the cause of the failure is removed, the converter ends the transition with all PWMs in HiZ
state and the output voltage of the section which triggered the protection lower than 250 mV.
7.2
Overcurrent and current monitor
The overcurrent threshold must be programmed to a safe value, in order to be sure that
each section does not enter OC during normal operation of the device. This value must take
into consideration also the process spread and temperature variations of the sensing elements (inductor DCR).
Furthermore, since also the internal threshold spreads, the design must consider the minimum/maximum values of the threshold.
7.2.1
Multi-phase section
The L6751B features two independent load indicator signals, IMON and ILIM, to properly
manage OC protection, current monitoring and DPM. Both IMON and ILIM source a current
proportional to the current delivered by the regulator, as follows:
Equation 10
DCR
I MON = ILIM = ------------- ⋅ I OUT
RG
The IMON and ILIM pins are connected to GND through a resistor (RIMON and RILIM respectively), implementing a load indicator with different targets.
●
IMON is used for current reporting purposes and for the DPM phase shedding. RIMON
must be designed considering that IMAX must correspond to 1.24 V (for correct IMAX
detection).
●
ILIM is used for the overcurrent protection only. RILIM must be designed considering
that the OC protection is triggered when V(ILIM)=2.5 V.
In addition, the L6751B also performs per-phase OC protection.
–
Per-phase OC.
Maximum information current per-phase (IINFOx) is internally limited to 35 μA. This
end-of-scale current (IOC_TH) is compared with the information current generated
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Output voltage monitoring and protection
L6751B
for each phase (IINFOx). If the current information for the single-phase exceeds the
end-of-scale current (i.e. if IINFOx > IOC_TH), the device turns on the LS MOSFET
until the threshold is re-crossed (i.e. until IINFOx < IOC_TH).
–
Total current OC.
The ILIM pin allows a maximum total output current for the system (IOC_TOT) to be
defined. ILIM current is sourced from the ILIM pin. By connecting a resistor RILIM
to GND, a load indicator with 2.5 V (VOC_TOT) end-of-scale can be implemented.
When the voltage present at the ILIM pin crosses VOC_TOT, the device detects an
OC and immediately latches with all the MOSFETs of all the sections OFF (HiZ).
Typical design considers the intervention of the total current OC before the per-phase OC,
leaving this last one as an extreme-protection in case of hardware failures in the external
components. Per-phase OC depends on the RG design while total OC is dependant on the
ILIM design and on the application TDC and max. current supported. Typical design flow is
the following:
–
Define the maximum total output current (IOC_TOT) according to system
requirements (IMAX, ITDC). Considering IMON design, IMAX must correspond to 1.24
V (for correct IMAX detection) while considering ILIM design IOC_TOT has to
correspond to 2.5 V.
–
Design per-phase OC and RG resistor in order to have IINFOx = IOC_TH (35 μA)
when IOUT is about 10% higher than the IOC_TOT current. It results:
Equation 11
( 1.1 ⋅ I OC_TOT ) ⋅ DCR
R G = ------------------------------------------------------------N ⋅ I OCTH
where N is the number of phases and DCR the DC resistance of the inductors. RG
should be designed in worst-case conditions.
–
Design the RIMON in order to have the IMON pin voltage to 1.24 V at the IMAX
current specified by the design. It results:
Equation 12
1.24V ⋅ R G
R IMON = -------------------------------I MAX ⋅ DCR
where IMAX is max. current requested by the processor (see Intel docs for details).
–
Design the RILIM in order to have the ILIM pin voltage to 2.5 V at the IOC_TOT
current specified above. It results:
Equation 13
2.5V ⋅ RG
R ILIM = ----------------------------------------I OC_TOT ⋅ DCR
where IOC_TOT is the overcurrent switch-over threshold previously defined.
36/58
–
Adjust the defined values according to application bench testing.
–
CILIM in parallel to RILIM can be added with proper time constant to prevent false
OC tripping and/or delay.
Doc ID 024028 Rev 1
L6751B
Output voltage monitoring and protection
–
CIMON in parallel to RIMON can be added to adjust the averaging interval for the
current reporting and/or adjust the DPM latencies. Additionally, it can be increased
to prevent false total-OC tripping during DVID.
Note:
This is the typical design flow. Custom design and specifications may require different
settings and ratios between the per-phase OC threshold and the total current OC threshold.
Applications with big ripple across inductors may be required to set per-phase OC to values
different than 110%: design flow should be modified accordingly.
Note:
Current reporting precision on IMON may be affected by external layout. The internal ADC is
referenced to the device GND pin: in order to perform the highest accuracy in the current
monitor, RIMON must be routed to the GND pin with dedicated net to avoid GND plane drops
affecting the precision of the measurement.
7.2.2
Overcurrent and power states
When the controller receives an SetPS command through the SVI interface, it automatically
changes the number of working phases. In particular, the maximum number of phases
which L6751B may work in >PS00h is limited to 2 phases regardless of the number N
configured in PS00h.
OC level is then scaled as the controller enters >PS00h, as per Table 14.
Table 14.
Multi-phase section OC scaling and power states
Power state [Hex]
N
OC level (VOC_TOT)
00h
3 to 6
2.500 V
3
1.650 V
4
1.250 V
5
1.000 V
6
0.830 V
01h, 02h
7.2.3
Single-phase section
The L6751B performs two different kinds of OC protection for the single-phase section: it
monitors both the total current and the per-phase current and allows an OC threshold to be
set for both.
–
Per-phase OC.
Maximum information current per-phase (ISINFOx) is internally limited to 35 μA.
This end-of-scale current (ISOC_TH) is compared with the information current
generated for each phase (ISINFOx). If the current information for the single-phase
exceeds the end-of-scale current (i.e. if ISINFOx > ISOC_TH), the device turns on the
LS MOSFET until the threshold is re-crossed (i.e. until ISINFOx < ISOC_TH).
–
Total current OC.
The SIMON pin allows a maximum total output current for the system (ISOC_TOT)
to be defined. ISMON current is sourced from the SIMON pin. By connecting a
resistor RSIMON to GND, a load indicator with 1.55 V (VSOC_TOT) end-of-scale can
be implemented. When the voltage present at the SIMON pin crosses VSOC_TOT,
the device detects an OC and immediately latches with all the MOSFETs of all the
sections OFF (HiZ).
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Output voltage monitoring and protection
L6751B
Typical design considers the intervention of the total current OC before the per-phase OC,
leaving this last one as an extreme protection in case of hardware failures in the external
components. Total current OC is, moreover, dependant on the SIMON design and on the
application TDC and MAX current supported. Typical design flow is the following:
–
Define the maximum total output current (ISOC_TOT) according to system
requirements (ISMAX, ISTDC). Considering ISMON design, ISMAX must correspond to
1.24 V (for correct SIMAX detection) so ISOC_TOT results defined, as a
consequence, as
I SOC_TOT = I SMAX ⋅ 1.55 ⁄ 1.24
–
Design per-phase OC and RSG resistor in order to have ISINFOx = ISOC_TH (35 μA)
when ISOUT is about 10% higher than the ISOC_TOT current. It results:
Equation 14
( 1.1 ⋅ I SOC_TOT ) ⋅ DCR
R SG = ----------------------------------------------------------------ISOCTH
where DCR is the DC resistance of the inductors. RSG should be designed in
worst-case conditions.
–
Design the total current OC and RSIMON in order to have the SIMON pin voltage to
1.24 V at the ISMAX current specified by the design. It results:
Equation 15
1.24V ⋅ R SG
R SIMON = -----------------------------------ISMAX ⋅ DCR
DCR
⎛I
= ------------- ⋅ I SOUT⎞
⎝ SIMON RSG
⎠
where ISMAX is max. current requested by the processor (see Intel docs for
details).
Note:
38/58
–
Adjust the defined values according to application bench tests.
–
CSIMON in parallel to RSIMON can be added with proper time constant to prevent
false OC tripping.
This is the typical design flow. Custom design and specifications may require different
settings and ratios between the per-phase OC threshold and the total current OC threshold.
Applications with big ripple across inductors may be required to set per-phase OC to values
different than 110%: design flow should be modified accordingly.
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L6751B
8
Single NTC thermal monitor and compensation
Single NTC thermal monitor and compensation
The L6751B features single NTC for thermal sensing for both thermal monitoring and
compensation. Thermal monitor consists in monitoring the converter temperature eventually
reporting alarm by asserting the VR_HOT signal. This is the base for the temperature
reporting. Thermal compensation consists in compensating the inductor DCR derating with
temperature, so preventing drifts in any variable correlated to the DCR: voltage positioning,
overcurrent (ILIM), IMON, current reporting. Both the functions share the same thermal
sensor (NTC) to optimize the overall application cost without compromising performance.
Thermal monitor is featured for both single-phase and multi-phase sections.
8.1
Thermal monitor and VR_HOT
The diagram for thermal monitor is reported in Figure 11. NTC should be placed close to the
power stage hot-spot in order to sense the regulator temperature. As the temperature of the
power stage increases, the NTC resistive value decreases, therefore reducing the voltage
observable at the TM/STM pin.
Recommended NTC is NTHS0805N02N6801HE for accurate temperature sensing and
thermal compensation. Different NTC may be used: to reach the requested accuracy in
temperature reporting, proper resistive network must be used in order to match the resulting
characteristic with the one coming from the recommended NTC.
The voltage observed at the TM/STM pin is internally converted and then used for the
temperature reporting. When the temperature observed on one of the two thermal sensors
exceeds TMAX (programmed via pinstrapping), the L6751B asserts VR_HOT (active low as long as the overtemperature event lasts).
Figure 11. Thermal monitor connections
2k
NTC
TM
TEMPERATURE
DECODING
VCC5
VR_HOT
Temp. zone
AM14843v1
8.2
Thermal compensation
The L6751B supports DCR sensing for output voltage positioning: the same current
information used for voltage positioning is used to define the overcurrent protection and the
current reporting. Having imprecise and temperature-dependant information leads to
violation of the specification and misleading information: positive thermal coefficient specific
from DCR needs to be compensated to get stable behavior of the converter as temperature
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Single NTC thermal monitor and compensation
L6751B
increases. Un-compensated systems show temperature dependencies on the regulated
voltage, overcurrent protection and current reporting.
The temperature information available on the TM/STM pin and used for thermal monitor may
be used also for this purpose. By comparing the voltage on the TM/STM pin with the voltage
present on the TCOMP/STCOMP pin, the L6751B corrects the IDROOP/ISDROOP current
used for voltage positioning (see Section 6.3), so recovering the DCR temperature
deviation. Depending on NTC location and distance from the inductors and the available
airflow, the correlation between NTC temperature and DCR temperature may be different:
TCOMP/STCOMP adjustments allow the gain between the sensed temperature and the
correction made upon the IDROOP/ISDROOP current to be modified.
Short TCOMP/STCOMP to GND to disable thermal compensation (no correction of
IDROOP/ISDROOP is made).
8.3
TM/STM and TCOMP/STCOMP design
This procedure applies to both single-phase and multi-phase sections.
1.
Properly choose the resistive network to be connected to the TM pin. Recommended
values/network is reported in Figure 11.
2.
Connect voltage generator to the TCOMP pin (default value 3.3 V).
3.
Power on the converter and load the thermal design current (TDC) with the desired
cooling conditions. Record the output voltage regulated as soon as the load is applied.
4.
Wait for thermal steady-state. Adjust down the voltage generator on the TCOMP pin in
order to get the same output voltage recorded at point #3.
5.
Design the voltage divider connected to TCOMP (between VCC5 and GND) in order to
get the same voltage set to TCOMP at point #4.
6.
Repeat the test with the TCOMP divider designed at point #5 and verify the thermal
drift is acceptable.
In case of positive drift (i.e. output voltage at thermal steady-state is bigger than
output voltage immediately after loading TDC current), change the divider at the
TCOMP pin in order to reduce the TCOMP voltage.
In case of negative drift (i.e. output voltage at thermal steady-state is smaller than
output voltage immediately after loading TDC current), change the divider at the
TCOMP pin in order to increase the TCOMP voltage.
7.
40/58
The same procedure can be implemented with a variable resistor in place of one of the
resistors of the divider. In this case, once the compensated configuration is found,
simply replace the variable resistor with a resistor with the same value.
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L6751B
9
Efficiency optimization
Efficiency optimization
As per VR12 specifications, the SVI master may define different power states for the VR
controller. This is performed by SetPS commands. The L6751B re-configures itself to
improve overall system efficiency, according to Table 15.
Table 15.
Efficiency optimization
Feature
9.1
PS00h
PS01h
DPM
According to pinstrapping
Active. 1Phase/2Phase according to
Iout
VFDE
Active when in single-phase and
DPM enabled
Active when in single-phase
GDC
12 V driving
GDC set to 5 V
Dynamic phase management (DPM)
Dynamic phase management allows the number of working phases to be adjusted
according to the delivered current still maintaining the benefits of the multi-phase regulation.
Phase number is reduced by monitoring the voltage level across the IMON pin: the L6751B
reduces the number of working phases according to the strategy defined by the DPM
pinstrapping and/or PMBus (TM) commands received (see Table 11). DPM12 refers to the
current at which the controller changes from 1 to 2 phases. In the same way, DPM23 defines
the current at which the controller changes from 2 to 3 phases and so on.
When DPM is enabled, the L6751B starts monitoring the IMON voltage for phase number
modification after VR_RDY has transition high: the soft-start is then implemented in
interleaving mode with all the available phases enabled.
DPM is reset in case of an SetVID command that affects the CORE section and when LTB
Technology detects a load transient. After being reset, if the voltage across IMON is
compatible, DPM is re-enabled after proper delay.
Delay in the intervention of DPM can be adjusted by properly sizing the filter across the
IMON pin. Increasing the capacitance results in increased delay in the DPM intervention.
See Section 7.2.1 for guidelines in designing the IMON load indicator.
Note:
During load transients with light slope, the filtering of IMON may result too slow for the IC to
set the correct number of phases required for the current effectively loading the system (LTB
does not trigger in case of light slopes). The L6751B features a safety mechanism which reenables phases that were switched off by comparing ILIM and IMON pin voltage. In fact, the
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Efficiency optimization
L6751B
‘ILIM pin is lightly filtered in order to perform fast reaction of OC protection while IMON is
heavily filtered to perform correct averaging of the information.
While working continuously in DPM, the device compares the information of IMON and ILIM:
ILIM voltage is divided in N steps whose width is VOCP/(2*N) (where VOCP = 2.5 V and N the
number of stuffed phases).
If the DPM phase number resulting from IMON is not coherent with the step in which ILIM
stays, the phase number is increased accordingly.
The mechanism is active only to increase the phase number which is reduced again by
DPM.
9.2
Variable frequency diode emulation (VFDE)
As the current required by the load is reduced, the L6751B progressively reduces the
number of switching phases according to DPM settings on the multi-phase section. If singlephase operation is configured, when the delivered current approaches the CCM/DCM
boundary, the controller enters VFDE operation. Single-phase section, being a singlephase, enters VFDE operation always when the delivered current approaches the
CCM/DCM boundary.
In a common single-phase DC-DC converter, the boundary between CCM and DCM is
when the delivered current is perfectly equal to 1/2 of the peak-to-peak ripple into the
inductor (Iout = Ipp/2).
Further decreasing the load in this condition maintaining CCM operation would cause the
current into the inductor to reverse, so sinking current from the output for a part of the offtime. This results in a poorly efficient system.
The L6751B is able (via the CSPx/CSNx pins) to detect the sign of the current across the
inductor (zero cross detection, ZCD), so it is able to recognize when the delivered current
approaches the CCM/DCM boundary. In VFDE operation, the controller fires the high-side
MOSFET for a TON and the low-side MOSFET for a TOFF (the same as when the controller
works in CCM mode) and waits the necessary time until next firing in high impedance (HiZ).
The consequence of this behavior is a linear reduction of the “apparent” switching frequency
that, in turn, results in an improvement of the efficiency of the converter when in very light
load conditions.
The “apparent” switching frequency reduction is limited to 30 kHz so as not to enter the
audible range.
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L6751B
Efficiency optimization
Figure 12. Output current vs. switching frequency in PSK mode
Iout = Ipp/2
Iout < Ipp/2
t
t
Tsw
Tsw
9.2.1
Tvfde
AM14844v1
VFDE and DrMOS
To guarantee correct behavior for DrMOS power stage compliant with Intel specification
rev3, it is recommended to control the DrMOS’ SMOD input through the ENDRV/SENDRV
pins of the L6751B. DrMOS enable must be controlled with the same signal used for the
L6751B EN pin.
Proper HiZ level can be programmed by adding proper external resistor divider across
PWM1 and PWM2. See Section 4.2 for details about HiZ level recognition. See reference
schematic in Figure 1.
9.3
Gate drive control (GDC)
Gate drive control (GDC) is a proprietary function which allows the L6751B to dynamically
control the Power MOSFET driving voltage in order to further optimize the overall system
efficiency. According to the SVI power state commanded and the configuration received
through the PMBus, the device switches this pin (GDC) between VCC5 or VDRV (inputs).
By connecting the power supply of external drivers directly to this pin, it is then possible to
carefully control the external MOSFET driving voltage.
In fact, high driving voltages are required to obtain good efficiency in high loading
conditions. On the contrary, in lower loading conditions, such high driving voltage penalizes
efficiency because of high losses in Qgs. GDC allows to tune the MOSFET driving voltage
according to the delivered current.
The default configuration considers GDC always switched to VDRV except when entering
power states higher than PS01h (included): in this case, to further increase efficiency,
simply supply Phase1 and Phase2 driver through the GDC pin. Their driving voltage is
automatically updated as lower power states are commanded through the SVI interface.
Further optimization may be possible by properly setting an automatic GDC threshold
through the dedicated PMBus command and/or pinstrapping. It is then possible to enable
the gate driving voltage switchover even in PS00h. According to the positioning of the
threshold compared with DPM thresholds, it is possible to achieve different performances.
Simulations and/or bench tests may be of help in defining the best performing configuration
achievable with the active and passive components available.
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Efficiency optimization
L6751B
Figure 13 allows the efficiency improvements with DPM/GDC enabled to be compared with
respect to the standard solution.
Note:
Systems supporting S3 power state may have the VDRV supplied by an OR-ing connection
between 5 Vsby and 12 V or different supply voltage for S0. It is recommended to connect
closely, between the VDRV and VCC5 pins, the OR-ing diode connecting VDRV to the 5
Vsby.
Figure 13. Efficiency performance with and without enhancements (DPM, GDC).
44/58
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L6751B
10
Main oscillator
Main oscillator
The internal oscillator generates the triangular waveform for the PWM charging and
discharging, with a constant current, an internal capacitor. The switching frequency for each
channel is internally fixed at 200 kHz (FSW) and at 230 kHz (FSSW): the resulting switching
frequency at the load side for the multi-phase section results in being multiplied by N
(number of configured phases).
The current delivered to the oscillator is typically 20 μA and may be varied using an external
resistor (ROSC, RSOSC) typically connected between the OSC/SOSC pins and GND. Since
the OSC/SOSC pins are fixed at 1.02 V, the frequency is varied proportionally to the current
sunk from the pin considering the internal gain of 10 kHz/μA for the multi-phase section and
of 11.5 kHz/μA for the single-phase section, see Figure 14.
Connecting ROSC/RSOSC to SGND, the frequency is increased (current is sunk from the pin),
according to the following relationships:
Equation 16
1.02V
kHz
F SW = 200kHz + --------------------------- ⋅ 10 ----------R OSC ( kΩ)
μA
Equation 17
1.02V
kHz
FSSW = 250kHz + ------------------------------- ⋅ 11.5 ----------R SOSC ( kΩ)
μA
Connecting ROSC/RSOSC to a positive voltage Vbias, the frequency is reduced (current is
injected into the pin), according to the following relationships:
Equation 18
Vbias – 1.02V
kHz
FSW = 200kHz – -------------------------------------- ⋅ 10 ----------R OSC ( kΩ)
μA
Equation 19
Vbias – 1.02V
kHz
F SSW = 250kHz – -------------------------------------- ⋅ 11.5 ----------R SOSC ( kΩ)
μA
Figure 14. ROSC vs. FSW per phase (ROSC to GND - left; ROSC to 3.3 V - right)
1000
1000
100
Multi Phase section
SinglePhase section
Multi Phase section
SinglePhase section
10
100
200
300
400
500
600
700
800
900
1000
75
100
125
150
175
200
225
AM14849v1
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System control loop compensation
11
L6751B
System control loop compensation
The control system can be modeled with an equivalent single-phase converter with the only
difference being the equivalent inductor L/N (where each phase has an L inductor and N is
the number of the configured phases), see Figure 15.
Figure 15. Equivalent control loop.
PWM
d VCOMP
L/N
VOUT
Ref
VCOMP
FB
COMP
RF
VSEN
IDROOP
CO
RO
ESR
FBR
RGND
CF
ZF(s)
ZFB(s)
RFB
AM14846v1
The control loop gain results (obtained opening the loop after the COMP pin):
Equation 20
PWM ⋅ Z F ( s ) ⋅ ( RLL + Z P ( s ) )
G LOOP ( s ) = – -----------------------------------------------------------------------------------------------------------------------ZF ( s ) ⎛
1 ⎞
[ Z P ( s ) + Z L ( s ) ] ⋅ -------------- + ⎝ 1 + ------------⎠ ⋅ R FB
A( s)
A(s )
where:
●
RLL is the equivalent output resistance determined by the droop function (voltage
positioning)
●
ZP(s) is the impedance resulting from the parallel of the output capacitor (and its ESR)
and the applied load RO
●
ZF(s) is the compensation network impedance
●
ZL(s) is the equivalent inductor impedance
●
A(s) is the error amplifier gain
●
V IN
9
PWM = ------ ⋅ ------------------- is the PWM transfer function.
10 ΔV OSC
The control loop gain is designed in order to obtain a high DC gain to minimize static error
and to cross the 0 dB axes with a constant -20 dB/dec slope with the desired crossover
frequency ωT. Neglecting the effect of ZF(s), the transfer function has one zero and two
poles; both poles are fixed once the output filter is designed (LC filter resonance ωLC) and
the zero (ωESR) is fixed by ESR and the droop resistance.
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L6751B
System control loop compensation
Figure 16. Control loop bode diagram and fine tuning.
dB
dB
CF
GLOOP(s)
GLOOP(s)
K
K
ZF(s)
RF[dB]
RF[dB]
ZF(s)
RF
wLC = wF
wESR
wT
w
wLC = wF
wESR
wT
w
AM14847v1
To obtain the desired shape, an RF-CF series network is considered for the ZF(s)
implementation. A zero at ωF=1/RFCF is then introduced together with an integrator. This
integrator minimizes the static error while placing the zero ωF in correspondence with the LC resonance assures a simple -20 dB/dec shape of the gain.
In fact, considering the usual value for the output filter, the LC resonance results as being at
a frequency lower than the above reported zero.
The compensation network can be designed as follows:
Equation 21
R FB ⋅ ΔV OSC 10
FSW ⋅ L
R F = ------------------------------------- ⋅ ------ ⋅ ---------------------------------V IN
( R LL + ESR )
9
Equation 22
CO ⋅ L
C F = ---------------------RF
11.1
Compensation network guidelines
The compensation network design assures a system response according to the crossover
frequency selected and to the output filter considered: it is however possible to further fine
tune the compensation network by modifying the bandwidth in order to get the best
response of the system as follows (see Figure 16):
–
Increase RF to increase the system bandwidth accordingly.
–
Decrease RF to decrease the system bandwidth accordingly.
–
Increase CF to move ωF to low frequencies, increasing as a consequence the
system phase margin.
Having the fastest compensation network does not guarantee load requirements are
satisfied: the inductor still limits the maximum dI/dt that the system can afford. In fact, when
a load transient is applied, the best that the controller can do is to “saturate” the duty cycle to
its maximum (dMAX) or minimum (0) value. The output voltage dV/dt is then limited by the
inductor charge/discharge time and by the output capacitance. In particular, the most
limiting transition corresponds to the load-removal since the inductor results being
discharged only by Vout (while it is charged by VIN-VOUT during a load appliance).
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System control loop compensation
L6751B
Note:
The introduction of a capacitor (CI) in parallel to RFB significantly speeds up the transient
response by coupling the output voltage dV/dt on the FB pin, so using the error amplifier as
a comparator. The COMP pin suddenly reacts and, also thanks to the LTB Technology
control scheme, all the phases can be turned on together to immediately give the required
energy to the output. Typical design considers starting from values in the range of 100 pF,
validating the effect by bench testing. Additional series resistor (RI) can also be used.
11.2
LTB Technology
LTB Technology further enhances the performance of the controller by reducing the system
latencies and immediately turning on all the phases to provide the correct amount of energy
to the load optimizing the output capacitor count.
LTB Technology monitors the output voltage through a dedicated pin detecting loadtransients with selected dV/dt, it cancels the interleaved phase-shift, turning on
simultaneously all phases.
The LTB detector is able to detect output load transients by coupling the output voltage
through an RLTB - CLTB network. After detecting a load transient, all the phases are turned
on together and the EA latencies also result as bypassed.
Sensitivity of the load transient detector can be programmed in order to control precisely
both the undershoot and the ring-back.
LTB Technology design tips.
48/58
–
Decrease RLTB to increase the system sensitivity making the system sensitive to
smaller dVOUT
–
Increase CLTB to increase the system sensitivity making the system sensitive to
higher dV/dt
–
Increase Ri to increase the width of the LTB pulse
–
Increase Ci to increase the LTB sensitivity over frequency.
Doc ID 024028 Rev 1
L6751B
12
PMBus support (preliminary)
PMBus support (preliminary)
The L6751B is compatible with PMBus™ standard revision 1.1, refer to PMBus standard
documentation for further information (www.pmbus.org).
Table 16.
Supported commands
Per
Rail
Code
[Hex]
Mode
Comments
Y
01
RW Byte
Used to turn the controller on/off in conjunction with the input
from the control pin. Also used to set margin voltages. Soft off
not supported
ON_OFF_CONFIG
N1
02
RW Byte
Configures how the controller responds when power is
applied
WRITE_PROTECT
Y
10
RW Byte
Controls writing to the PMBus device to prevent accidental
changes
VOUT_COMMAND
Y
21
RW Word
Causes the converter to set its output voltage to the
commanded value - VID mode
VOUT_MAX
Y
24
RW Word
Sets the upper limit on the output voltage regardless of any
other command
VOUT_MARGIN_HIGH
Y
25
RW Word
Sets the voltage to which the output is to be changed when
the OPERATION command is set to “margin high”
VOUT_MARGIN_LOW
Y
26
RW Word
Sets the voltage to which the output is to be changed when
the OPERATION command is set to “margin low”
IOUT_CAL_OFFSET
Y
39
RW Word Calibration for IOUT reading
OT_FAULT_LIMIT
Y
4F
RW Word Overtemperature fault threshold
OT_WARN_LIMIT
Y
51
RW Word Overtemperature warning threshold
VIN_OV_FAULT_LIMIT
N
55
RW Word Input voltage monitor overvoltage limit
VIN_UV_FAULT_LIMIT
N
59
RW Word Input voltage monitor undervoltage limit
MFR_SPECIFIC_01
N
D1
RW Byte
AVERAGE_TIME_SCALE. Sets the time between two
measurements
MFR_SPECIFIC_02
Y
D2
RW Byte
DEBUG_MODE. [01/10] Switches [ON/OFF] the Vout control
on PMBus domain
MFR_SPECIFIC_05
Y
D5
RW Byte
VOUT_TRIM. Used to apply a fixed offset voltage to the
output voltage command value
MFR_SPECIFIC_08
Y
D8
RW Byte
VOUT_DROOP. Used to change the Vout droop
MFR_SPECIFIC_35
N1
F3
RW Byte
MANUAL_PHASE_SHEDDING. Used to manage the phase
shedding manually
MFR_SPECIFIC_38
Y
F6
RW Byte
VOUT_OV_FAULT_LIMIT. Allows the OV protection threshold
to be programmed for each rail
MFR_SPECIFIC_39
Y
F7
RW Byte
VFDE_ENABLE
MFR_SPECIFIC_40
Y
F8
RW Byte
ULTRASONIC_ENABLE
Command
OPERATION
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PMBus support (preliminary)
Table 16.
L6751B
Supported commands
Per
Rail
Code
[Hex]
Mode
MFR_SPECIFIC_41
N1
F9
RW Byte
GDC_THRESHOLD. To access the internal register to set
GDC threshold [A]
MFR_SPECIFIC_42
N1
FA
RW Byte
DPM12_THRESHOLD. To access the internal register to set
the DPM12 threshold [A]
MFR_SPECIFIC_43
N1
FB
RW Byte
DPM23_THRESHOLD. To access the internal register to set
the DPM23 threshold [A]
MFR_SPECIFIC_44
N1
FC
RW Byte
DPM34_THRESHOLD. To access the internal register to set
the DPM34 threshold [A]
MFR_SPECIFIC_45
N1
FD
RW Byte
DPM46_THRESHOLD. To access the internal register to set
the DPM46 threshold [A]
CAPABILITY
N
19
R Byte
Provides a way for a host system to determine key
capabilities of a PMBus device, such as maximum bus speed
and PMBus alert
VOUT_MODE
N
20
R Byte
The device operates in VID mode
PMBUS_REVISION
N
98
R Byte
Revision of the PMBus which the device is compliant to
MFR_ID
N
99
R Block
Returns the manufacturers ID
MFR_MODEL
N
9A
R Block
Returns manufacturers model number
MFR_REVISION
N
9B
R Block
Returns the device revision number
MFR_SPECIFIC_EXT
ENDED_COMMAND_
00
Y
00
R Byte
VR12_STATUS1
MFR_SPECIFIC_EXT
ENDED_COMMAND_
01
Y
01
R Byte
VR12_STATUS2
MFR_SPECIFIC_EXT
ENDED_COMMAND_
02
Y
02
R Byte
VR12_TEMPZONE
MFR_SPECIFIC_EXT
ENDED_COMMAND_
03
Y
03
R Byte
VR12_IOUT
MFR_SPECIFIC_EXT
ENDED_COMMAND_
05
Y
05
R Byte
VR12_VRTEMP
MFR_SPECIFIC_EXT
ENDED_COMMAND_
07
Y
07
R Byte
VR12_STATUS2_LASTREAD
MFR_SPECIFIC_EXT
ENDED_COMMAND_
08
Y
08
R Byte
VR12_ICCMAX
MFR_SPECIFIC_EXT
ENDED_COMMAND_
09
Y
09
R Byte
VR12_TEMPMAX
Command
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Comments
Doc ID 024028 Rev 1
L6751B
Table 16.
PMBus support (preliminary)
Supported commands
Command
Per
Rail
Code
[Hex]
Mode
MFR_SPECIFIC_EXT
ENDED_COMMAND_
10
Y
0A
R Byte
VR12_SRFAST
MFR_SPECIFIC_EXT
ENDED_COMMAND_
11
Y
0B
R Byte
VR12_SRSLOW
MFR_SPECIFIC_EXT
ENDED_COMMAND_
12
Y
0C
R Byte
VR12_VBOOT
MFR_SPECIFIC_EXT
ENDED_COMMAND_
13
Y
0D
R Byte
VR12_VOUTMAX
MFR_SPECIFIC_EXT
ENDED_COMMAND_
14
Y
0E
R Byte
VR12_VIDSETTING
MFR_SPECIFIC_EXT
ENDED_COMMAND_
15
Y
0F
R Byte
VR12_PWRSTATE
MFR_SPECIFIC_EXT
ENDED_COMMAND_
16
Y
10
R Byte
VR12_OFFSET
CLEAR_FAULTS
N
03
READ_VIN
N
88
R Word
Returns the input voltage in volts (VIN pin)
READ_VOUT
Y
8B
R Word
Returns the actual reference used for the regulation in VID
format
READ_IOUT
Y
8C
R Word
Returns the output current in amps
N1
94
R Word
Returns the duty cycle of the devices main power converter in
percentage
MFR_SPECIFIC_04
Y
D4
R Word
READ_VOUT. Returns the actual reference used for the
regulation in volts for LINEAR format
READ_TEMPERATUR
E_1
Y
8D
R Word
READ_TEMPERATURE. [DegC]
STATUS_BYTE
Y
78
R Byte
One byte with information on the most critical faults
STATUS_WORD
Y
79
R Word
Two bytes with information on the units fault condition
STATUS_VOUT
Y
7A
R Byte
Status information on the output voltage warnings and faults
STATUS_IOUT
Y
7B
R Byte
Status information on the output current warnings and faults
STATUS_TEMPERATU
RE
Y
7D
R Byte
Status information on the temperature warnings and faults
STATUS_CML
Y
7E
R Byte
Status information on the units communication, logic and
memory
READ_DUTY_CYCLE
Comments
Send Byte Used to clear any fault bits that have been set
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PMBus support (preliminary)
Table 16.
Supported commands
Command
STATUS_INPUT
STATUS_MFR_SPECI
FIC
Note:
12.1
L6751B
Per
Rail
Code
[Hex]
Mode
N1
7C
R Byte
Status information on the input warning and fault
Y
80
R Byte
Manufacturer specific status
1
Applies to multi-phase only.
2
Applies to single-phase only.
Comments
Enabling the device through PMBus
The default condition for the L6751B is to power up through the EN pin ignoring PMBus
commands. By properly setting the ON_OFF_CONFIG command, it is also possible to let
the device ignore the EN pin acting only as a consequence of the OPERATION command
issued.
12.2
Controlling Vout through PMBus
Vout can be set independently from SetVID commands issued through the SVI interface by
using PMBus. Two main modes can be identified as:
–
Offset above SVI commanded voltage.
By enabling the MARGIN mode through the OPERATION command and by
commanding the MARGIN_HIGH and MARGIN_LOW registers, it is possible to
dynamically control an offset above the output voltage commanded through the
SVI bus.
–
Fixed Vout regardless of SVI.
It is necessary to enter DEBUG_MODE. In this condition, commands from SVI are
acknowledged but not executed and VOUT_COMMAND controls the voltage
regulated on the output.
The L6751B can enter and exit DEBUG_MODE anytime. Upon any transition, Vout
remains unchanged and only the next-coming command affects the output voltage
positioning (i.e. when exiting DEBUG_MODE, returning to SVI domain, output
voltage remains unchanged until the next SetVID command).
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L6751B
PMBus support (preliminary)
Figure 17. Device initialization: PMBus controlling Vout
VCC5
VDRV
UVLO
2mSec POR
UVLO
UVLO
VIN
50uSec
EN
ENVTT (Ignored by ON_OFF_Config setting)
SVI BUS
Command ACK but not executed
PMBus
Command Rejected
SVI Packet
ON-OFF_Config
Operation
V_SinglePhase
64uSec
SVRRDY
V_MultiPhase
64uSec
VRRDY
AM14848v1
12.3
Input voltage monitoring (READ_VIN)
The dedicated PMBus command allows the user to monitor input voltage. By connecting the
VIN pin to the input voltage with the recommended resistor values, the L6751B returns the
value of the input voltage measured as a voltage (linear format, N=-4).
The divider needs to be programmed to have 1.24 V on the pin when VIN=15.9375 V.
According to this, RUP=118.5 kΩ and RDOWN=10 kΩ.
Errors in defining the divider lead to monitoring errors accordingly.
Filter VIN pin locally to GND to increase stability of the voltage being measured.
12.4
Duty cycle monitoring (READ_DUTY)
The dedicated PMBus command allows the user to monitor duty cycle for multi-phase with
the aim of calculating input current inexpensively (no need for input current-sense resistors).
By connecting the PHASE pin to the phase1 PHASE pin, the L6751B returns the value of
the duty cycle as a percentage (linear format, N=-2).
The divider needs to be programmed to respect absolute maximum ratings for the pin (7
Vmax). According to this, RUP=5.6 kΩ and RDOWN=470 Ω.
Doc ID 024028 Rev 1
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PMBus support (preliminary)
12.5
L6751B
Output voltage monitoring (READ_VOUT)
The dedicated PMBus command allows the user to monitor output voltage for both sections.
The L6751B returns the value of the programmed VID in VID LSBs (i.e. number of LSBs.
C8h = 200 dec x 5 mV = 1.000 V).
12.6
Output current monitoring (READ_IOUT)
The dedicated PMBus command allows the user to monitor output current for both sections.
The L6751B returns the value of the delivered current by reading IMON voltage (same as
VR12 register 15h) in Amperes (linear format, N=0).
12.7
Temperature monitoring (READ_TEMPERATURE)
The dedicated PMBus command allows the user to monitor the temperature of the power
section for multi-phase. The L6751B returns the value of the temperature sensed by NTC
connected on the TM/STM pin (same as VR12 temperature zone) in degrees Celsius (linear
format, N=0).
12.8
Overvoltage threshold setting
The dedicated MFR_SPECIFIC command allows specific threshold for multi-phase and
single-phase sections to be programmed.
The threshold can be programmed according to Table 17. Different thresholds can be
configured for multi-phase and single-phase sections.
Table 17.
OV threshold setting
Data byte [Hex]
OC threshold [mV] (above programmed VID)
00h
+175 mV (default)
01h
+225 mV
02h
+275 mV
03h
+325 mV
This product is subject to a limited license from Power-One, Inc. related to digital power technology patents owned by Power-One,
Inc. This license does not extend to stand-lone power supply products.
54/58
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L6751B
13
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
Table 18.
L6751B VFQFPN68 8x8 mm mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0
0.02
0.05
b
0.15
0.20
0.25
D
7.90
8.00
8.10
E
7.90
8.00
8.10
D2
4.60
4.70
4.80
E2
4.60
4.70
4.80
e
0.40
L
0.35
K
0.20
0.45
aaa
0.10
bbb
0.10
ccc
0.10
Doc ID 024028 Rev 1
0.55
55/58
Package mechanical data
L6751B
Figure 18. L6751B VFQFPN68 8x8 mm drawing
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L6751B
14
Revision history
Revision history
Table 19.
Document revision history
Date
Revision
07-Dec-2012
1
Changes
Initial release.
Doc ID 024028 Rev 1
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L6751B
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