L9348-TR

L9348 QUAD LOW SIDE DRIVER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ SUPPLY VOLTAGE RANGE: 4.8 TO 18V OUTPUT VOLTAGE UP TO 40V OUTPUT VOLTAGE CLAMP DURING RECIRCULATION OF INDUCTIVE LOADS OUTPUT CURRENT CAPABILITY 2 X 5A AND 2 X 3A LOW POWER DISSIPATION DURING RECIRCULATION OF INDUCTIVE LOADS BY INTEGRATED FREE WHEELING DIODES (3A-DRIVERS ONLY) LOW ON-RESISTANCE 2 X 0.2 , 2 X 0.35 (TYP.) OUTPUT SHORT CIRCUIT CURRENT PROTECTION REAL TIME DIAGNOSTIC FUNCTIONS OVERTEMPERATURE SHUTDOWN SIGNAL- AND POWER-GROUND-LOSS SHUTDOWN PowerSO-36 BARE DIE ORDERING NUMBERS: L9348 L9348-DIE1 3.3V CMOS COMPATIBLE INPUTS AND STATUS ■ DESCRIPTION The L9348 is a monolithic integrated quad low side driver realized in advanced Multipower-BCD technology. It is intended to drive inductive loads (relays, electromagnetic valves) in automotive and industrial applications. Figure 1. Block Diagram VS Voltage Regulator VS + VREG – VDD C 166kHz = VCC EN Q1 VS VDD IN1 EN ≥1 FAIL Diagnostic OL VREG SCP PGND1 TSD 5A - DRIVER GL ST1 CHANNEL1 PWRES IN2 C 166kHz ST2 EN CHANNEL2 PWRES ENA VDD EN PWRES C 166kHz PWRES C 166kHz EN D3 Q3 VS VDD Q2 PGND2 VS IN3 EN ≥1 Diagnostic FAIL VREG OL SCP PGND3 TSD 3A - DRIVER GL ST3 FB CHANNEL3 PWRES IN4 C 166kHz ST4 PWRES 99AT0073 September 2013 D4 EN CHANNEL4 Q4 PGND4 GND 1/13 L9348 Figure 2. Pin Connection N.C. PGND3 Q3 D3 Q1 Q2 D4 Q4 PGND4 N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 99AT0074 Table 1. Pin Description N° Pin 1, 18, 19, 36 N.C. Function 2, 3 PGND3 4, 5 Q3 Power Output Channel 3 (3A switch) 6, 7 D3 Recirculation Diode Channel 3 8, 9 Q1 Power Output Channel 1 (5A switch) 10, 11 Q2 Power Output Channel 2 (5A switch) (GND) Power Ground Channel 3 12, 13 D4 Recirculation Diode Channel 4 14, 15 Q4 Power Output Channel 4 (3A switch) 16, 17 PGND4 Power Ground Channel 4 20 ST4 Status Output Channel 4 21 IN2 Control Input Channel 2 22 IN4 Control Input Channel 4 23 ST2 Status Output Channel 2 24 ENA Enable 25, 26 PGND2 27 GND Signal Ground 28 VS Supply Voltage 29 N.C. Not Connected 30, 31 PGND1 Power Output Channel 3 32 ST1 Status Output Channel 1 33 IN3 Control Input Channel 3 34 IN1 Control Input Channel 1 2/13 Power Ground Channel 2 N.C. ST3 IN1 IN3 ST1 PGND1 N.C. VS GND PGND2 ENA ST2 IN4 IN2 ST4 N.C. L9348 Table 2. Thermal Data Values Symbol Parameter Test Conditions Unit Min. Tj Junction temperature Tjc Junction temperature during clamping (life time) Tstg Storage temperature Typ. Max. -40 t = 30min t = 15min -55 150 °C 175 190 °C °C 150 °C 2 °C/W Rth j-case Thermal resistance junction to case Table 3. Absolute Maximum Ratings The absolute maximum ratings are the limiting values for this device. Damage may occur if this device is subjected to conditions which are beyond these values. Symbol Parameter Test Conditions Value Unit -0.3 to 40 V Voltages Supply voltage range VS VQ, VD max. static Output voltage VIN, VEN Input voltage range (IN1 to IN4, EN) 40 V |II | < 10mA -1.5 to 6 V -0.3 to 6 V 55 V VST Status output voltage range |II | < 1mA VDRmax max. Reverse breakdown voltage free wheeling diodes D3, D4 IR = 100 A Currents IQ 1/2 Output current at reversal supply for Q1, Q2 -4 A IQ 3/4 Output current at reversal supply for Q3, Q4 -2 A IST Status output current range EQ1/2 max. Discharging energy for inductive loads per channel Q1, Q2 IFDmax max. load current free wheeling diodes -1 to 1 mA Tj = 25°C 50 mJ Tj = 150°C 30 mJ t < 5ms 3 A ESD Protection Supply and Signal pins Output pins (QX, DX) versus GND 2 kV versus common ground (=short of SGND with all PGND) 4 kV Note: Human Body Model according to MIL883C. The device withstands ST1 class level. Table 4. Operating Range. Symbol Parameter Test Conditions Values Min. Typ. Max. Unit VS Supply voltage 4.8 18 V Tj Junction temperature -40 150 °C 3/13 L9348 Table 5. Electrical Characteristcs The electrical characteristics are valid within the operating range (Table 4), unless otherwise specified Symbol Parameter Test Condition Min. Typ. Max. Unit Power Supply IS Supply current VIN1...IN4, ENA = H 8 mA IQ Quiescent current (outputs OFF) VENA = L 6 mA Quiescent current at pins D3/4 VD3/4  18V; VIN3/4 = L 10 400 A VQU1 to 4 Output open load voltage threshold VS  6.5V VEN = X; VIN = L 0.3 0.36 x VS IQU1 to 4 Output open load current threshold VS  6.5V VEN = H; VIN = H 50 140 mA IQO1/2 Overload current threshold Q 1, 2 VS  6.5V 5 7.5 9 A IQO3/4 Overload current threshold Q 3, 4 VS  6.5V 3 5 8 A Tth Overtemperature shutdown threshold 2) 210 °C Thy Overtemperature hysteresis VthPGL Power-GND-loss threshold 1.5 2.5 3.5 V VthSGL Signal-GND-loss threshold 150 330 510 mV ID3/4 Diagnostic Functions 0.33 175 10 °C Power Outputs (Q1 to Q4) RDSON1/2 Static drain-source ON-resistance Q1, Q2 RDSON3,4 Static drain-source ON-resistance Q3, Q4 IQ = 1A; VS  9.5V Tj = 25°C  0.2 Tj = 125°C 3) 0.5  Tj = 150°C 4) 0.5  IQ = 1A; VS  9.5V Tj = 25°C  0.35 Tj = 125°C 3) 0.75  Tj = 150°C 4) 0.75  VZ Z-diode clamping voltage = threshold of flyback detection Q3/4 IQ  100mA, pos. supply VD3/4 45 60 V VC Clamping voltage IQ  100mA, neg. supply VD3/4 4 10 V IPD Output pull down current VENA = H, VIN = L 10 50 A 4/13 20 L9348 Table 5. Electrical Characteristcs The electrical characteristics are valid within the operating range (Table 4), unless otherwise specified Symbol IQlk Parameter Output leakage current Test Condition Min. Typ. Max. Unit VENA = L,Tj = 25°C 1 A Tj = 125°C 5 A VFD3/4 Forward voltage of free wheeling diodes D3, D4 ID3/4 = -1.5A 0.5 1.75 V RPD0 Gate pull down resistor for nonsupplied VS VS  0V, VD3/4  6.5V 0.3 3 k Output ON delay time IQ = 1A 1) 0 5 20 s Output ON fall time IQ = 1A 1) 0.5 1.5 8 s Output OFF delay time IQ = 1A 1) 0 10 30 s Output OFF rise time IQ = 1A 1) 0.5 1.5 5 s 6 30 65 s 0.75 1.5 2.25 ms 5.8 35 s 20 70 s Timings tON tf tOFF tr tDSO tD tfilter tOLOFF Overload switch-OFF delay time Output OFF status delay time error detection filter time 2) OLOFF error detection filter time Digital Inputs (IN1 to IN4, ENA) VIL Input low voltage -1.5 1 V VIH Input high voltage 2 6 V VIHy Input voltage hysteresis 2) IIN Input pull down current 50 100 VIN = 5V, VS  6.5V 8 20 IST  40A mV 40 A 0 0.4 V IST  -40A 2.5 3.45 V IST  -120A 2 3.45 V Digital Outputs (ST1 to ST4) VSTL Status output voltage in low state 5) VSTH Status output voltage in high state 5) RDIAGL ROUT + RDSON in low state 0.3 0.64 1.5 k RDIAGH ROUT + RDSON in high state 1.5 3.2 7 k (1).See chapter 2.0 Timing Diagrams; resistive load condition; VS  9V (2).This parameter will not be tested but assured by design (3).Wafer-measurement (4).Measured on P-SO36 devices (5).Short circuit between two digital outputs (one in high the other in low state) will lead to the defined result "LOW" 5/13 L9348 1.0 FUNCTIONAL DESCRIPTION 1.1 Overview The four low-side switches are designed to drive inductive loads (relays, electromagnetic valves). For the 3A switches (Q3/4) integrated free-wheeling diodes (D3/4) are available and can be used as recirculation path for inductive loads. If either integrated nor external free-wheeling diodes are used the output voltage is clamped internally during discharge of inductive loads. The switches are controlled by CMOS compatible inputs (IN1-4) if the enable input is set to “high”. The status of each switch is monitored by the related status output (ST1-4). 1.2 Input Circuits The control and enable inputs are active high, featuring switching thresholds with hysteresis and pull-down current sources. Not connected inputs are interpreted as “LOW”. If the enable input is set to “LOW” the outputs are switched off independent of the control input state (IN1-4). 1.3 Switching Stages The four power outputs consist of DMOS-power transistors. The output stages are protected against short circuit to supply. Integrated output voltage clamp limits the output voltage in case of inductive load current flyback. Internal pull down current sources are provided at the outputs to assure a defined conditon in OFF mode. They will be disconnected in the disable mode (ENA=L). If the supply of the device gets lost but the loads and D3/4 are still supplied, an internal pull down resistor discharges the gate of the DMOS-power transistor to avoid switch on due to capacitive coupling. 1.4 Status Outputs The CMOS compatible status outputs indicate the state of the drivers (LOW-level indicates driver in OFF state, HIGH-level indicates driver in ON state). If an error occurs the status output voltage changes like described in chapter 1.6 Error Detection. 1.5 Protective Circuits The outputs are protected against current overload, overtemperature, and Power-GND-loss. 1.6 Error Detection Two main error types are distinguished in the diagnostic logic. If current overload, overtemperature, signalGND-loss or a power-GND-loss occurs, the status output signal is inverted, an internal register is set and the driver is shutdown. The reset is done by switching off the corresponding control input or the enable input for at least the time tD (defined to 1.5ms typ.). See also Figure 6 in chapter 2.0 Timing Diagrams. All other errors (openload, active output voltage clamp) only cause an inverted status output signal but no shutdown of the driver. An internal register is set too, but the reset is triggered automatically after the time tD, if the error condition is no longer valid (see Figure 7 and Figure 8). Excepting the detection of the active output voltage clamp all errors are digitally filtered before they are interpreted by the diagnostic logic. The table 6 below shows the different failure conditions monitored in ON and OFF state: Table 6. ON State ENA = HIGH, IN = HIGH Overloading of output (also shorted load to supply) Open load (under voltage detection) 6/13 OFF State ENA = HIGH, IN = LOW X X typ. Filter time Reset done by 18s ENA or INx = “LOW” for t 1.5ms (typ.) 44s internal timer (1.5ms typ.) L9348 Table 6. ON State ENA = HIGH, IN = HIGH OFF State ENA = HIGH, IN = LOW typ. Filter time Reset done by Open load (under current detection) X 18s internal timer (1.5ms typ.) Overtemperature X 18s ENA or INx = “LOW” for t 1.5ms (typ.) Power-GND-loss X X 18s ENA or INx = “LOW” for t 1.5ms (typ.) Signal-GND-loss X X 18s ENA or INx = “LOW” for t 1.5ms (typ.) X - Output voltage clamp active (Q3/4 only) 1.7 internal timer (1.5ms typ.) Diagnostic Output at Pulse Width Operation (PWM) If an input is operated with a pulsed signal (f tD = 667 Hz typ.), the status does not follow each single pulse. An internal delay tD of typ. 1.5ms leads to a continuous status output signal (see Figure 4 in chapter 2.0 Timing Diagrams). 1.8 Diagnostic Table In general the diagnostic follows the input signal in normal operating conditions. If any error is detected the diagnostic is inverted. Table 7. Operating Condition Enable Input ENA Control Input IN Power Output Q Status Output ST Normal function L L H H L H/PWM L H/PWM OFF OFF OFF ON L L L H Open load or short to ground L L H H L H/PWM L H/PWM OFF OFF OFF ON X X H L H H H –> L H H/PWM H/PWM X H/PWM –> L OFF OFF OFF OFF L L L L H H H –> L H H/PWM H/PWM X H/PWM –> L OFF OFF OFF OFF L L L L Overload or short to supply Latched overload Reset latch Overtemperature Latched overtemperature Reset latch 7/13 L9348 2.0 TIMING DIAGRAMS Figure 3. Output slope with Resistive Load VIN t tON tf tOFF tr VQ 100% V Q 85% V Q 15% V Q t note: parameters are not shown proportionally 99AT0061 Figure 4. Diagnostic Output at PWM operation VIN t IQ IQU t VST tD tD t delayed status signal 99AT0063 8/13 note: parameters are not shown proportionally L9348 Figure 5. Overload Detection VIN t overload detected IQ IQO driver shut down IQU t tDSO tfilter VST error condition signalized t note: parameters are not shown proportionally 99AT0062 Figure 6. Driver Shut Down in Case of Overload VIN t tD driver is shuted down and locked driver is now free again IQ IQO t VST tD error is signalized 99AT0064 t note: parameters are not shown proportionally 9/13 L9348 Figure 7. Under Current Condition VIN t IQ IQU t tfilter under current condition detected VST tD under current condition signalized t status signal is changed by internal reset 99AT0065 note: parameters are not shown proportionally Figure 8. Open Load Condition in Off State VIN t VQ VQU tdetection tOLOFF tdetection t tOLOFF openload condition detected but not signalized due to: tdetection < t OLOFF openload condition detected and signalized due to: tdetection > t OLOFF VST tD 99AT0066 10/13 note: parameters are not shown proportionally t L9348 Figure 9. Output Voltage Clamp Detection VIN3/4 t VQ3/4 VZ t VST3/4 tclamp tclamp t time between two clamping periods is shorter than internal delay time -> status signal remains low tD note: parameters are not shown proportionally 99AT0067 3.0 PAD POSITIONS Chip Size: 5.17 x 2.76 mm2 Figure 10. PGND4 ST4 Q4 IN2 D4 IN4 ST2 Q2 ENA PGND2 Q1 GND VS D3 PGND1 Q3 ST1 IN3 PGND3 IN1 ST3 11/13 L9348 DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.60 0.10 0.30 a2 MAX. 0.1417 0.0039 0.0118 3.30 0.1299 a3 0 0.10 b 0.22 0.38 0.0087 0.0150 c 0.23 0.32 0.0091 0.0126 D 15.80 16.00 0.6220 0.6299 D1 9.40 9.80 0.3701 E 13.90 14.5 0.5472 0.5709 E1 10.90 11.10 0.4291 0.4370 E2 E3 e 6.20 0.3858 0.1142 0.2283 0.65 e3 0 H 15.50 h 0.4350 0.10 0.0039 15.90 0.6102 1.10 0.8 0.2441 0.0256 11.05 G L 0.0039 2.90 5.80 OUTLINE AND MECHANICAL DATA 1.10 0.6260 0.0433 0.0315 N 10˚ (max) s 8˚ (max) 0.0433 PowerSO-36 Note: “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions are "a3", "E" and "G". 0096119 C 12/13 L9348 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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