L9935

® L9935 TWO-PHASE STEPPER MOTOR DRIVER 2 X 1.1A FULL BRIDGE OUTPUTS INTEGRATED CHOPPING CURRENT REGULATION MINIMIZED POWER DISSIPATION DURING FLYBACK OUTPUT STAGES WITH CONTROLLED OUTPUT VOLTAGE SLOPES TO REDUCE ELECTROMAGNETIC RADIATION SHORT-CIRCUIT PROTECTION OF ALL OUTPUTS ERROR-FLAG FOR OVERLOAD, OPEN LOAD AND OVERTEMPERATURE PREALARM DELAYED CHANNEL SWITCH-ON TO REDUCE PEAK CURRENTS MAX. OPERATING SUPPLY VOLTAGE 24V STANDBY CONSUMPTION TYPICALLY 40µA SERIAL INTERFACE (SPI) PowerSO20 ORDERING NUMBER: L9935 DESCRIPTION The L9935 is a two-phase stepper motor driver circuit suited to drive bipolar stepper motors. The device can be controlled by a serial interface (SPI). All protections required to design a well protected system (short-circuit, overtemperature, cross conduction etc.) are integrated. BLOCK DIAGRAM GND 1 20 GND ~ 19 SRA OUTA1 2 DRIVER LOGIC 18 OUTA2 N.C. VS 17 16 SCK 3 SDI SDO VCC CSN EN 4 OSCILLATOR 5 6 7 8 COMMON LOGIC DIAGNOSTIC 15 OSC 14 BIASING C DRV OUTB1 9 DRIVER LOGIC 13 OUTB2 12 SRB GND GND 10 ~ 11 D99AT415 November 1999 1/19 L9935 PIN CONNECTION GND OUTB1 EN CSN VCC SDO SDI SCK OUTA1 GND 10 9 8 7 6 5 4 3 2 1 D99AT416 11 12 13 14 15 16 17 18 19 20 GND SRB OUTB2 CDRV OSC VS N.C. OUTA2 SRA GND PIN FUNCTIONS Pin No 1,10,11,20 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 Name GND OUTA1 SCK SDI SDO VCC CSN EN OUTB1 SRB OUTB2 CDRV OSC VS NC OUTA2 SRA Output 1 of full bridge 1 Clock for serial interface (SPI) Serial data input Serial data output 5V logic suplly voltage Chip select (Low active) Enable (Low active) Output 1 of full bridge 2 Cyrrent sense resistor of the chopper regulator for OUTB Output 2 of full bridge 2 Charge pump buffer capacitor Oscillator capacitor or external clock Supply voltage Not connected Output of full bridge 1 Current sense resistor of the chopper regulator for OUTA Description Ground. (All ground pins are internally connected to the frame of the device). 2/19 L9935 ABSOLUTE MAXIMUM RATINGS Symbol VS VSPulsed VOUT (Ai/Bi) Parameter DC Supply Voltage Pulsed supply voltage T < 400ms Output Voltages Value -0.3 to 35 -0.3 to 40 internally clamped to VS or GND depending on the current direction ±1.2 ±2.5 -0.3 to 6.2 -0.3 to 6.2 -0.3 to 10 -2 to 8 -0.3 to VCC +0.3 Unit V V IOUT (Ai/Bi) VSRA/SRB VCC V CDRV VSCK, VSDI, VCSN, VEN VOSC, VSDO DC Output Currents Peak Output Currents (T/tp ≥ 10) Sense Resistor Voltages Logic Supply Voltages Charge Pump Buffer Voltage versus VS Logic Input Voltages Oscillator Voltage Range, Logic Output A A V V V V V Note: ESD for all pins, except pins SDO, SRA and SRB, are according to MIL883C, tested at 2kV, corre sponding to a maximum energy dissipation of 0.2mJ. SDO, SRA and SRB pins are tested with 800V. THERMAL DATA Symbol Rth j-case Rth j-amb Rth j-amb, FR4 Parameter Typical Thermal Resistance Junction to Case Typical Thermal Resistance Junction to Ambient (6cm2 Ground Plane 35µm Thhickness) Typical Thermal Resistance Junction to Ambient (soldered on a FR 4 board with through holes for heat transfer and external heat sink applied) Storage Temperature Typical Thermal Shut-Down Temperature Value 5 35 8 Unit °C/W °C/W °C/W °C °C TS TSD -40 to 150 180 ELECTRICAL CHARACTERISTICS (8V ≤ VS ≤ 24V; -40°C ≤ Tj ≤ 150 °C; 4.5V ≤ VCC ≤ 5.5V, unless otherwise specified.)1) Symbol SUPPLY IS85 Total Supply Current IS + IVCC (Both Bridges Off) Operating Supply Current VS = 14V EN = HIGH TJ ≤ 85°C IOUT Ai/Bi = 0 fOSC = 30kHz VS = 14V EN = LOW Current bit combinations LL, LH, VS ≥ 12V Current bit Combinations LL, LH, VS = 8V EN = HIGH IFWD = 1A; VS ≥ 12V EN = LOW IREV = 1A 0.1...0.9 VOUT VS = 14V Chopping 550mA 0.3 40 100 µA Parameter Test Condition Min. Typ. Max. Unit ISOP 4.5 mA ICC ROUT, Sink ROUT, Source ROUT8, Sink 5V Supply Current RDSON of Sink Transistors RDSON of Source Transistors RDSON of Sink Transistors + RDSON of Source Transistors Forward Voltage of the DMOS Body Diodes Reverse DMOS Voltage Rise and Fall Time of Outputs OUTAi/Bi 1.4 0.4 0.4 1.6 10 0.7 0.7 3 mA Ω Ω Ω FULL BRIDGES VFWD VREV t r, t f 1 0.5 0.6 1.4 0.9 1.5 V V µs 3/19 L9935 ELECTRICAL CHARACTERISTICS (continued) Symbol VSRHL VSRLH VSRLL VEN High VEN low VEN Hyst IEN High IEN Low VHIGH VLOW VHyst IHIGH Parameter Voltage Drops Across R1 ⋅ R 2 2) (Voltage at Pin SRA or SRB vs. GND) Test Condition Bit 5, 2 = H Bit 5, 2 = L Bit 4, 1 = L Bit 4, 1 = H Min. 12 160 270 VCC -1.2V 1.2 0.1 VHigh = VCC VLOW = 0V EN = LOW -10 -3 2.6 -0.3 0.8 VHigh = VCC VLow = 0V ISDO = -1mA ISDO = 1mA EN = LOW EN = LOW COSC = 1nF EN = High → Low 2.2 1 45 20 2/fosc 160 130 10 -10 -3 VCC -1 1.2 0 -10 VCC -0.17 0.17 2.46 1.23 62 25 5/fosc 180 160 20 30 0 -10 10 -30 8 1 1.6 10 -30 VCC 1 2.6 1.4 80 31 8/fosc 200 °C °C K Typ. 20 180 300 Max. 35 210 340 Unit mV mV mV V V V µA µA V V V µA µA V V V V µA kHz SWITCH OFF THRESHOLD OF THE CHOPPER (R 1 ⋅ R2 = 0.33Ω) Bit 5, 4, 2, 1 = L ENABLE INPUT EN High Input Voltage Low Input Voltage Enable Hysteresis High Input Current Low Input Current High Input Voltage Low Input Voltage Hysteresis High Input Current LOGIC INPUTS SDI. SCK, CSN Low Input Current ILow LOGIC OUTPUTS (SDO) VSDO,High VSDO,Low VOSC, H VOSC, L IOSC fOSC tStart TJ-OFF TJ-ALM ∆TMGN High Output Voltage Low Output Voltage High Peak Voltage Low Peak Voltage Charging/Discharging Current Oscillator Frequency Oscillator Startup Time Thermal Shut-Down Temperature Thermal Prealarm Margin Prealarm/Shut-Down OSCILLATOR THERMAL PROTECTION 1) Parameters are tested at 125°C. Values at 140°C are guaranteed by design and correlation. 2) Currents of combinations LH and LL are sensed at the external resistors. The Current of bit combination HL is sensed internally and cannot be adjusted by changing the sense resistors. 4/19 L9935 Figure 1. General Application Circuit Proposal. GND 1 20 GND ~ 19 SRA R1 0.33Ω OUTA1 2 DRIVER LOGIC 18 OUTA2 N.C. VS 17 16 SCK 3 SDI INTERFACE SDI SDO CSN 4 OSCILLATOR 5 7 8 6 COMMON LOGIC DIAGNOSTIC 15 OSC COSC 1nF CDriver 100nF CDRV STEPPER MOTOR POWER SUPPLY C2 10µF µC +5V 100nF EN VCC 14 BIASING C1 100nF OUTB1 9 DRIVER LOGIC 13 OUTB2 12 SRB R2 0.33Ω GND GND 10 ~ 11 D99AT417 Application hints: C1 and C2 should be placed as close to the device as possible. Low ESR of C2 is advantageous. Peak currents through C1 and C2 may reach 2A. Care should be taken that the resonance of C1, C2 together with supply wire inductances is not the chopping frequency or a multiple of it. FUNCTIONAL DESCRIPTION Basic structure The L9935 is a dual full bridge driver for inductive Table 1. bit5, bit2 H H L L bit4, bit1 H L H L loads with a chopper current regulation. Outputs A1 and A2 belong to full bridge A Outputs B1 and B2 belong to full bridge B The polarity of the bridges can be controlled by bit0 and bit3 (for full bridge A, bit3, for full bridge B, bit0). Bit5, bit4 (for full bridge A) and bit2, bit1 (for full bridge B) control the currents. Bit3 high leads to output A1 high. Bit0 high leads to output B1 high. Current setting Table 1 using a 0.33W sense resistor. IQX (Typ.) 0 60mA 550mA 900mA IRX/max 0% Remark inernally sensed 61% 100% 5/19 L9935 Figure 2. Typical average load current dependence on RSense. I A 1.8 D99AT418 typical current limitation of high side transistor 1.1 1 0.8 0.6 0.4 0.2 0.075 0 0 limit recommended for usual application suggested range of operation ILL ILH IHL 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 R Ω Full Bridge Function Figure 3. Displays a full bridge including the current sense circuit. VS M11 D11 A1 bit3, (bit0) DRIVE LOGIC D12 D11 D21 A2 M21 D21 M12 D12 LOAD D22 M22 D22 - τ + COMP1 R1 bit5, (bit2) CURRENT LOGIC INHIBIT ON HH CURRENT ADJUST R1 EXTERNAL SENSE RESISTOR bit4, (bit1) D99AT419 6/19 L9935 No current: Bit 5, bit 4 (corresponding bit 2 and bit1 for bridge B) both are HIGH, the current logic will inhibit all drivers D11, D12, D21, D22 turning off M11, M12, M21, M22 independently from the signal of the current sense comparator comp 1. Turning on: Changing bit 5 or bit 4 or both to LOW will turn on either M11 and M22 or M21 and M12 (depending on the phase signal bit 3). Current will start to flow through the load. The current will be sensed by the drop across R1. The threshold of the comparator comp 1 depends on the current settings of bit 5 and bit 4. The current will rise until it exceeds the turn off threshold of comp 1. Chopping: Exceeding the threshold of comp 1 the drive logic will turn off the sink transistor (M12 or M22). The sink transistor periodically is turned on again by the oscillator. Immediately after turning on M12 or M22 the comparator comp 1 will be inhibited for a certain time to blank switch over spikes caused Figure 4. Principal chopper control circuit. MS1 by capacitive load components up to 5 nF. Turning off for example M12 will yield a flyback current through D11. (So now the free wheeling current flows through M21, the load and D11). This leads to a slow current decay during flyback. Maximum duty cycles of more than 85% (at fOSC = 25kHz) are possible. In this case current flows of both bridges will overlap (not shown in Fig. 5). Reversing phase: Suppose the current flowed via M21, the load and M12 before reversing phase. Reversing phase M21 and M12 will be turned off. So now the current will flow through D22, the load and D11. This leads to a fast current decay. Chopper control by oscillator Both chopping circuits work with offset phase. One chopper will switch on the bridge at the maximum voltage of the oscillator while the other chopper will switch on the bridge at minimum voltage of the oscillator. MS1 and MS2 blank switching spikes that could lead to errors of the current control circuit. inhibit + RESET DOMINANT R RES1 RSFF1 S OSC OSCILLATOR COSC S RSFF2 fOSC= iOSC 2.46V · COSC RES2 R RESET DOMINANT Dr2 Comp1 - SRA Dr1 MOS DRIVERS SRB + Comp2 inhibit MS2 D99AT420 7/19 L9935 Figure 5. Pulse diagram to explain offset chopping. VOSC current threshold 1 VSRA current threshold 2 VSRB turn off delay due to slope velocity control total current consumption IVS ∆I D99AT421 Using offset chopping the changes of the supply current remain half as large as using non offset chopping. Turning off the oscillator for example by shorting pin OSC to ground will hinder turning on of the bridges anymore after the comparators have generated a turn off signal. External clocking is possible overdriving the charge and discharge currents of the oscillator for example with a push pull logic gate. So several devices can be synchronized. Protection and Diagnosis Functions The L9935 provides several protection functions and error detection functions. Current limitation usually is customer defined by the external current sense resistors. The current sensed there is used to regulate the current through the stepper motor windings by pulse width modulation. This PWM regulation protects the sink transistors. The source transistors are protected by an internal overcurrent shut down turning off the source transistors in case of overload. Overload detection of the source transistor will turn off the bridge and set the corresponding error flag. To turn on the bridge again a new byte must be written into the interface. (Rising slope of CSN resets the overload error flag). Both bridges use the same flags. To locate which bridge is affected by an error the bridges can be tested individually (One bridge just is turned off to check for the error in the other bridge). Short from an Output to the Supply Voltage VS The current will be limited by the pulse width modulator. The sink transistor will turn off again after some microseconds. The transistor will periodically be turned on again by the oscillator 8 times. After having detected short 8 times the low side transistor will remain off until the next data transfer took place. After detection of a short to VS we suggest to turn off the corresponding bridge to reduce power dissipation for at least 1ms. 8/19 L9935 Diagnosis of a Short to VS During the short current through the sink transistor will rise more rapidly than under normal load conditions. Reaching a peak current of 1.5 times the maximum PWM current between typically 2µs and 5µs after turn on will be detected as a short to VS. Detecting a short the low side transistor will try to turn on again the next 7 trigger pulse of the oscillator. Simultaneously the error flag will updated on each pulse. Figure 6. Normal PWM current versus short circuit current and detection of short to VS.. IQ short threshold PWM threshold t tON tshort tPWM tON tshort tPWM tON tshort tPWM tON tshort tPWM PWM detection signal (internal) Short detection signal (internal) Error 1 ton : turn on of the sink transistor ton + t1 = tshort : activation of short threshold ton + tdelay = tPWM : activation of PWM threshold t t t D99AT422 Between ton and tshort the over current detection is totally blanked. Between tshort and tPWM the current threshold is set to 1.5 times the maximum PWM current (1.5 times the current of current setting LL). Overcurrent now will set the error flag. After tPWM the current threshold is the nominal PWM current set by the external resistor. Exceeding this current will just turn off the sink transistor. This is considered as normal operation. The error flag is detached from the comparator after tPWM so no error flag is set during normal pulse width modulation. Short from an Output to Ground The current through the short will be detected by the protection of the source transistor. The source transistor will turn off exceeding a current of typically 1.8A. Minimum overload detection current is 1.2A. To obtain proper current regulation (by the sink transistors and not by source transistor shut down) the maximum current of the PWM regulator should be set to a maximum value of 1.1A. 9/19 L9935 Diagnosis of a Short to Ground Detecting an overload will set an overcurrent error (Error2 = LOW) (bit6). To reset the error flag a new byte must be written into the interface. (Reset of the error flag takes place at the rising slope of CSN). Shorted Load With a shorted load both, the sink- and the source protection or the PWM alone will respond. In either case there will be no flyback pulse. Diagnosis of a Shorted Load Shorting the load two events may take place: - overload (of the high side transistor) while low side transistor overcurrent is detected will set the following combinations: bit6 = LOW bit7 = HIGH - overload is marginal. So the low side driver may turn off before overload is detected. This leads to the combination bit6 = HIGH and bit7 = LOW. Open Load An open load will not lead to any flyback pulses. Error detection will take advantage of the flyback pulse. Missing the flyback pulse after reversing the polarity of a motor winding bit7 will become LOW. Open load will not be tested in the low current mode (current bits HL) to avoid the risk of instable diagnosis at low flayback currents. Open load immediately after reset or power down may on random be detected in the low current mode too. This diagnosis however will not persist longer than 8 changes of polarity. We strongly suggest to test open load at a high current mode (combination LH or LL). Overtemperature Prealarm Typically 20K before thermal shut down takes place an overtemperature prealarm (bit7 and bit6 low) takes place. Typically overtemperature prealarm temperature is between 150 °C and 160 °C. Application hints using a high resistive stepper motor The L9935 was originally targeted on stepper chopping stepper motor application with typical resistances of 8..12W. Using motors with higher resistance will work too but diagnosis behaviour will slightly change. This paragraph shows the details that should be taken in account using diagnosis for high resistive motors. Startup behaviour: The device has simple digital filter to avoid triggering diagnosis at a single event that could be random noise. This digital filter needs 4 chopping pulses to settle. Using a high resistive motor this chopping does not take place. Instead the digital filter samples each time a polarty change takes place. So the first three response telegrams after reset may show an ’open load’ error. Inpu t data Standby 1st telegram (550mA or 900mA) Reverse phase (550mA or 900mA) Reverse phase (550mA or 900mA) Any data Any data HH XH XH XH HH HH HH HH HH HH High resistive motor (error bits) Low resistive motor (error bits) H means check for HIGH at the error bits. X means don’t care because filter is not yet settled. 10/19 L9935 Using 75mA chopping immediatelly after stand by: The high resistive motor can be forced to chopping operation in the low current range. This leads to the samebehaviour as using a low resistive motor. Short to VS detection using high resistive motors: The short to VS flag is overwritten each time the chopper comparator responds. Having detected a short this flagonly can be reset by reaching chopping operation or resetting the circuit (ENN=1). For a high resistive motor thisleads to the following consequence: Once a short to VS is detected the error flag will persist even if the short is removed again until either a reset (ENN=1) or chopping (for example in 75mA mode) has taken place. We suggest to return to operation once a short to VS was detected by using the low current mode to reset the flag. Limitation of the Diagnosis The diagnosis depends on either detecting an overcurrent of more than typically 1.8A through the source transistor or on not detecting a flyback pulse, or on detecting severe overcurrents of the sink transistor immediately after turn on. Small currents bypassing the load will not be detected. In the low current range (hold current) the flyback pulse (especially commutating against the supply voltage after changing phase) may (depending on the inductivity of the stepper motor windings) be too short to be detected correctly. For this reason diagnosis using the flyback pulse is blanked at phase reversal at hold current. In the low current range (hold current) the current capability of the bridge is reduced on purpose. Short to VS may not be detected. In stead the bridge may just chop like normal operation. Flyback pulse detection is not blanked during PWM regulation at hold current (here commutation voltage is less than 1V thus providing a longer pulse duration.) This however should be taken in account using stepper motors with low inductivity (less than 0.5mH). Using motors with such a low inductivity the flyback voltage in hold mode may decay too fast. Motors with extremely low ohmic resistance tend to pump up the current because current decay during flyback approaches zero while at bridge turn on the current will increase. This may lead to overcurrent detection. We suggest to use stepper motors with an ohmic resistance of approximately 3Ω or more. Partial shorts of windings or shorts of stepper motors with coils in series may still yield a flyback pulses that are accepted by the diagnosis as a proper signal. Table 2. Error table. Error 1 bit7 H L Error 2 bit6 H H Normal operation Short to VS (sink overload immediately after turn on) shorted load (no flyback) open load (no flyback) short to gnd (source overload, missing flyback is masked) overtemperature prealarm Description H L L L At stepping rates faster than 1ms/data transfer error flags indicating a short should be used to initiate a pause of at least 1ms to allow the power bridges to cool down again. 11/19 L9935 Serial Data Interface (SPI) The serial data interface itself consists of the pins SCL (serial clock), SDI (serial data input) and SDO (serial data output). To especially support bus controlled applications the additional signals EN (chip enable not) and CSN (chip select not) are available. Startup of the Serial Data Interface Falling slope of EN activates the device. After ten.sck the device is ready to work. Falling slope of CSN indicates start of frame. Data transfer (reading SDI into the register) takes place at the rising slopes of SCK. Data transfer of the register to SDO takes place at the falling slope of SCK. Rising slope of CSN indicates end of frame. At the end of frame data will only be accepted if modulo 8 bit (modulo 8 falling slopes to SCK) have been transferred. If this is not the case the input will be ignored and the bridges will maintain the same status as before. SDO is a tristate output. SDO is active while CSN = LOW, while CSN = HIGH SDO is high resistive. Figure 7. SPI Data/Clock Timing. ten_sck EN CSN SCK SDI MSB7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 SDO MSB7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ERROR BITS CURRENT A POLARITY A CURRENT B POLARITY B AX tPd CSN t1 SCK tsu tsh SDI td SDO bit7 bit7 bit0 tzch bit0 D99AT437 t1 tcl tch t1 t1 12/19 L9935 Test condition for all propagation times (unless otherwise specified) HIGH ≥ 3V; LOW ≤ 0.8V; t r, tf = 10ns, Enable: ENN Low < 0.8V, ENN High > Vcc -0.8V Symbol fSCLK t1 tch tcl tsu tsh td tzc ten_sck tpd Parameter SCK-Frequency SCK stable before and after CSN = 0 Width of SCK high pulse Width of SCK low pulse SDI setup time SDI hold time SDO delay time (CL = 50pF) SDO high Z CSN high Setup time ENABLE to SCK Propagation delay SPI to output QXX Test Conditions Min. DC 100 200 200 80 80 100 100 HIGH > VCC -1.2V 30 2 (*) Typ. Max. 2MHz Unit ns ns ns ns ns ns ns µs µs (*) Measured at a transition from High impedance (Bridge off) to bridge on. (Reversing polarity takes about 1µs longer because the bridge first turns off before turning on in reverse direction). Table of bits bit5,bit4 : current range of bridge A (Outputs A1 and A2) bit3 : polarity of bridge A bit2,bit1 : current range of bridge B (Outputs B1 and B2) bit0 : polarity of bridge B bit7,bit6 : Error1 and Error 2 Cascading several Devices Cascading several devices can be done using the SDO output to pass data to the next device. The whole frame now consists of n byte. n is the number of devices used. Figure 8. Cascading Several Stepper motor drivers. no.1 SDO SDI SDO SDI no.2 SDO SDI no.3 SDO µP CSN SCK SCK CSN SCK CSN SCK CSN D99AT438 Figure 9. Control sequence for 3 Stepper motor drivers. EN CSN SCK SDO of µP byte for no. 3 byte for no. 2 byte for no. 1 QXX D99AT439 13/19 L9935 Figure 10. Paralleling several Devices. no.1 SDI SDO SDI SCK CSN no.2 SDI SCK CSN SDO SDO µP SCK CSN1 CSN2 D99AT440 here usually only one Stepper motor driver is selected at a time while all others are deselected. Application Information For driving a stepper motor we suggest to use the following codes. The columned ’SDO correct’ shows the data returned at SDO in correct function. The columnes presented under ’Error cases’ display the diagnosis bits if errors are detected. Examples of control sequences Full step mode control sequences and diagnosis response. SDI SDO correct A O P E N B O P E N A1 S H O R T VS 76 A2 S H O R T VS 76 Error cases and SDObit7, bit6 B1 S H O R T VS 76 B2 S H O R T VS 76 A1 *) S H O R T A2 *) S H O R T B1 *) S H O R T B2 *) S H O R T therm. alarm therm. shut down (reset operating codes) bit 76543210 XX111111 XX011011 XX010011 XX010010 XX011010 XX011011 XX010011 XX010010 XX011010 76543210 76 76 GND GND GND GND 76 76 76 76 76 76543210 SDO PRESENT LAST DATA OR 11 11 11 11 11111111 01 11 11 11 11011011 01 01 11 01 11010011 11 01 01 11 11010010 01 01 11 01 11011010 01 11 01 11 11011011 01 01 11 01 11010011 11 01 01 11 11010010 11111111 IN CASE PREV. STATE WAS STAND BY 00111111 00 11 11 11 11 11 11 00111111 00 11 10 11 10 01 11 00111111 00 11 10 10 01 01 11 00111111 00 10 01 10 11 01 01 00111111 00 10 11 01 10 11 01 00111111 00 01 10 11 10 01 01 00111111 00 11 10 10 01 01 11 00111111 00 10 01 10 11 01 01 *) Motor resistance approximatelly 10 Ω and VS = 12V. So a short to ground only is detected on one branche of the bridge. Lower resistivity of the motor may lead to detection of short to ground on both branches of the bridge leading to code 10 on all steps. 14/19 L9935 T hese sequences are intended to give the user a good starting point for his software development. Besides these two there are further possibilities how to implement control sequences for this device (other currents, quarters step etc.). SDI SDO A O P E N B O P E N A1 S H O R T VS 76 11 11 11 11 11 01 01 01 01 01 11 11 01 01 01 01 01 A2 S H O R T VS 76 11 01 01 01 01 01 11 11 11 01 01 01 01 01 11 11 11 B1 S H O R T VS 76 11 11 11 11 11 11 11 01 01 01 01 01 11 11 11 01 01 B2 S H O R T VS 76 11 11 11 11 01 01 01 01 11 11 11 01 01 01 01 01 11 A1 *) S H O R T A2 *) S H O R T B1 *) S H O R T B2 *) S H O R T therm. alarm therm. shut down (reset operating codes) GND GND GND GND 76 11 10 10 10 10 01 11 11 11 11 10 01 10 01 11 11 11 76 11 11 11 11 11 11 10 10 10 01 11 11 11 11 10 10 10 76 11 11 11 11 10 10 10 01 11 11 11 11 10 10 10 01 11 76 11 11 11 11 11 11 11 11 10 10 10 01 11 11 11 11 10 76 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 76543210 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 00111111 bit 76543210 76543210 76 11 11 11 11 11 01 11 11 11 01 11 11 11 01 11 11 11 76 11 11 11 11 11 11 11 01 11 11 11 01 11 11 11 01 11 XX111111 previous code 11111111 XX011111 11011111 XX011111 11011111 XX011111 11011111 XX011011 11011111 XX111011 11011011 XX010011 11111011 XX010111 11010011 XX010010 11010111 XX110010 11110010 XX011010 11011010 XX011110 11011110 XX011011 11011011 XX111011 11111011 XX010011 11010011 XX010111 11010111 XX010010 11010010 XX110010 Double errors: Double errors will create composite codes by an AND operation between columns of the same dominance. Open and short to VS are the least dominant error codes. (first 6 error code columns). Short to ground is the second dominant error code. detection of short to gnd will overwrite error codes of the least dominant kind (open, short to VS). Temperature prealarm and thermal shut down are the most dominant error codes. Thermal prealarm returns error code 00 but the device still is working and returns the appropriate operation code (bits 0..5). Thermal shut down returns error code 00 and turns off the device. The opcode returned corresponds the action eventually performed (bit 0..5 become 1). For example open bridge A and simultaneously open bridge B will lead to error code 01 by performing an AND operation between the two corresponding columns. *) Motor resistance approximatelly 10 Ω and VS = 12V. So a short to ground only is detected on one branche of the bridge. Lower resistivity of the motor may lead to detection of short to ground on both branches of the bridge leading to code 10 on all steps. Electromagnetic Emission classification(EME) Electromagnetic Emission classes presented below are typical data found on bench test. For detailed test description please refer to ’Electromagnetic Emission (EME) Measurement of Integrated Circuits, DC to 1GHz’ of VDE/ZVEI work group 767.13 and VDE/ZVEI work group 767.14 or IEC project number 47A 1967Ed. This data is targetedto boarddesigners to allow an estimation of emission filtering effortrequired in application. Pin GND VCC EN. SDI, CSN, CSK, SDO in tristate SDO Power output A1, A2, B1, B2 Power output A1, A2, B1, B2 E E K G E 5 6 EME class 10 0 e h f f f SDO in low-Z state, no data transfer Sourcing output Sinking output in chopping mode fosc = 20kHz Remark 1Ω test Blocked with 100nF closemto the device Electromagnetic Emission is not tested in production. 15/19 L9935 Figure 11. State diagram. STAND BY DEVICE ON turn on CHECKS FOR ERRORS 11 new telegram no error ON 11 new telegram same polarity new telegram flyback OK short to VS t or sh VS to to or gn t d sh short to gnd new telegram current = 0 or reverse polarity ON CHECKING FLYBACK 6 new telegram missing flyback ON 01 OFF OFF new telegram shor t to VS o sh t rt o gn d shor t to gnd sho rt t og nd new telegram CHECKING FOR ERRORS 10 CHECKING FOR ERRORS 01 no short no short short to VS same polarity as before short to VS LOGIC SELECTS BRANCHE DEPENDING ON PREVIOUS STATE different polar ity than before D99AT441 Remark: Return to stand by is possible from every state Note: Reversing polarity in low current mode no flyback check will be performed. Electromagnetic Emission classification(EME) Electromagnetic Emission classes presentel below are typical data found on bench test. For detailed test description please refer to ’Electromagnetic Emission (EME) Measurement of Integrated Circuits, DC to 1GHz’ of VDE/ZVEI work group 767.13 and VDE/ZVEI work group 767.14 or IEC project number 47A 1967Ed. This data is targeted to board designers to allow an estimation of emission filtering effort required in application. Pin GND VCC EN, SDI, CSN, SCK, SDO in tristate SDO Power output A1, A2, B1, B2 Power output A1, A2, B1, B2 E E K G E 5 6 EME class 10 o e h f f f SDO in low-state, no data transfer Sourcing output Sinking output in chopping mode fOSC = 20kHz 1Ω test Blocked with 100nF close to the device Remark Electromagnetic Emission is not tested in production. 16/19 L9935 Figure 12. EMC Compatibility for L9935 Vbatt 100 H 47nF 47nF100 F Vs Out 1 Out 2 to motors Out 3 Out 4 GND 1/10/ 11/20 4* 2,2nF 17/19 L9935 18/19 L9935 I nformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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