LD39150PU18R

LD39150 Ultra low drop BICMOS voltage regulator Feature summary ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 1.5A Guaranteed output current Ultra low dropout voltage (200mV typ. @ 1.5A load, 40mV typ. @300mA load) Very low quiescent current (1mA typ. @ 1.5A load, 1µA max @ 25°C in off mode) Logic-controlled electronic shutdown Current and thermal internal limit PPAK DPAK ±1.5% Output voltage tolerance @ 25°C Fixed and ADJ output voltages: 1.22V, 1.8V, 2.5V, 3.3V, ADJ. (*see order code) Temperature range: -40 to 125°C Fast dynamic response to line and load changes Stable with ceramic capacitor (see paragraph 7.1, 7.2, 7.3) Available in PPAK, DPAK and DFN8 (4x4mm) DFN8 (4x4 mm) Description The LD39150 is a fast ultra low drop linear regulator which operates from 2.5V to 6V input supply. A wide range of output options are available. The low drop voltage, low noise, and ultra low quiescent current make it suitable for low voltage microprocessor and memory applications. The device is developed on a BiCMOS process which allows low quiescent current operation independently of output load current. Typical application ■ ■ ■ ■ Microprocessor power supply DSPs power supply Post regulators for switching suppliers High efficiency linear regulator Order codes Part numbers DPAK (T&R) LD39150DT12-R LD39150DT18-R LD39150DT25-R LD39150DT33-R LD39150PT18-R LD39150PT25-R LD39150PT33-R LD39150PT-R 1. Available on request PPAK (T&R) DFN (1) LD39150PU12R LD39150PU18R LD39150PU25R LD39150PU33R LD39150PU-R Output Voltage 1.22V 1.8V 2.5V 3.3V ADJ From 1.22 to 5.0V January 2007 Rev. 1 1/19 www.st.com 19 LD39150 Contents 1 2 3 4 5 6 7 Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.1 7.2 7.3 7.4 7.5 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Inhibit input operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 LD39150 Diagram 1 Figure 1. Diagram Block diagram (*) Not present on ADJ Versions 3/19 Pin configuration LD39150 2 Figure 2. Pin configuration Pin connections (top view for DPAK and PPAK, bottom view for DFN) DFN8 (4x4 mm) PPAK DPAK Table 1. Pin description SYMBOL NOTE For fixed versions: to be connected with LDO Output Voltage pins for DFN package and Not Connected on PPAK For adjustable version: Error Amplifier Input pin for VO from 1.22 to 5.0V LDO Input Voltage; VI from 2.5V to 6V, CI=1µF must be located at a distance of not more than 0.5’’ from input pin. LDO Output Voltage pins, with minimum CO=2.2µF needed for stability (also refer to CO vs. ESR stability chart) Inhibit Input Voltage: ON MODE when VINH ≥ 2V, OFF MODE when VINH ≤ 0.3V (Do not leave floating, not internally pulled down/up) Common ground Not Connected PlN N° DFN PPAK DPAK VSENSE/N.C. ADJ 3, 4 6, 7 2 1 5 2 4 1 3 2 1 3 VI VO VINH GND N.C. 8 5 4/19 LD39150 Typical application circuits 3 Typical application circuits (CI and CO Capacitors must be placed as close as possible to the IC pins) Figure 3. LD39150 fixed version with inhibit 1 Figure 4. Inhibit Pin is not internally pulled down/up then it must not be left floating. Disable the device when connected to GND or to a positive voltage less than 0.3V LD39150 adjustable version VO = VREF (1 + R1/R2) 2 Set R2 as close as possible to 4.7KΩ. 5/19 Typical application circuits LD39150 Figure 5. LD39150 DPAK Figure 6. Timing diagram 6/19 LD39150 Maximum ratings 4 Table 2. Symbol VI VINH VO VADJ IO PD TSTG TOP Maximum ratings Absolute maximum ratings Parameter DC Input voltage INHIBIT Input voltage DC Output voltage ADJ Pin voltage Output current Power dissipation Storage temperature range Operating junction temperature range Value -0.3 to 6.5 -0.3 to VI +0.3 (6.5V Max) -0.3 to VI +0.3 (6.5V Max) -0.3 to VI +0.3 (6.5V Max) Internally Limited Internally Limited -50 to 150 -40 to 125 Unit V V V V mA mW °C °C Note: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All values are referred to GND. Thermal Data Parameter Thermal resistance junction-ambient Thermal resistance junction-case PPAK 100 8 DPAK 100 8 DFN (1) 40 10 Unit °C/W °C/W Table 3. Symbol RthJA RthJC 1. With PCB ground plane heatsink. 7/19 Electrical characteristics LD39150 5 Table 4. Electrical characteristics Electrical characteristics (TJ = 25°C, VI = VO+1V, CI = 1µF, CO = 2.2µF, ILOAD = 10mA, VINH = 2V, unless otherwise specified) Parameter Operating input voltage VI = VO+1V, ILOAD = 10mA to 1.5A VO Output voltage tolerance VI = VO+1V to 6V, ILOAD = 10mA to 1.5A TJ = -40 to 125°C Parameter Min. 2.5 -1.5 -3 1.22 VI = VO+1V to 6V VI = VO+1V to 6V, TJ = -40 to 125°C ILOAD = 10mA to 1.5A ILOAD = 10mA to 1.5A, TJ = -40 to 125°C ILOAD = 300mA, TJ=-40 to 125°C ILOAD = 1.5A, TJ = -40 to 125°C ILOAD = 10mA to 1.5A, VINH = 2V TJ = -40 to 125°C VINH = 0.3V VINH = 0.3V, TJ = -40 to 125°C 0.04 0.1 0.06 %/A 0.2 40 200 1 0.4 80 mV 400 2.5 1 µA 5 mA 0.2 Typ. Max. 6 1.5 3 % of VO(NOM) V % % Unit V Symbol VI VREF ∆VO Reference voltage Output voltage LINE regulation Output voltage LOAD ∆VO/∆ILOAD regulation VDROP Dropout voltage (VI - VO) Quiescent current: ON MODE IQ Quiescent current: OFF MODE Short Circuit Protection ISC Inhibit Input Inhibit threshold LOW VINH TD-OFF TD-ON IINH Inhibit threshold HIGH Current limit Current limit Inhibit input current (1) VI = 2.5 to 6V OFF TJ = -40 to 125°C ILOAD = 1.5A, VO = 3.3V ILOAD = 1.5A, VO = 3.3V VI = 6V, VINH = 0 to 6V 0.3 V 2 15 µs 15 ±0.1 ±1 µA Short circuit protection RL = 0 3 A AC Parameters SVR Supply voltage rejection VI = 4.5 ± 1V, VO = 3.3V, ILOAD = 10mA, f = 120Hz f = 1kHz 65 dB 55 100 170 °C Hysteresis 10 µVRMS eN TSHDN Output noise voltage Thermal shutdown OFF BW = 10Hz to 100kHz, CO = 2.2µF, VO = 2.5V 1. Guaranteed by design 8/19 LD39150 Typical performance characteristics 6 Typical performance characteristics (TJ = 25°C, VI = VO+1V, CI = 1µF, CO = 2.2µF, ILOAD = 10mA, VINH = VI, unless otherwise specified) Output voltage vs temperature Figure 8. Dropout voltage vs temperature Figure 7. Figure 9. Dropout voltage vs output current Figure 10. Quiescent current vs supply voltage Figure 11. Quiescent current vs temperature Figure 12. Quiescent current vs temperature 9/19 Typical performance characteristics LD39150 Figure 13. Short circuit current vs temperature Figure 14. Output voltage vs input voltage Figure 15. Stability region vs CO & ESR (at 100kHz) Figure 16. Stability region vs CO & Low ESR (at 100kHz) Figure 17. Load transient Figure 18. Line transient VI = 3.5V, IO = 10mA to 1.5A, CI = 1µF, CO = 2.2µF VI = 3.5V to 5.5V, ILOAD = 10mA, CO = 2.2µF 10/19 LD39150 Application notes 7 7.1 Application notes External capacitors The LD39150 requires external capacitors for regulator stability. These capacitors must be selected to meet the requirements of minimum capacitance and equivalent series resistance (see Figure 15. Figure 16.). The input/output capacitors must be located less than 1cm from the relative pins and connected directly to the input/output ground pins using traces which have no other currents flowing through them. Any good quality of Ceramic or Electrolytic capacitors can be used. 7.2 Input capacitor An input capacitor whose minimum value is 1µF is required with the LD39150 (amount of capacitance can be increased without limit). This capacitor must be located a distance of not more than 1cm from the input pin of the device and returned to a clean analog ground. Any good quality ceramic, tantalum or film capacitors can be used for this capacitor. 7.3 Output capacitor It is possible to use Ceramic or Tantalum capacitors but the output capacitor must meet the requirement for minimum amount of capacitance and E.S.R. (equivalent series resistance) value. A minimum capacitance of 2.2µF is a good choice to guarantee the stability of the regulator. Anyway, other CO values can be used according to the (Figure 15. Figure 16.) showing the allowable ESR range as a function of the output capacitance. This curve represents the stability region over the full temperature and IO range. 7.4 Thermal note The output capacitor must maintain its ESR in the stable region over the full operating temperature range to assure stability. Also, capacitors tolerance and variation with temperature must be kept in consideration in order to assure the minimum amount of capacitance at all times. 7.5 Inhibit input operation The inhibit pin can be used to turn OFF the regulator when pulled down, so drastically reducing the current consumption down to less than 1µA. When the inhibit feature is not used, this pin must be tied to VI to keep the regulator output ON at all times. To assure proper operation, the signal source used to drive the inhibit pin must be able to swing above and below the specified thresholds listed in the electrical characteristics section (VIH VIL). The inhibit pin must not be left floating because it is not internally pulled down/up. 11/19 Package mechanical data LD39150 8 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 12/19 LD39150 Package mechanical data PPAK MECHANICAL DATA mm. DIM. MIN. A A1 A2 B B2 C C2 D D1 E E1 e G G1 H L2 L4 L5 L6 0.6 1 2.8 4.9 2.38 9.35 0.8 6.4 4.7 1.27 5.25 2.7 10.1 1 1 0.023 0.039 0.110 0.193 0.093 0.368 0.031 2.2 0.9 0.03 0.4 5.2 0.45 0.48 6 5.1 6.6 0.252 0.185 0.050 0.206 0.106 0.397 0.039 0.039 TYP MAX. 2.4 1.1 0.23 0.6 5.4 0.6 0.6 6.2 MIN. 0.086 0.035 0.001 0.015 0.204 0.017 0.019 0.236 0.201 0.260 TYP. MAX. 0.094 0.043 0.009 0.023 0.212 0.023 0.023 0.244 inch 0078180-E 13/19 Package mechanical data LD39150 DPAK MECHANICAL DATA mm. DIM. MIN. A A1 A2 B b4 C C2 D D1 E E1 e e1 H L (L1) L2 L4 0.6 4.4 9.35 1 2.8 0.8 1 0.023 6.4 4.7 2.28 4.6 10.1 0.173 0.368 0.039 0.110 0.031 0.039 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 5.1 6.6 0.252 0.185 0.090 0.181 0.397 TYP MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.200 0.260 TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 inch 0068772-F 14/19 LD39150 Package mechanical data DFN8 (4x4) MECHANICAL DATA mm. DIM. MIN. A A1 A3 b D D2 E E2 e L 0.40 0.23 3.90 2.82 3.90 2.05 0.80 0 TYP 0.90 0.02 0.20 0.30 4.00 3.00 4.00 2.20 0.80 0.50 0.60 0.016 0.38 4.10 3.23 4.10 2.30 0.009 0.154 0.111 0.154 0.081 MAX. 1.00 0.05 MIN. 0.031 0 TYP. 0.035 0.001 0.008 0.012 0.157 0.118 0.157 0.087 0.031 0.020 0.024 0.015 0.161 0.127 0.161 0.09 1 MAX. 0.039 0.002 inch 7869653B 15/19 Package mechanical data LD39150 Tape & Reel DPAK-PPAK MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.80 10.40 2.55 3.9 7.9 6.90 10.50 2.65 4.0 8.0 12.8 20.2 60 22.4 7.00 10.60 2.75 4.1 8.1 0.268 0.409 0.100 0.153 0.311 0.272 0.413 0.104 0.157 0.315 13.0 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.2.76 0.417 0.105 0.161 0.319 0.512 MIN. TYP. MAX. 12.992 0.519 inch 16/19 LD39150 Package mechanical data Tape & Reel QFNxx/DFNxx (4x4) MECHANICAL DATA mm. DIM. MIN. A C D N T Ao Bo Ko Po P 4.35 4.35 1.1 4 8 12.8 20.2 99 101 14.4 0.171 0.171 0.043 0.157 0.315 TYP MAX. 330 13.2 0.504 0.795 3.898 3.976 0.567 MIN. TYP. MAX. 12.992 0.519 inch 17/19 Revision history LD39150 9 Table 5. Date Revision history Revision history Revision 1 Initial release. Changes 26-Jan-2007 18/19 LD39150 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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