LDLN015PU18R

LDLN015 150 mA - ultra low noise - high PSRR linear voltage regulator IC Datasheet - production data Description Features             Ultra low noise: 6.3 µVRMS from 10 Hz to 100 kHz Input voltage from 2.1 to 5.5 V Very low quiescent current (35 µA typ. at no load, 70 µA typ. at 150 mA load; 2 µA max. in off mode) Output voltage tolerance: ± 1% at 25 °C 150 mA guaranteed output current Wide range of output voltage from 0.8 V to 3.3 V with 100 mV step Logic-controlled electronic shutdown Compatible with ceramic capacitor (COUT = 0.47 µF) No bypass capacitor is required Internal current and thermal limit Package DFN6 (2 x 2 mm) Temperature range: - 40 °C to 125 °C The LDLN015 is an ultra low noise linear regulator which provides 150 mA maximum current from an input voltage ranging from 2.1 V to 5.5 V with a typical dropout voltage of 86 mV. With its 6.3 µ VRMS noise value in a band from 10 Hz to 100 kHz, the LDLN015 provides a very clean output suitable for ultra sensitive loads. It is stable with ceramic capacitors. High PSRR, low quiescent current and very low noise features make it suitable for low power battery powered applications. Power supply rejection is higher than 90 dB at low frequencies and starts to roll off at 10 kHz. The enable logic control function puts the LDLN015 into shutdown mode allowing a total current consumption lower than 1 µA. The device also includes a short-circuit constant current limiting and thermal protection. Typical applications are noise sensitive loads like ADC, VCO in mobile phones, and personal digital assistants (PDAs). Table 1: Device summary May 2017 Order code Output voltage (V) LDLN015PU10R 1.0 LDLN015PU12R 1.2 LDLN015PU15R 1.5 LDLN015PU18R 1.8 LDLN015PU25R 2.5 LDLN015PU28R 2.8 LDLN015PU30R 3.0 LDLN015PU33R 3.3 DocID022735 Rev 5 This is information on a product in full production. 1/16 www.st.com Contents LDLN015 Contents 1 Application diagram ........................................................................ 3 2 Pin configuration ............................................................................. 4 3 Maximum ratings ............................................................................. 5 4 5 Electrical characteristics ................................................................ 6 Typical performance characteristics ............................................. 8 6 Package information ..................................................................... 12 7 2/16 6.1 DFN6 (2 x 2 mm) package information ........................................... 12 6.2 DFN6 (2 x 2 mm) packing information ............................................. 14 Revision history ............................................................................ 15 DocID022735 Rev 5 LDLN015 1 Application diagram Application diagram Figure 1: Block diagram Figure 2: Typical application circuit DocID022735 Rev 5 3/16 Pin configuration 2 LDLN015 Pin configuration Figure 3: Pin connections (top view) Table 2: Pin description Pin Symbol Name and function 1 IN Input voltage 2 NC Not connected 3 EN Enable input. Set VEN > 0.9 to turn on the device Set VEN < 0.4 to turn off the device 4 GND 5 NC Not connected 6 OUT Output voltage Ground Exposed pad is electrically connected to GND. 4/16 DocID022735 Rev 5 LDLN015 3 Maximum ratings Maximum ratings Table 3: Absolute maximum ratings Symbol VIN Parameter DC input voltage Value Unit -0.3 to 7 V From -0.3 to 4.6 V From -0.3 to VIN + 0.3 V Output current Internally limited mA Power dissipation Internally limited mW VOUT DC output voltage VEN Enable input voltage IOUT PD TSTG Storage temperature range -65 to 150 °C TOP Operating junction temperature range -40 to 125 °C ±3 kV ±300 V ESD Human body model Machine model Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Table 4: Thermal data Symbol Parameter Value Unit RthJA Thermal resistance junction-ambient 105 °C/W RthJC Thermal resistance junction-case 20 °C/W DocID022735 Rev 5 5/16 Electrical characteristics 4 LDLN015 Electrical characteristics TJ = 25 °C, VIN = VOUT(NOM) + 1 V, CIN = COUT = 0.47 µF, IOUT = 1 mA, VEN = VIN, unless otherwise specified. Table 5: Electrical characteristics Symbol VIN VOUT Parameter Test condition Max. Unit 2.1 5.5 V IOUT = 1 mA -1 1 -40 °C < TJ < 125 °C, IOUT = from 1 mA to 150 mA, VIN = VOUT(NOM) + 1 V to 5.5 V -2 2 Operating input voltage VOUT accuracy Min. Typ. % ∆VOUT Static line regulation VOUT + 1 V ≤ VIN ≤ 5.5 V, IOUT = 1 mA 0.005 %/V ∆VOUT Static load regulation IOUT = 1 mA to 150 mA 0.001 %/mA VDROP Dropout voltage (1) IOUT = 150 mA, VOUT > 1.9 V -40 °C < TJ < 125 °C 86 10 Hz to 100 kHz, IOUT = 0 mA, VOUT = 1.0 V 6.3 10 Hz to 100 kHz, IOUT = 150 mA, VOUT = 1.0 V 9.9 VIN = VOUTNOM + 1 V +/-VRIPPLE VRIPPLE = 0.5 V Freq. = 1 kHz IOUT = 10 mA 92 VIN = VOUTNOM + 1 V +/-VRIPPLE VRIPPLE = 0.5 V Freq. = 10 kHz IOUT = 10 mA 89 VIN = VOUTNOM + 1 V+/-VRIPPLE VRIPPLE = 0.5 V Freq. = 100 kHz IOUT = 1 mA 50 IOUT = 0 mA, -40 °C < TJ < 125 °C IOUT = 150 mA, -40 °C < TJ < 125 °C 35 70 60 120 0.002 2 eN SVR IQ Output noise voltage Supply voltage rejection VOUT = 1.0 V Quiescent current 6/16 Short-circuit current RL = 0 VIN = 2.0 V DocID022735 Rev 5 mV µVRMS VIN input current in OFF mode VEN = GND ISC 180 300 dB µA mA LDLN015 Electrical characteristics Symbol Parameter Enable input logic low VIN = 2.1 V to 5.5 V, -40 °C < TJ < 125 °C Enable input logic high VIN = 2.1 V to 5.5 V, -40 °C < TJ < 125 °C Enable pin input current VEN = 5.5 V VEN IEN TON TSHDN COUT Test condition Turn-on time Min. Typ. V 0.9 0.1 100 110 Thermal shutdown 166 Hysteresis 10 Capacitance (see Figure 15: "Stability area") Unit 0.4 (2) Output capacitor Max. 0.33 nA µs °C 4.7 µF Notes: (1)Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply for output voltages below 2 V. (2)Turn-on time is time measured between the enable input just exceeding VEN high value and the output voltage just reaching 95% of its nominal value. Note:   For VOUT(NOM) < 1.0 V, VIN = 2 V All transient values are guaranteed by design, not production tested DocID022735 Rev 5 7/16 Typical performance characteristics 5 8/16 LDLN015 Typical performance characteristics Figure 4: Output voltage vs temperature Figure 5: Output voltage vs input voltage VOUT = 1 V Figure 6: Output voltage vs input voltage VOUT = 3.3 V Figure 7: Dropout voltage vs temperature Figure 8: Dropout voltage vs IOUT Figure 9: Quiescent current vs temperature DocID022735 Rev 5 LDLN015 Typical performance characteristics Figure 10: Quiescent current vs IOUT Figure 11: Quiescent current vs VIN Figure 12: Supply voltage rejection vs frequency Figure 13: Supply voltage rejection vs IOUT Figure 14: Noise spectral density Figure 15: Stability area DocID022735 Rev 5 9/16 Typical performance characteristics LDLN015 Figure 16: Load transient Figure 17: Line transient at IOUT = 1 mA Figure 18: Line transient at IOUT = 150 mA Figure 19: Turn-on time at IOUT = 1 mA; VOUT = 1 V Figure 20: Turn-on time at IOUT = 150 mA, VOUT = 1 V Figure 21: Turn-on time at IOUT = 1 mA; VOUT = 3.3 V 10/16 DocID022735 Rev 5 LDLN015 Typical performance characteristics Figure 22: Turn-on time at IOUT= 150 mA, VOUT = 3.3 V DocID022735 Rev 5 Figure 23: Startup transient 11/16 Package information 6 LDLN015 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 DFN6 (2 x 2 mm) package information Figure 24: DFN6 (2 x 2 mm) package outline 12/16 DocID022735 Rev 5 LDLN015 Package information Table 6: DFN6 (2 x 2 mm) mechanical data mm Dim. Min. Typ. Max. A 0.51 0.55 0.60 A1 0 0.02 0.05 b 0.18 0.25 0.30 D D2 2.00 1.30 E E2 1.55 2.00 0.85 e L 1.45 1.00 1.10 0.50 0.15 0.25 0.35 Figure 25: DFN6 (2 x 2 mm) recommended footprint DocID022735 Rev 5 13/16 Package information 6.2 LDLN015 DFN6 (2 x 2 mm) packing information Figure 26: DFN6 (2 x 2 mm) reel outline Table 7: DFN6 (2 x 2 mm) tape and reel mechanical data Dim. mm Min. Typ. A 180 C 12.8 D 20.2 N 60 13.2 T 14/16 Max. 14.4 A0 2.4 B0 2.4 K0 1.3 P0 4 P 4 DocID022735 Rev 5 LDLN015 7 Revision history Revision history Table 8: Document revision history Date Revision 31-Jan-2012 1 Initial release. 2 Changed the LDLN015xx to LDLN015. Updated the Description in cover page. Updated Table 1: Device summary, Section 5: Typical performance characteristics and Section 6: Package information. Added Section 6.2: DFN6 (2 x 2 mm) packing information. Minor text changes. 14-Jan-2015 3 Updated the features in cover page. Updated Table 5: Electrical characteristics and Figure 9: Quiescent current vs. temperature. Minor text changes. 26-Oct-2015 4 Modified Section 6: Package information. Minor text changes. 18-May-2017 5 Updated Section 6.1: "DFN6 (2 x 2 mm) package information". Minor text changes. 15-Jan-2014 Changes DocID022735 Rev 5 15/16 LDLN015 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved 16/16 DocID022735 Rev 5