LSM6DS0TR

LSM6DS0 iNEMO inertial module: 3D accelerometer and 3D gyroscope Datasheet - production data Description The LSM6DS0 is a system-in-package featuring a 3D digital accelerometer and a 3D digital gyroscope. ST’s family of MEMS sensor modules leverages the robust and mature manufacturing processes already used for the production of micromachined accelerometers and gyroscopes. LGA-16L (3x3x0.86 mm) The various sensing elements are manufactured using specialized micromachining processes, while the IC interfaces are developed using CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics. Features  Analog supply voltage: 1.71 V to 3.6 V  Independent IOs supply (1.71 V)  “Always on” eco power mode down to 1.8 mA  3 independent acceleration channels and 3 angular rate channels  ±2/±4/±8/±16 g full scale  ±245/±500/±2000 dps full scale  SPI/I2C serial interface  Embedded temperature sensor The LSM6DS0 has a full-scale acceleration range of ±2/±4/±8/±16 g and an angular rate range of ±245/±500/±2000 dps. The LSM6DS0 has two operating modes in that the accelerometer and gyroscope sensors can be either activated at the same ODR or the accelerometer can be enabled while the gyroscope is in power-down. The LSM6DS0 is available in a plastic land grid array (LGA) package.  Embedded FIFO  ECOPACK®, RoHS and “Green” compliant Table 1. Device summary Applications Part number Temp. range [°C] LSM6DS0 -40 to +85  GPS navigation systems  Impact recognition and logging  Gaming and virtual reality input devices LSM6DS0TR -40 to +85  Motion-activated functions Package LGA-16L (3x3x0.86 mm) Packing Tray Tape and reel  Intelligent power saving for handheld devices  Vibration monitoring and compensation  Free-fall detection  6D orientation detection November 2014 This is information on a product in full production. DocID025604 Rev 3 1/59 www.st.com Contents LSM6DS0 Contents 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Module specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 3 4 2.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 SPI - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.2 I2C - inter-IC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6 Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.1 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.2 Zero-g and zero rate level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Gyroscope power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3 Multiple reads (burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 Digital block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.1 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5.2 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.3 Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5.4 Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.5 Bypass-to-Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1 I2C serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.1 4.2 2/59 Recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SPI bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2.1 SPI read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DocID025604 Rev 3 LSM6DS0 Contents 4.2.3 5 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 External capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.1 ACT_THS (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.2 ACT_DUR (05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.3 INT_GEN_CFG_XL (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.4 INT_GEN_THS_X_XL (07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.5 INT_GEN_THS_Y_XL (08h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.6 INT_GEN_THS_Z_XL (09h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.7 INT_GEN_DUR_XL (0Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.8 REFERENCE_G (0Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.9 INT_CTRL (0Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.10 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.11 CTRL_REG1_G (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.12 CTRL_REG2_G (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.13 CTRL_REG3_G (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.14 ORIENT_CFG_G (13h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.15 INT_GEN_SRC_G (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.16 OUT_TEMP_L (15h), OUT_TEMP_H (16h) . . . . . . . . . . . . . . . . . . . . . . . 43 7.17 STATUS_REG (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.18 OUT_X_G (18h - 19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.19 OUT_Y_G (1Ah - 1Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.20 OUT_Z_G (1Ch - 1Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.21 CTRL_REG4 (1Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.22 CTRL_REG5_XL (1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.23 CTRL_REG6_XL (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.24 CTRL_REG7_XL (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.25 CTRL_REG8 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.26 CTRL_REG9 (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 DocID025604 Rev 3 3/59 59 Contents LSM6DS0 7.27 CTRL_REG10 (24h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.28 INT_GEN_SRC_XL (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.29 STATUS_REG (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.30 OUT_X_XL (28h - 29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.31 OUT_Y_XL (2Ah - 2Bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.32 OUT_Z_XL (2Ch - 2Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.33 FIFO_CTRL (2Eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.34 FIFO_SRC (2Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.35 INT_GEN_CFG_G (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.36 INT_GEN_THS_X_G (31h - 32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.37 INT_GEN_THS_Y_G (33h - 34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.38 INT_GEN_THS_Z_G (35h - 36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.39 INT_GEN_DUR_G (37h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8 Soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4/59 DocID025604 Rev 3 LSM6DS0 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 SPI slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Gyroscope operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Operating mode current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Accelerometer turn-on time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Gyroscope turn-on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 I2C terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SAD+Read/Write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 28 Transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 28 Register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 ACT_THS register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ACT_THS register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ACT_DUR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 ACT_DUR register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT_GEN_CFG_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INT_GEN_CFG_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT_GEN_THS_X_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT_GEN_THS_X_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT_GEN_THS_Y_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT_GEN_THS_Y_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT_GEN_THS_Z_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT_GEN_THS_Z_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT_GEN_DUR_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT_GEN_DUR_XL register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 REFERENCE_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 REFERENCE_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INT_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 INT_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 WHO_AM_I register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CTRL_REG1_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 CTRL_REG1_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ODR and BW configuration setting (after LPF1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ODR and BW configuration setting (after LPF2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 CTRL_REG2_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG2_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG3_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 CTRL_REG3_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Gyroscope high-pass filter cutoff frequency configuration [Hz]. . . . . . . . . . . . . . . . . . . . . . 42 DocID025604 Rev 3 5/59 59 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. 6/59 LSM6DS0 ORIENT_CFG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ORIENT_CFG_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 INT_GEN_SRC_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 INT_GEN_SRC_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 OUT_TEMP_L register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 OUT_TEMP_H register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 OUT_TEMP register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CTRL_REG4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CTRL_REG4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CTRL_REG5_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CTRL_REG5_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 CTRL_REG6_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CTRL_REG6_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ODR register setting (accelerometer only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 CTRL_REG7_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CTRL_REG7_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Low pass cut-off frequency in high resolution mode (HR = 1) . . . . . . . . . . . . . . . . . . . . . . 47 CTRL_REG8 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CTRL_REG8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 CTRL_REG9 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 CTRL_REG9 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 CTRL_REG10 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 CTRL_REG10 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 INT_GEN_SRC_XL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 INT_GEN_SRC_XL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 STATUS_REG register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 STATUS_REG register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FIFO_CTRL register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FIFO_CTRL register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FIFO mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FIFO_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FIFO_SRC register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 FIFO_SRC example: OVR/FSS details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 INT_GEN_CFG_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 INT_GEN_CFG_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 INT_GEN_THS_XH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 INT_GEN_THS_XL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 INT_GEN_THS_X_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 INT_GEN_THS_YH_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 INT_GEN_THS_YL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 INT_GEN_THS_Y_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 INT_GEN_THS_ZH_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 INT_GEN_THS_ZL_G register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 INT_GEN_THS_Z_G register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 INT_GEN_DUR_G register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 INT_GEN_DUR_G register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DocID025604 Rev 3 LSM6DS0 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SPI slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2C slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Switching operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Multiple reads: accelerometer only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Multiple reads: accelerometer and gyroscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Digital block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Continuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Continuous-to-FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bypass-to-Continuous mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 SPI read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Multiple byte SPI read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SPI write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Multiple byte SPI write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SPI read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 LSM6DS0 electrical connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 INT_SEL and OUT_SEL configuration gyroscope block diagram . . . . . . . . . . . . . . . . . . . 41 Wait bit disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Wait bit enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 LGA 3x3x0.86 16L package outline and dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 DocID025604 Rev 3 7/59 59 Pin description 1 LSM6DS0 Pin description Figure 1. Pin connections Z 14 Z X 8/59 +Ω Y +Ω X (TOP VIEW) DIRECTIONS OF THE DETECTABLE ANGULAR RATES DocID025604 Rev 3 BOTTOM VIEW 9 5 8 6 RES +Ω 1 INT X 16 13 RES GND GND RES RES RES Vdd Cap DIRECTION OF THE DETECTABLE ACCELERATIONS RES (TOP VIEW) Y Vdd_IO SCL/SPC SDA/SDI/SDO SDO/SA0 CS LSM6DS0 Pin description Table 2. Pin description Pin# Name Function 1 Vdd_IO(1) 2 SCL SPC I2C serial clock (SCL) SPI serial port clock (SPC) 3 SDA SDI SDO I2C serial data (SDA) SPI serial data input (SDI) 3-wire interface serial data output (SDO) 4 SDO SA0 SPI serial data output (SDO) I2C least significant bit of the device address (SA0) 5 CS 6 RES Leave unconnected 7 INT Programmable interrupt 8 RES Connect to GND 9 RES Connect to GND 10 RES Connect to GND 11 RES Connect to Vdd or GND 12 GND 0 V supply 13 GND 0 V supply 14 Cap Connect to GND with ceramic capacitor(2) 15 RES Connect to Vdd or GND 16 Vdd(3) Power supply for I/O pins SPI enable I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) Power supply 1. Recommended 100 nF filter capacitor. 2. 10 nF (±10%), 16 V. 1 nF minimum value has to be guaranteed under 11 V bias condition. 3. Recommended 100 nF plus 10 μF capacitors. DocID025604 Rev 3 9/59 59 Module specifications LSM6DS0 2 Module specifications 2.1 Mechanical characteristics @ Vdd = 2.2 V, T = 25 °C unless otherwise noted(a) Table 3. Mechanical characteristics Symbol Test conditions Parameter Min. Typ.(1) Max. Unit ±2 LA_FS ±4 Linear acceleration measurement range g ±8 ±16 ±245 G_FS Angular rate measurement range ±500 dps ±2000 LA_So G_So Linear acceleration sensitivity Angular rate sensitivity FS = ±2 g 0.061 FS = ±4 g 0.122 FS = ±8 g 0.244 FS = ±16 g 0.732 FS = ±245 dps 8.75 FS = ±500 dps 17.50 FS = ±2000 dps 70 mg/LSb mdps/LSb LA_TyOff Linear acceleration typical zero-g level offset accuracy(2) FS = ±8 g ±90 mg G_TyOff Angular rate typical zero-rate level(3) FS = ±2000 dps ±30 dps Gyro ON 952 476 238 119 59.5 14.9 Hz Gyro OFF 952 476 238 119 50 10 Hz LA_ODR Linear acceleration output data rate a. The product is factory calibrated at 2.2 V. The operational power supply range is from 1.71 V to 3.6 V. 10/59 DocID025604 Rev 3 LSM6DS0 Module specifications Table 3. Mechanical characteristics (continued) Symbol G_ODR Top Parameter Test conditions Min. Typ.(1) Max. 952 476 238 119 59.5 14.9 Angular digital output data rate Operating temperature range -40 Unit Hz +85 °C 1. Typical specifications are not guaranteed. 2. Typical zero-g level offset value after soldering. 3. Typical zero-rate level offset value after MSL3 preconditioning. DocID025604 Rev 3 11/59 59 Module specifications 2.2 LSM6DS0 Electrical characteristics @ Vdd = 2.2 V, T = 25 °C unless otherwise noted Table 4. Electrical characteristics Symbol Vdd Parameter Test conditions Supply voltage Vdd_IO Power supply for I/O LA_Idd G_Idd Top Trise Twait Accelerometer current consumption in normal mode Min. Max. Unit 1.71 3.6 V 1.71 Vdd + 0.1 V ODR = 10 Hz 60 ODR = 50 Hz 160 ODR  119 Hz 330 Gyroscope current consumption in normal mode μA 4.0 Operating temperature range Time for power supply rising Typ.(1) (2) Time delay between Vdd_IO and Vdd mA -40 +85 °C 0.01 100 ms 0 10 ms (2) 1. Typical specifications are not guaranteed. 2. Please refer to Section 2.2.1: Recommended power-up sequence for more details. 2.2.1 Recommended power-up sequence For the power-up sequence please refer to the following figure, where:  Trise is the time for the power supply to rise from 10% to 90% of its final value  Twait is the time delay between the end of the Vdd_IO ramp (90% of its final value) and the start of the Vdd ramp Figure 2. Recommended power-up sequence Trise Vdd_IO 0V Twait Vdd 0V Trise 12/59 DocID025604 Rev 3 LSM6DS0 2.3 Module specifications Temperature sensor characteristics @ Vdd = 2.2 V, T = 25 °C unless otherwise noted (b) Table 5. Temperature sensor characteristics Symbol Parameter TODR Temperature refresh rate TSen Temperature sensitivity(3) Top Test condition Min. Gyro off(2) Typ.(1) Max. 50 Gyro on Hz 59.5 16 Operating temperature range -40 Unit LSB/°C +85 °C 1. Typical specifications are not guaranteed. 2. When the accelerometer ODR is set to 10 Hz and the gyroscope part is turned off, the TODR value is 10 Hz. 3. The output of the temperature sensor is 0 (typ.) at 25°C b. The product is factory calibrated at 2.2 V. DocID025604 Rev 3 13/59 59 Module specifications LSM6DS0 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 6. SPI slave timing values Value(1) Symbol Parameter Unit Min tc(SPC) SPI clock cycle fc(SPC) SPI clock frequency tsu(CS) CS setup time 5 th(CS) CS hold time 20 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time th(SO) SDO output hold time tdis(SO) SDO output disable time Max 100 ns 10 MHz ns 50 5 50 1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production Figure 3. SPI slave timing diagram Note: 14/59 Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports. DocID025604 Rev 3 LSM6DS0 2.4.2 Module specifications I2C - inter-IC control interface Subject to general operating conditions for Vdd and Top. Table 7. I2C slave timing values Symbol f(SCL) I2C Standard mode(1) Parameter SCL clock frequency I2C Fast mode (1) Min Max Min Max 0 100 0 400 tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time 0 th(ST) START condition hold time 4 0.6 tsu(SR) Repeated START condition setup time 4.7 0.6 tsu(SP) STOP condition setup time 4 0.6 4.7 1.3 tw(SP:SR) Bus free time between STOP and START condition 3.45 Unit kHz μs ns 0 0.9 μs μs 1. Data based on standard I2C protocol requirement, not tested in production. Figure 4. I2C slave timing diagram REPEATED START START tsu(SR) tw(SP:SR) SDA tsu(SDA) START th(SDA) tsu(SP) STOP SCL th(ST) Note: tw(SCLL) tw(SCLH) Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. DocID025604 Rev 3 15/59 59 Module specifications 2.5 LSM6DS0 Absolute maximum ratings Stresses above those listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 8. Absolute maximum ratings Symbol Maximum value Unit Vdd Supply voltage -0.3 to 4.8 V TSTG Storage temperature range -40 to +125 °C 10,000 g 2 kV 0.3 to Vdd_IO +0.3 V Sg ESD Vin Note: Ratings Acceleration g for 0.1 ms Electrostatic discharge protection (HBM) Input voltage on any control pin (including CS, SCL/SPC, SDA/SDI/SDO, SDO/SA0) Supply voltage on any pin should never exceed 4.8 V. This device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. This device is sensitive to electrostatic discharge (ESD), improper handling can cause permanent damage to the part. 16/59 DocID025604 Rev 3 LSM6DS0 Module specifications 2.6 Terminology 2.6.1 Sensitivity Linear acceleration sensitivity can be determined, for example, by applying 1 g acceleration to the device. Because the sensor can measure DC accelerations, this can be done easily by pointing the selected axis towards the ground, noting the output value, rotating the sensor 180 degrees (pointing towards the sky) and noting the output value again. By doing so, ±1 g acceleration is applied to the sensor. Subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. This value changes very little over temperature and over time. The sensitivity tolerance describes the range of sensitivities of a large number of sensors. An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the considered axis. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time. 2.6.2 Zero-g and zero rate level Linear acceleration zero-g level offset (TyOff) describes the deviation of an actual output signal from the ideal output signal if no acceleration is present. A sensor in a steady state on a horizontal surface will measure 0 g on both the X-axis and Y-axis, whereas the Z-axis will measure 1 g. Ideally, the output is in the middle of the dynamic range of the sensor (content of OUT registers 00h, data expressed as two’s complement number). A deviation from the ideal value in this case is called zero-g offset. Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. Offset changes little over temperature, see “Linear acceleration zero-g level change vs. temperature” in Table 3. The zero-g level tolerance (TyOff) describes the standard deviation of the range of zero-g levels of a group of sensors. The zero-rate level describes the actual output signal if there is no angular rate present. The zero-rate level of precise MEMS sensors is, to some extent, a result of stress to the sensor and therefore the zero-rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress. This value changes very little over temperature and time. DocID025604 Rev 3 17/59 59 Functionality LSM6DS0 3 Functionality 3.1 Operating modes The LSM6DS0 has two operating modes available: only accelerometer active and gyroscope in power-down or both accelerometer and gyroscope sensors active at the same ODR. Switching from one mode to the other requires one write operation: writing to CTRL_REG6_XL (20h), the accelerometer operates in normal mode and the gyroscope is powered down, writing to CTRL_REG1_G (10h) both the accelerometer and gyroscope are activated at the same ODR. Figure 5 depicts both modes of operation from power down. Figure 5. Switching operating modes Accelerometer Only Write CTRL_REG6_XL Power Down Write CTRL_REG1_G With CTRL_REG6_XL = PD 3.2 Write CTRL_REG1_G Accelerometer + Gyro Gyroscope power modes In the LSM6DS0, the gyroscope can be configured in three different operating modes: power-down, low-power and normal mode. Low-power mode is available for lower ODR (14.9, 59.5, 119 Hz) while for greater ODR (238, 476, 952 Hz) the device is automatically in normal mode. Table 9 summarizes the ODR configuration (ODR_G[2:0] bits set in CTRL_REG1_G (10h)) and the corresponding power modes. To enable low-power mode, the LP_mode bit in CTRL_REG3_G (12h) has to be set to ‘1’. Low-power mode allows reaching low-power consumption while maintaining the device always on, refer to Table 10. 18/59 DocID025604 Rev 3 LSM6DS0 Functionality Table 9. Gyroscope operating modes ODR_G [2:0] Power mode(1) ODR [Hz] 000 Power-down Power-down 001 14.9 Low-power/Normal mode 010 59.5 Low-power/Normal mode 011 119 Low-power/Normal mode 100 238 Normal mode 101 476 Normal mode 110 952 Normal mode 1. Gyroscope low-power mode is available for G_FS = ±2000 dps. Table 10. Operating mode current consumption ODR [Hz] Current consumption(1) Power mode [mA] 14.9 Low-power 1.8 59.5 Low-power 2.3 119 Low-power 2.9 238 Normal mode 4.3 476 Normal mode 4.3 952 Normal mode 4.3 1. Typical values of gyroscope and accelerometer current consumption are based on characterization data Table 11. Accelerometer turn-on time BW = 400 Hz(1) ODR [Hz] BW = 200 Hz(1) BW = 100 Hz(1) BW = 50 Hz(1) 14.9 0 0 0 0 59.5 0 0 0 0 119 1 1 1 2 238 1 1 2 4 476 1 2 4 7 952 2 4 7 14 1. The table contains the number of samples to be discarded after switching between power-down mode and normal mode. DocID025604 Rev 3 19/59 59 Functionality LSM6DS0 Table 12. Gyroscope turn-on time LPF1 only(1) ODR [Hz] LPF1 and LPF2(1) 14.9 2 LPF2 not available 59.5 or 119 3 13 238 4 14 476 5 15 952 8 18 1. The table contains the number of samples to be discarded after switching between low-power mode and normal mode. 3.3 Multiple reads (burst) When only the accelerometer is activated and the gyroscope is in power down, starting from OUT_X_XL (28h - 29h) multiple reads can be performed. Once OUT_Z_XL (2Ch - 2Dh) is read, the system automatically restarts from OUT_X_XL (28h - 29h) (see Figure 6). Figure 6. Multiple reads: accelerometer only Read #1 Read #n x,y,z OUT_TEMP (15-16) OUT_X_XL OUT_Y_XL OUT_Z_XL (2A-2B) (28-29) (2C-2D) x,y,z OUT_X_XL OUT_Y_XL OUT_Z_XL (2A-2B) (28-29) (2C-2D) When both accelerometer and gyroscope sensors are activated at the same ODR, starting from OUT_X_G (18h - 19h) multiple reads can be performed. Once OUT_Z_XL (2Ch - 2Dh) is read, the system automatically restarts from OUT_X_G (18h - 19h) (see Figure 7). Figure 7. Multiple reads: accelerometer and gyroscope Read #1 Read #n 20/59 x,y,z OUT_TEMP (15-16) OUT_X_G OUT_Y_G OUT_Z_G OUT_X_XL OUT_Y_XL OUT_Z_XL (1A-1B) (2A-2B) (18-19) (1C-1D) (28-29) (2C-2D) x,y,z OUT_X_G OUT_Y_G OUT_Z_G OUT_X_XL OUT_Y_XLOUT_Z_XL (1A-1B) (2A-2B) (18-19) (1C-1D) (28-29) (2C-2D) DocID025604 Rev 3 LSM6DS0 3.4 Functionality Digital block diagram Figure 8. Digital block diagram HR HPIS1 0 0 LPF2 XL 1 1 LPF1 XL ADC XL HPF XL Interrupt Generator XL 0 1 FDS OUT_SEL Data Reg FIFO 0 ADC Gyro LPF1 Gyro HPF Gyro 1 I2C SPI LPF2 Gyro SRC Registers CFG Registers HP_EN Interrupt Generator Gyro INT_SEL DocID025604 Rev 3 21/59 59 Functionality 3.5 LSM6DS0 FIFO The LSM6DS0 embeds 32 slots of 16-bit data FIFO for each of the gyroscope’s three output channels, yaw, pitch and roll, and 16-bit data FIFO for each of the accelerometer’s three output channels, X, Y and Z. This allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the FIFO. This buffer can work accordingly to five different modes: Bypass mode, FIFO-mode, Continuous mode, Continuous-to-FIFO mode and Bypass-to-Continuous. Each mode is selected by the FMODE [2:0] bits in the FIFO_CTRL (2Eh) register. Programmable FIFO threshold status, FIFO overrun events and the number of unread samples stored are available in the FIFO_SRC (2Fh) register and can be set to generate dedicated interrupts on the INT pin using the INT_CTRL (0Ch) register. FIFO_SRC (2Fh)(FTH) goes to '1' when the number of unread samples (FIFO_SRC (2Fh) (FSS5:0)) is greater than or equal to FTH [4:0] in FIFO_CTRL (2Eh). If FIFO_CTRL (2Eh) (FTH[4:0]) is equal to 0, FIFO_SRC (2Fh)(FTH) goes to ‘0’. FIFO_SRC (2Fh)(OVRN) is equal to '1' if a FIFO slot is overwritten. FIFO_SRC (2Fh)(FSS [5:0]) contains stored data levels of unread samples. When FSS [5:0] is equal to ‘000000’, FIFO is empty. When FSS [5:0] is equal to ‘100000’, FIFO is full and the unread samples are 32. The FIFO feature is enabled by writing '1' in CTRL_REG9 (23h) (FIFO_EN). To guarantee the correct acquisition of data during the switching into and out of FIFO mode, the first sample acquired must be discarded. 3.5.1 Bypass mode In Bypass mode (FIFO_CTRL (2Eh)(FMODE [2:0]= 000), the FIFO is not operational and it remains empty. Bypass mode is also used to reset the FIFO when in FIFO mode. As described in Figure 9, for each channel only the first address is used. When new data is available the old data is overwritten. Figure 9. Bypass mode xi,yi,zi empty 22/59 x0 y0 z0 x1 y1 z1 x2 y2 z2 x31 y31 z31 DocID025604 Rev 3 LSM6DS0 3.5.2 Functionality FIFO mode In FIFO mode (FIFO_CTRL (2Eh) (FMODE [2:0] = 001) data from the output channels are stored in the FIFO until it is overwritten. To reset FIFO content, Bypass mode should be selected by writing FIFO_CTRL (2Eh) (FMODE [2:0]) to '000'. After this reset command, it is possible to restart FIFO mode, writing FIFO_CTRL (2Eh) (FMODE [2:0]) to '001'. The FIFO buffer memorizes 32 levels of data, but the depth of the FIFO can be resized by setting the STOP_ON_FTH bit in CTRL_REG9 (23h). If the STOP_ON_FTH bit is set to '1', FIFO depth is limited to FIFO_CTRL (2Eh)(FTH [4:0]) + 1 data. A FIFO threshold interrupt can be enabled (INT_OVR bit in INT_CTRL (0Ch)) in order to be raised when the FIFO is filled to the level specified by the FTH[4:0] bits of FIFO_CTRL (2Eh). When a FIFO threshold interrupt occurs, the first data has been overwritten and the FIFO stops collecting data from the input channels. Figure 10. FIFO mode xi,yi,zi 3.5.3 x0 y0 z0 x1 y1 z1 x2 y2 z2 x31 y31 z31 Continuous mode Continuous mode (FIFO_CTRL (2Eh) (FMODE[2:0] = 110) provides a continuous FIFO update: as new data arrives the older is discarded. A FIFO threshold flag FIFO_SRC (2Fh)(FTH) is asserted when the number of unread samples in FIFO is greater than or equal to FIFO_CTRL (2Eh)(FTH4:0). It is possible to route FIFO_SRC (2Fh)(FTH) to the INT pin by writing the INT_FTH bit to ‘1’ in register INT_CTRL (0Ch). A full-flag interrupt can be enabled (INT_CTRL (0Ch) (INT_ FSS5)= '1') when the FIFO becomes saturated and in order to read the contents all at once. If an overrun occurs, the oldest sample in FIFO is overwritten and the OVRN flag in FIFO_SRC (2Fh) is asserted. In order to empty the FIFO before it is full, it is also possible to pull from FIFO the number of unread samples available in FIFO_SRC (2Fh) (FSS[5:0]). DocID025604 Rev 3 23/59 59 Functionality LSM6DS0 Figure 11. Continuous mode xi,yi,zi 3.5.4 x0 y0 z0 x1 y1 z1 x2 y2 z2 x30 y30 z30 x31 y31 z31 Continuous-to-FIFO mode In Continuous-to-FIFO mode (FIFO_CTRL (2Eh)(FMODE [2:0] = 011), FIFO behavior changes according to the INT_GEN_SRC_XL (26h)(IA_XL) bit. When the INT_GEN_SRC_XL (26h)(IA_XL) bit is equal to '1', FIFO operates in FIFO mode. When the INT_GEN_SRC_XL (26h)(IA_XL) bit is equal to '0', FIFO operates in Continuous mode. The interrupt generator should be set to the desired configuration by means of INT_GEN_CFG_XL (06h), INT_GEN_THS_X_XL (07h), INT_GEN_THS_Y_XL (08h) and INT_GEN_THS_Z_XL (09h). The CTRL_REG4 (1Eh)(LIR_XL) bit should be set to '1' in order to have latched interrupt. Figure 12. Continuous-to-FIFO mode xi,yi,zi x0 y0 z0 x1 y1 z1 x2 y2 z2 x30 y30 z30 x31 y31 z31 xi,yi,zi Continuous Mode Trigger event 24/59 DocID025604 Rev 3 x0 y0 z0 x1 y1 z1 x2 y2 z2 x31 y31 z31 FIFO Mode LSM6DS0 3.5.5 Functionality Bypass-to-Continuous mode In Bypass-to-Continuous mode (FIFO_CTRL (2Eh)(FMODE[2:0] = '100'), data measurement storage inside FIFO operates in Continuous mode when INT_GEN_SRC_XL (26h)(IA_XL) is equal to '1', otherwise FIFO content is reset (Bypass mode). The interrupt generator should be set to the desired configuration by means of INT_GEN_CFG_XL (06h), INT_GEN_THS_X_XL (07h), INT_GEN_THS_Y_XL (08h) and INT_GEN_THS_Z_XL (09h). The CTRL_REG4 (1Eh)(LIR_XL) bit should be set to '1' in order to have latched interrupt. Figure 13. Bypass-to-Continuous mode xi,yi,zi empty x0 y0 z0 x1 y1 z1 x2 y2 z2 x31 y31 xi,yi,zi x0 y0 z0 x1 y1 z1 x2 y2 z2 x30 y30 z30 x31 y31 z31 z31 Bypass Mode Continuous Mode Trigger event DocID025604 Rev 3 25/59 59 Digital interfaces 4 LSM6DS0 Digital interfaces The registers embedded inside the LSM6DS0 may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the CS line must be tied high (i.e connected to Vdd_IO). Table 13. Serial interface pin description Pin name Pin description CS SPI enable I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) SCL/SPC SDA/SDI/SDO SDO/SA0 4.1 I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SPI Serial Data Output (SDO) I2C less significant bit of the device address I2C serial interface The LSM6DS0 I2C is a bus slave. The I2C is employed to write the data to the registers whose content can also be read back. The relevant I2C terminology is provided in the table below. Table 14. I2C terminology Term Transmitter Receiver Description The device which sends data to the bus The device which receives data from the bus Master The device which initiates a transfer, generates clock signals and terminates a transfer Slave The device addressed by the master There are two signals associated with the I2C bus: the serial clock line (SCL) and the Serial DAta line (SDA). The latter is a bidirectional line used for sending and receiving the data to/from the interface. Both the lines must be connected to Vdd_IO through an external pullup resistor. When the bus is free, both the lines are high. The I2C interface is implemeted with fast mode (400 kHz) I2C standards as well as with the standard mode. In order to disable the I2C block, the I2C_disable bit must be written to ‘1’ in CTRL_REG9 (23h). 26/59 DocID025604 Rev 3 LSM6DS0 4.1.1 Digital interfaces I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a high-to-low transition on the data line while the SCL line is held high. After this has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the master. The Slave ADdress (SAD) associated to the LSM6DS0 is 110101xb. The SDO/SA0 pin can be used to modify the less significant bit of the device address. If the SDO/SA0 pin is connected to a voltage supply, LSb is ‘1’ (address 1101011b), else if the SDO/SA0 pin is connected to ground, the LSb value is ‘0’ (address 1101010b). This solution permits to connect and address two different inertial modules to the same I2C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded inside the LSM6DS0 behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, an 8-bit sub-address (SUB) is transmitted. The increment of the address is configured by the CTRL_REG8 (22h) (IF_ADD_INC). The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated START (SR) condition must be issued after the two sub-address bytes. If the bit is ‘0’ (Write) the master will transmit to the slave with direction unchanged. Table 15 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 15. SAD+Read/Write patterns Command SAD[6:1] SAD[0] = SA0 R/W SAD+R/W Read 110101 0 1 11010101 (D5h) Write 110101 0 0 11010100 (D4h) Read 110101 1 1 11010111 (D7h) Write 110101 1 0 11010110 (D6h) Table 16. Transfer when master is writing one byte to slave Master ST SAD + W Slave SUB SAK DATA SAK SP SAK Table 17. Transfer when master is writing multiple bytes to slave Master Slave ST SAD + W SUB SAK DATA SAK DocID025604 Rev 3 DATA SAK SP SAK 27/59 59 Digital interfaces LSM6DS0 Table 18. Transfer when master is receiving (reading) one byte of data from slave Master ST SAD + W Slave SUB SAK SR SAD + R SAK NMAK SAK SP DATA Table 19. Transfer when master is receiving (reading) multiple bytes of data from slave Master Slave ST SAD+W SUB SAK SR SAD+R SAK MAK SAK DATA MAK DAT A NMAK SP DATA Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit (MSb) first. If a receiver can’t receive another complete byte of data until it has performed some other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be left high by the slave. The master can then abort the transfer. A low-to-high transition on the SDA line while the SCL line is high is defined as a STOP condition. Each data transfer must be terminated by the generation of a STOP (SP) condition. In the presented communication format MAK is Master acknowledge and NMAK is No Master Acknowledge. 4.2 SPI bus interface The LSM6DS0 SPI is a bus slave. The SPI allows to write and read the registers of the device. The serial interface connects to applications using 4 wires: CS, SPC, SDI and SDO. Figure 14. Read and write protocol CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and it is controlled by the SPI master. It goes low at the start of the transmission and goes back high at the end. SPC is the serial port clock and it is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are respectively the serial port data input and output. Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC. 28/59 DocID025604 Rev 3 LSM6DS0 Digital interfaces Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple read/write bytes. Bit duration is the time between two falling edges of SPC. The first bit (bit 0) starts at the first falling edge of SPC after the falling edge of CS while the last bit (bit 15, bit 23, ...) starts at the last falling edge of SPC just before the rising edge of CS. bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0) from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written into the device (MSb first). bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When the CTRL_REG8 (22h) (IF_ADD_INC) bit is ‘0’, the address used to read/write data remains the same for every block. When the CTRL_REG8 (22h)(IF_ADD_INC) bit is ‘1’, the address used to read/write data is increased at every block. The function and the behavior of SDI and SDO remain unchanged. 4.2.1 SPI read Figure 15. SPI read protocol CS SPC SDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that will be read from the device (MSb first). bit 16-... : data DO(...-8). Further data in multiple byte reads. DocID025604 Rev 3 29/59 59 Digital interfaces LSM6DS0 Figure 16. Multiple byte SPI read protocol (2-byte example) CS SPC SDI RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15DO14DO13DO12DO11DO10DO9 DO8 4.2.2 SPI write Figure 17. SPI write protocol CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 The SPI write command is performed with 16 clock pulses. A multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0: WRITE bit. The value is 0. bit 1 -7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DI(7:0) (write mode). This is the data that is written inside the device (MSb first). bit 16-... : data DI(...-8). Further data in multiple byte writes. Figure 18. Multiple byte SPI write protocol (2-byte example) CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 30/59 DocID025604 Rev 3 LSM6DS0 4.2.3 Digital interfaces SPI read in 3-wire mode 3-wire mode is entered by setting the CTRL_REG8 (22h)(SIM) bit equal to ‘1’ (SPI serial interface mode selection). Figure 19. SPI read protocol in 3-wire mode CS SPC SDI/O DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 RW AD6 AD5 AD4 AD3 AD2 AD1 AD0 The SPI read command is performed with 16 clock pulses: bit 0: READ bit. The value is 1. bit 1-7: address AD(6:0). This is the address field of the indexed register. bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). A multiple read command is also available in 3-wire mode. DocID025604 Rev 3 31/59 59 Application hints 5 LSM6DS0 Application hints Figure 20. LSM6DS0 electrical connections Vdd_IO C2 100 nF GND Vdd_IO SCL/SPC SDO/SA0 CS SDA /SDI/SDO Vdd C3 5 RES 100 nF GND Vdd (TOP VIEW) INT C4 1 10 μF GND RES RES Cap *C1 13 9 GND 10nF(16V) GND GND RES RES RES * C1 must guarantee 1 nF value under 11 V bias condition GND 5.1 External capacitors The device core is supplied through the Vdd line. Power supply decoupling capacitors (C2, C3 = 100 nF ceramic, C4 = 10 μF Al) should be placed as near as possible to the supply pin of the device (common design practice). The functionality of the device and the measured acceleration/angular rate data is selectable and accessible through the SPI/I2C interface. 32/59 DocID025604 Rev 3 LSM6DS0 6 Register mapping Register mapping The table given below provides a list of the 8/16 bit registers embedded in the device and the corresponding addresses. Table 20. Register mapping Register address Name Type Default Hex Binary Reserved -- 00-03 -- -- ACT_THS r/w 04 00000100 00000000 ACT_DUR r/w 05 00000101 00000000 INT_GEN_CFG_XL r/w 06 00000110 00000000 INT_GEN_THS_X_XL r/w 07 00000111 00000000 INT_GEN_THS_Y_XL r/w 08 00001000 00000000 INT_GEN_THS_Z_XL r/w 09 00001001 00000000 INT_GEN_DUR_XL r/w 0A 00001010 00000000 REFERENCE_G r/w 0B 00001011 00000000 INT_CTRL r/w 0C 00001100 00000000 Reserved -- 0D-0E -- -- WHO_AM_I r 0F 00001111 01101000 CTRL_REG1_G r/w 10 00010000 00000000 CTRL_REG2_G r/w 11 00010001 00000000 CTRL_REG3_G r/w 12 00010010 00000000 ORIENT_CFG_G r/w 13 00010011 00000000 INT_GEN_SRC_G r 14 00010100 output OUT_TEMP_L r 15 00010101 output OUT_TEMP_H r 16 00010110 output STATUS_REG r 17 00010111 output OUT_X_L_G r 18 00011000 output OUT_X_H_G r 19 00011001 output OUT_Y_L_G r 1A 00011010 output OUT_Y_H_G r 1B 00011011 output OUT_Z_L_G r 1C 00011100 output OUT_Z_H_G r 1D 00011101 output CTRL_REG4 r/w 1E 00011110 00111000 CTRL_REG5_XL r/w 1F 00011111 00111000 CTRL_REG6_XL r/w 20 00100000 00000000 DocID025604 Rev 3 Note Reserved Reserved 33/59 59 Register mapping LSM6DS0 Table 20. Register mapping (continued) Register address Name Type Default Hex Binary CTRL_REG7_XL r/w 21 00100001 00000000 CTRL_REG8 r/w 22 00100010 00000100 CTRL_REG9 r/w 23 00100011 00000000 CTRL_REG10 r/w 24 00100100 00000000 Reserved -- 25 -- -- INT_GEN_SRC_XL r 26 00100110 output STATUS_REG r 27 00100111 output OUT_X_L_XL r 28 00101000 output OUT_X_H_XL r 29 00101001 output OUT_Y_L_XL r 2A 00101010 output OUT_Y_H_XL r 2B 00101011 output OUT_Z_L_XL r 2C 00101100 output OUT_Z_H_XL r 2D 00101101 output FIFO_CTRL r/w 2E 00101110 00000000 FIFO_SRC r 2F 00101111 output INT_GEN_CFG_G r/w 30 00110000 00000000 INT_GEN_THS_XH_G r/w 31 00110001 00000000 INT_GEN_THS_XL_G r/w 32 00110010 00000000 INT_GEN_THS_YH_G r/w 33 00110011 00000000 INT_GEN_THS_YL_G r/w 34 00110100 00000000 INT_GEN_THS_ZH_G r/w 35 00110101 00000000 INT_GEN_THS_ZL_G r/w 36 00110110 00000000 INT_GEN_DUR_G r/w 37 00110111 00000000 r 38-7F -- -- Reserved Note Reserved Reserved Registers marked as Reserved must not be changed. Writing to those registers may cause permanent damage to the device. To guarantee proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored on those registers must not be changed. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered up. 34/59 DocID025604 Rev 3 LSM6DS0 7 Register description Register description The device contains a set of registers which are used to control its behavior and to retrieve linear acceleration, angular rate and temperature data. The register addresses, consisting of 7 bits, are used to identify them and to write the data through the serial interface. 7.1 ACT_THS (04h) Activity threshold register. Table 21. ACT_THS register SLEEP_ON _INACT_EN ACT_THS6 ACT_THS5 ACT_THS4 ACT_THS3 ACT_THS2 ACT_THS1 ACT_THS0 Table 22. ACT_THS register description SLEEP_ON_ INACT_EN Gyroscope operating mode during inactivity. Default value: 0 ACT_THS [6:0] Inactivity threshold. Default value: 000 0000 7.2 (0: Gyroscope in power-down; 1: Gyroscope in sleep mode) ACT_DUR (05h) Inactivity duration register. Table 23. ACT_DUR register ACT_DUR7 ACT_DUR6 ACT_DUR5 ACT_DUR4 ACT_DUR3 ACT_DUR2 ACT_DUR1 ACT_DUR0 Table 24. ACT_DUR register description ACT_DUR [7:0] 7.3 Inactivity duration. Default value: 0000 0000 INT_GEN_CFG_XL (06h) Linear acceleration sensor interrupt generator configuration register. Table 25. INT_GEN_CFG_XL register AOI_XL 6D ZHIE_XL ZLIE_XL YHIE_XL DocID025604 Rev 3 YLIE_XL XHIE_XL XLIE_XL 35/59 59 Register description LSM6DS0 Table 26. INT_GEN_CFG_XL register description AOI_XL AND/OR combination of accelerometer’s interrupt events. Default value: 0 (0: OR combination; 1: AND combination) 6D 6-direction detection function for interrupt. Default value: 0 (0: disabled; 1: enabled) ZHIE_XL Enable interrupt generation on accelerometer’s Z-axis high event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) ZLIE_XL Enable interrupt generation on accelerometer’s Z-axis low event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) YHIE_XL Enable interrupt generation on accelerometer’s Y-axis high event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) YLIE_XL Enable interrupt generation on accelerometer’s Y-axis low event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) XHIE_XL Enable interrupt generation on accelerometer’s X-axis high event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value higher than preset threshold) XLIE_XL Enable interrupt generation on accelerometer’s X-axis low event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured acceleration value lower than preset threshold) 7.4 INT_GEN_THS_X_XL (07h) Linear acceleration sensor interrupt threshold register. Table 27. INT_GEN_THS_X_XL register THS_XL_X7 THS_XL_X6 THS_XL_X5 THS_XL_X4 THS_XL_X3 THS_XL_X2 THS_XL_X1 THS_XL_X0 Table 28. INT_GEN_THS_X_XL register description THS_XL_X [7:0] 36/59 X-axis interrupt threshold. Default value: 0000 0000 DocID025604 Rev 3 LSM6DS0 7.5 Register description INT_GEN_THS_Y_XL (08h) Linear acceleration sensor interrupt threshold register. Table 29. INT_GEN_THS_Y_XL register THS_XL_Y7 THS_XL_Y6 THS_XL_Y5 THS_XL_Y4 THS_XL_Y3 THS_XL_Y2 THS_XL_Y1 THS_XL_Y0 Table 30. INT_GEN_THS_Y_XL register description THS_XL_Y [7:0] 7.6 Y-axis interrupt threshold. Default value: 0000 0000 INT_GEN_THS_Z_XL (09h) Linear acceleration sensor interrupt threshold register. Table 31. INT_GEN_THS_Z_XL register THS_XL_Z7 THS_XL_Z6 THS_XL_Z5 THS_XL_Z4 THS_XL_Z3 THS_XL_Z2 THS_XL_Z1 THS_XL_Z0 Table 32. INT_GEN_THS_Z_XL register description THS_XL_Z [7:0] 7.7 Z-axis interrupt threshold. Default value: 0000 0000 INT_GEN_DUR_XL (0Ah) Linear acceleration sensor interrupt duration register. Table 33. INT_GEN_DUR_XL register WAIT_XL DUR_XL6 DUR_XL5 DUR_XL4 DUR_XL3 DUR_XL2 DUR_XL1 DUR_XL0 Table 34. INT_GEN_DUR_XL register description WAIT_XL Wait function enabled on duration counter. Default value: 0 (0: wait function off; 1: wait for DUR_XL [6:0] samples before exiting interrupt) DUR_XL [6:0] 7.8 Enter/exit interrupt duration value. Default value: 000 0000 REFERENCE_G (0Bh) Angular rate sensor reference value register for digital high-pass filter (r/w) Table 35. REFERENCE_G register REF7_G REF6_G REF5_G REF4_G REF3_G REF2_G REF1_G REF0_G Table 36. REFERENCE_G register description REF_G [7:0] Reference value for gyroscope’s digital high-pass filter (r/w). Default value: 0000 0000 DocID025604 Rev 3 37/59 59 Register description 7.9 LSM6DS0 INT_CTRL (0Ch) INT pin control register. Table 37. INT_CTRL register INT_IG _G INT_IG_XL INT_ FSS5 INT_OVR INT_FTH INT_ Boot INT_ DRDY_G INT_ DRDY_XL Table 38. INT_CTRL register description Gyroscope interrupt enable on INT pin. Default value: 0 INT_IG_G (0: disabled; 1: enabled) Accelerometer interrupt generator on INT pin. Default value: 0 INT_ IG_XL (0: disabled; 1: enabled) FSS5 interrupt enable on INT pin. Default value: 0 INT_ FSS5 (0: disabled; 1: enabled) Overrun interrupt on INT pin. Default value: 0 (0: disabled; 1: enabled) INT_OVR FIFO threshold interrupt on INT pin. Default value: 0 INT_FTH (0: disabled; 1: enabled) Boot status available on INT pin. Default value: 0 INT_ Boot (0: disabled; 1: enabled) Gyroscope data ready on INT pin. Default value: 0 INT_DRDY_G INT_DRDY_XL 7.10 (0: disabled; 1: enabled) Accelerometer data ready on INT pin. Default value: 0 (0: disabled; 1: enabled) WHO_AM_I (0Fh) Who_AM_I register. Table 39. WHO_AM_I register 0 7.11 1 1 0 1 0 0 0 BW_G1 BW_G0 CTRL_REG1_G (10h) Angular rate sensor control register 1. Table 40. CTRL_REG1_G register ODR_G2 ODR_G1 ODR_G0 FS_G1 FS_G0 1. This bit must be set to ‘0’ for the correct operation of the device 38/59 DocID025604 Rev 3 0(1) LSM6DS0 Register description Table 41. CTRL_REG1_G register description Gyroscope output data rate selection. Default value: 000 ODR_G [2:0] (Refer to Table 42 and Table 43) FS_G [1:0] Gyroscope full-scale selection. Default value: 00 (00: 245 dps; 01: 500 dps; 10: not available; 11: 2000 dps) BW_G [1:0] Gyroscope bandwidth selection. Default value: 00 ODR_G [2:0] are used to set ODR selection when both the accelerometer and gyroscope are activated. BW_G [1:0] are used to set the bandwidth selection of the gyroscope. The following table summarizes all frequencies available for each combination of the ODR_G / BW_G bits after LPF1 (see Table 42) and LPF2 (see Table 43) when both the accelerometer and gyroscope are activated. For more details regarding signal processing please refer to Figure 21. Table 42. ODR and BW configuration setting (after LPF1) ODR_G2 ODR_G1 ODR_G0 ODR [Hz] Cutoff [Hz](1) 0 0 0 Power-down n.a. 0 0 1 14.9 5 0 1 0 59.5 19 0 1 1 119 38 1 0 0 238 76 1 0 1 476 100 1 1 0 952 100 1 1 1 n.a. n.a. 1. The values in the table are indicative and can vary proportionally with the specific ODR value. DocID025604 Rev 3 39/59 59 Register description LSM6DS0 Table 43. ODR and BW configuration setting (after LPF2) ODR_G [2:0] BW_G [1:0] ODR [Hz] Cutoff [Hz](1) 000 00 Power-down n.a. 000 01 Power-down n.a. 000 10 Power-down n.a. 000 11 Power-down n.a. 001 00 14.9 n.a. 001 01 14.9 n.a. 001 10 14.9 n.a. 001 11 14.9 n.a. 010 00 59.5 16 010 01 59.5 16 010 10 59.5 16 010 11 59.5 16 011 00 119 14 011 01 119 31 011 10 119 31 011 11 119 31 100 00 238 14 100 01 238 29 100 10 238 63 100 11 238 78 101 00 476 21 101 01 476 28 101 10 476 57 101 11 476 100 110 00 952 33 110 01 952 40 110 10 952 58 110 11 952 100 111 00 n.a. n.a. 111 01 n.a. n.a. 111 10 n.a. n.a. 111 11 n.a. n.a. 1. The values in the table are indicative and can vary proportionally with the specific ODR value. 40/59 DocID025604 Rev 3 LSM6DS0 7.12 Register description CTRL_REG2_G (11h) Angular rate sensor control register 2. Table 44. CTRL_REG2_G register (1) 0 0 (1) 0(1) 0(1) INT_SEL1 INT_SEL0 OUT_SEL1 OUT_SEL0 1. These bits must be set to ‘0’ for the correct operation of the device Table 45. CTRL_REG2_G register description INT_SEL [1:0] INT selection configuration. Default value: 00 (Refer to Figure 21) OUT_SEL [1:0] Out selection configuration. Default value: 00 (Refer to Figure 21) Figure 21. INT_SEL and OUT_SEL configuration gyroscope block diagram DataReg FIFO LPF2 ADC LPF1 HPF Interrupt generator 7.13 CTRL_REG3_G (12h) Angular rate sensor control register 3. Table 46. CTRL_REG3_G register LP_mode HP_EN 0(1) 0(1) HPCF3_G HPCF2_G HPCF1_G HPCF0_G 1. These bits must be set to ‘0’ for the correct operation of the device Table 47. CTRL_REG3_G register description LP_mode Low-power mode enable. Default value: 0 (0: low-power disable; 1: low-power enable) HP_EN High-pass filter enable. Default value: 0 (0: HPF disabled; 1: HPF enabled, refer to Figure 21) HPCF_G [3:0] Gyroscope high-pass filter cutoff frequency selection. Default value: 0000 Refer to Table 48. DocID025604 Rev 3 41/59 59 Register description LSM6DS0 Table 48. Gyroscope high-pass filter cutoff frequency configuration [Hz](1) HPCF_G [3:0] ODR= 14.9 Hz ODR= 59.5 Hz ODR= 119 Hz ODR= 238 Hz ODR= 476 Hz ODR= 952 Hz 0000 1 4 8 15 30 57 0001 0.5 2 4 8 15 30 0010 0.2 1 2 4 8 15 0011 0.1 0.5 1 2 4 8 0100 0.05 0.2 0.5 1 2 4 0101 0.02 0.1 0.2 0.5 1 2 0110 0.01 0.05 0.1 0.2 0.5 1 0111 0.005 0.02 0.05 0.1 0.2 0.5 1000 0.002 0.01 0.02 0.05 0.1 0.2 1001 0.001 0.005 0.01 0.02 0.05 0.1 1. Values in the table are indicative and can vary proportionally with the specific ODR value. 7.14 ORIENT_CFG_G (13h) Angular rate sensor sign and orientation register. Table 49. ORIENT_CFG_G register 0(1) 0(1) SignX_G SignY_G SignZ_G Orient_2 Orient_1 1. These bits must be set to ‘0’ for the correct operation of the device Table 50. ORIENT_CFG_G register description SignX_G Pitch axis (X) angular rate sign. Default value: 0 (0: positive sign; 1: negative sign) SignY_G Roll axis (Y) angular rate sign. Default value: 0. (0: positive sign; 1: negative sign) SignZ_G Yaw axis (Z) angular rate sign. Default value: 0. (0: positive sign; 1: negative sign) Orient [2:0] 42/59 Directional user orientation selection. Default value: 000 DocID025604 Rev 3 Orient_0 LSM6DS0 7.15 Register description INT_GEN_SRC_G (14h) Angular rate sensor interrupt source register. Table 51. INT_GEN_SRC_G register 0 IA_G ZH_G ZL_G YH_G YL_G XH_G XL_G Table 52. INT_GEN_SRC_G register description 7.16 IA_G Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) ZH_G Yaw (Z) high. Default value: 0 (0: no interrupt, 1: Z high event has occurred) ZL_G Yaw (Z) low. Default value: 0 (0: no interrupt; 1: Z low event has occurred) YH_G Roll (Y) high. Default value: 0 (0: no interrupt, 1: Y high event has occurred) YL_G Roll (Y) low. Default value: 0 (0: no interrupt, 1: Y low event has occurred) XH_G Pitch (X) high. Default value: 0 (0: no interrupt, 1: X high event has occurred) XL_G Pitch (X) low. Default value: 0 (0: no interrupt, 1: X low event has occurred) OUT_TEMP_L (15h), OUT_TEMP_H (16h) Temperature data output register. L and H registers together express a 16-bit word in two’s complement right-justified. Table 53. OUT_TEMP_L register Temp7 Temp6 Temp5 Temp11 Temp11 Temp11 Temp4 Temp3 Temp2 Temp1 Temp0 Temp9 Temp8 Table 54. OUT_TEMP_H register Temp11 Temp11 Temp10 Table 55. OUT_TEMP register description Temp [11:0] Temperature sensor output data. The value is expressed as two’s complement sign extended to the MSB. DocID025604 Rev 3 43/59 59 Register description 7.17 LSM6DS0 STATUS_REG (17h) Status register. Table 56. STATUS_REG register 0 IG_XL IG_G INACT BOOT_ STATUS TDA GDA XLDA Table 57. STATUS_REG register description IG_XL Accelerometer interrupt output signal. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) IG_G Gyroscope interrupt output signal. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) INACT Inactivity interrupt output signal. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) BOOT_ STATUS Boot running flag signal. Default value: 0 (0: no boot running; 1: boot running) TDA Temperature sensor new data available. Default value: 0 (0: new data is not yet available; 1: new data is available) GDA Gyroscope new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) XLDA Accelerometer new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) 7.18 OUT_X_G (18h - 19h) Angular rate sensor pitch axis (X) angular rate output register. The value is expressed as a 16-bit word in two’s complement. 7.19 OUT_Y_G (1Ah - 1Bh) Angular rate sensor roll axis (Y) angular rate output register. The value is expressed as a 16-bit word in two’s complement. 7.20 OUT_Z_G (1Ch - 1Dh) Angular rate sensor yaw axis (Z) angular rate output register. The value is expressed as a 16-bit word in two’s complement. 44/59 DocID025604 Rev 3 LSM6DS0 7.21 Register description CTRL_REG4 (1Eh) Control register 4. Table 58. CTRL_REG4 register (1) 0 0 (1) Zen_G Yen_G Xen_G 0(1) LIR_XL1 4D_XL1 1. These bits must be set to ‘0’ for the correct operation of the device Table 59. CTRL_REG4 register description Zen_G Yen_G Xen_G LIR_XL1 Gyroscope’s yaw axis (Z) output enable. Default value: 1 (0: Z-axis output disabled; 1: Z-axis output enabled) Gyroscope’s roll axis (Y) output enable. Default value: 1 (0: Y-axis output disabled; 1: Y-axis output enabled) Gyroscope’s pitch axis (X) output enable. Default value: 1 (0: X-axis output disabled; 1: X-axis output enabled) Latched interrupt. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) 4D option enabled on interrupt. Default value: 0 4D_XL1 (0: interrupt generator uses 6D for position recognition; 1: interrupt generator uses 4D for position recognition) 7.22 CTRL_REG5_XL (1Fh) Linear acceleration sensor Control Register 5. Table 60. CTRL_REG5_XL register DEC_1 DEC_0 Zen_XL Yen_XL Xen_XL 0(1) 0(1) 0(1) 1. These bits must be set to ‘0’ for the correct operation of the device Table 61. CTRL_REG5_XL register description Decimation of acceleration data on OUT REG and FIFO. Default value: 00 (00: no decimation; DEC_ [0:1] 01: update every 2 samples; 10: update every 4 samples; 11: update every 8 samples) Zen_XL Yen_XL Xen_XL Accelerometer’s Z-axis output enable. Default value: 1 (0: Z-axis output disabled; 1: Z-axis output enabled) Accelerometer’s Y-axis output enable. Default value: 1 (0: Y-axis output disabled; 1: Y-axis output enabled) Accelerometer’s X-axis output enable. Default value: 1 (0: X-axis output disabled; 1: X-axis output enabled) DocID025604 Rev 3 45/59 59 Register description 7.23 LSM6DS0 CTRL_REG6_XL (20h) Linear acceleration sensor control register 6. Table 62. CTRL_REG6_XL register ODR_XL2 ODR_XL1 ODR_XL0 FS1_XL FS0_XL BW_SCAL _ODR BW_XL1 BW_XL0 Table 63. CTRL_REG6_XL register description ODR_XL [2:0] Output data rate and power mode selection. Default value: 000 (see Table 67) FS_XL [1:0] Accelerometer full-scale selection. Default value: 00 (00: ±2g; 01: ±16g; 10: ±4g; 11: ±8g) Bandwidth selection. Default value: 0 (0: bandwidth determined by ODR selection: - BW = 408 Hz when ODR = 952 Hz, 50 Hz, 10 Hz; BW_SCAL_ODR - BW = 211 Hz when ODR = 476 Hz; - BW = 105 Hz when ODR = 238 Hz; - BW = 50 Hz when ODR = 119 Hz; 1: bandwidth selected according to BW_XL [2:1] selection) Anti-aliasing filter bandwidth selection. Default value: 00 (00: 408 Hz; 01: 211 Hz; 10: 105 Hz; 11: 50 Hz) BW_XL [1:0] ODR_XL [2:0] is used to set the power mode and ODR selection. Table 64 summarizes all available frequencies when only the accelerometer is activated. Table 64. ODR register setting (accelerometer only mode) ODR_XL2 46/59 ODR_XL1 ODR_XL0 ODR selection [Hz] 0 0 0 Power-down 0 0 1 10 Hz 0 1 0 50 Hz 0 1 1 119 Hz 1 0 0 238 Hz 1 0 1 476 Hz 1 1 0 952 Hz 1 1 1 n.a. DocID025604 Rev 3 LSM6DS0 7.24 Register description CTRL_REG7_XL (21h) Linear acceleration sensor control register 7. Table 65. CTRL_REG7_XL register HR DCF1 DCF0 0(1) 0(1) 0(1) FDS HPIS1 1. These bits must be set to ‘0’ for the correct operation of the device Table 66. CTRL_REG7_XL register description High resolution mode for accelerometer enable. Default value: 0 (0: disabled; 1: enabled). Refer to Table 67. HR DCF[1:0] FDS Accelerometer digital filter (high-pass and low-pass) cutoff frequency selection: the bandwidth of the high-pass filter depends on the selected ODR. Refer to Table 67. Filtered data selection. Default value: 0 (0: internal filter bypassed; 1: data from internal filter sent to output register and FIFO) High-pass filter enabled for acceleration sensor interrupt function on interrupt. Default HPIS1 value: 0 (0: filter bypassed; 1: filter enabled) Table 67. Low pass cut-off frequency in high resolution mode (HR = 1) HR 7.25 CTRL_REG7 (DCF [1:0]) LP cutoff freq. [Hz] 1 00 ODR/50 1 01 ODR/100 1 10 ODR/9 1 11 ODR/400 CTRL_REG8 (22h) Control register 8. Table 68. CTRL_REG8 register BOOT BDU H_LACTIVE PP_OD SIM DocID025604 Rev 3 IF_ADD_INC BLE SW_RESET 47/59 59 Register description LSM6DS0 Table 69. CTRL_REG8 register description BOOT Reboot memory content. Default value: 0 (0: normal mode; 1: reboot memory content(1)) BDU Block Data Update. Default value: 0 (0: continuous update; 1: output registers not updated until MSB and LSB read) H_LACTIVE Interrupt activation level. Default value: 0 (0: interrupt output pins active high; 1: interrupt output pins active low) PP_OD Push-pull/Open Drain selection on INT pin. Default value: 0 (0: push-pull mode; 1: open drain mode) SIM SPI Serial Interface Mode selection. Default value: 0 (0: 4-wire interface; 1: 3-wire interface). IF_ADD_INC Register address automatically incremented during a multiple byte access with a serial interface (I2C or SPI). Default value: 1 (0: disabled; 1: enabled) BLE Big/Little Endian Data Selection. Default value 0 (0: data LSB @ lower address; 1: data MSB @ lower address) SW_RESET Software reset. Default value: 0 (0: normal mode; 1: reset device) 1. Boot request is executed as soon as the internal oscillator is turned-on. It is possible to set the bit while in power-down mode, in this case it will be served at the next normal mode or sleep mode. 7.26 CTRL_REG9 (23h) Control register 9. Table 70. CTRL_REG9 register 0(1) SLEEP_G 0(1) FIFO_ TEMP_EN DRDY_ mask_bit I2C_disable FIFO_EN STOP_ON _FTH 1. These bits must be set to ‘0’ for the correct operation of the device Table 71. CTRL_REG9 register description SLEEP_G Gyroscope sleep mode enable. Default value: 0 (0: disabled; 1: enabled) FIFO_TEMP_EN Temperature data storage in FIFO enable. Default value: 0 (0: temperature data not stored in FIFO; 1: temperature data stored in FIFO) DRDY_mask_bit Data available enable bit. Default value: 0 (0: DA timer disabled; 1: DA timer enabled) I2C_disable Disable I2C interface. Default value: 0. (0: both I2C and SPI enabled; 1: I2C disabled, SPI only) FIFO_EN FIFO memory enable. Default value: 0 (0: disabled; 1: enabled) STOP_ON_FTH Enable FIFO threshold level use. Default value: 0. (0: FIFO depth is not limited; 1: FIFO depth is limited to threshold level) 48/59 DocID025604 Rev 3 LSM6DS0 7.27 Register description CTRL_REG10 (24h) Control register 10. Table 72. CTRL_REG10 register (1) 0 (1) 0 0 (1) 0(1) 0(1) ST_G 0(1) ST_XL 1. These bits must be set to ‘0’ for the correct operation of the device Table 73. CTRL_REG10 register description 7.28 ST_G Angular rate sensor self-test enable. Default value: 0 (0: Self-test disabled; 1: Self-test enabled) ST_XL Linear acceleration sensor self-test enable. Default value: 0 (0: Self-test disabled; 1: Self-test enabled) INT_GEN_SRC_XL (26h) Linear acceleration sensor interrupt source register. Table 74. INT_GEN_SRC_XL register 0 IA_XL ZH_XL ZL_XL YH_XL YL_XL XH_XL XL_XL Table 75. INT_GEN_SRC_XL register description IA_XL Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) ZH_XL Accelerometer’s Z high event. Default value: 0 (0: no interrupt, 1: Z high event has occurred) ZL_XL Accelerometer’s Z low event. Default value: 0 (0: no interrupt; 1: Z low event has occurred) YH_XL Accelerometer’s Y high event. Default value: 0 (0: no interrupt, 1: Y high event has occurred) YL_XL Accelerometer’s Y low event. Default value: 0 (0: no interrupt, 1: Y low event has occurred) XH_XL Accelerometer’s X high event. Default value: 0 (0: no interrupt, 1: X high event has occurred) XL_XL Accelerometer’s X low event. Default value: 0 (0: no interrupt, 1: X low event has occurred) DocID025604 Rev 3 49/59 59 Register description 7.29 LSM6DS0 STATUS_REG (27h) Status register. Table 76. STATUS_REG register 0 IG_XL IG_G INACT BOOT_ STATUS TDA GDA XLDA Table 77. STATUS_REG register description IG_XL Accelerometer interrupt output signal. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) IG_G Gyroscope interrupt output signal. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) INACT Inactivity interrupt output signal. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) BOOT_ STATUS Boot running flag signal. Default value: 0 (0: no boot running; 1: boot running) TDA Temperature sensor new data available. Default value: 0 (0: new data is not yet available; 1: new data is available) GDA Gyroscope new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) XLDA Accelerometer new data available. Default value: 0 (0: a new set of data is not yet available; 1: a new set of data is available) 7.30 OUT_X_XL (28h - 29h) Linear acceleration sensor X-axis output register. The value is expressed as a 16-bit word in two’s complement. 7.31 OUT_Y_XL (2Ah - 2Bh) Linear acceleration sensor Y-axis output register. The value is expressed as a 16-bit word in two’s complement. 7.32 OUT_Z_XL (2Ch - 2Dh) Linear acceleration sensor Z-axis output register. The value is expressed as a 16-bit word in two’s complement. 50/59 DocID025604 Rev 3 LSM6DS0 7.33 Register description FIFO_CTRL (2Eh) FIFO control register. Table 78. FIFO_CTRL register FMODE2 FMODE1 FMODE0 FTH4 FTH3 FTH2 FTH1 FTH0 Table 79. FIFO_CTRL register description FMODE [2:0] FIFO mode selection bits. Default value: 000 For further details refer to Table 80. FTH [4:0] FIFO threshold level setting. Default value: 0 0000 Table 80. FIFO mode selection FMODE2 7.34 FMODE1 FMODE0 Mode 0 0 0 Bypass mode. FIFO turned off 0 0 1 FIFO mode. Stop collecting data when FIFO is full. 0 1 0 Reserved 0 1 1 Continuous mode until trigger is deasserted, then FIFO mode. 1 0 0 Bypass mode until trigger is deasserted, then Continuous mode. 1 1 0 Continuous mode. If the FIFO is full, the new sample overwrites the older sample. FIFO_SRC (2Fh) FIFO status control register. Table 81. FIFO_SRC register FTH OVRN FSS5 FSS4 FSS3 FSS2 FSS1 FSS0 Table 82. FIFO_SRC register description FTH FIFO threshold status. (0: FIFO filling is lower than threshold level; 1: FIFO filling is equal to or higher than the threshold level OVRN FIFO overrun status. (0: FIFO is not completely filled; 1: FIFO is completely filled and at least one sample has been overwritten) For further details refer to Table 83. FSS [5:0] Number of unread samples stored in FIFO. (000000: FIFO empty; 100000: FIFO full, 32 unread samples) For further details refer to Table 83. DocID025604 Rev 3 51/59 59 Register description LSM6DS0 Table 83. FIFO_SRC example: OVR/FSS details FTH 0 OVRN FSS5 FSS4 FSS3 FSS2 FSS1 FSS0 Description 0 0 0 0 0 0 0 FIFO empty 0 0 0 0 0 0 1 1 unread sample --(1) 0 1 0 0 0 0 0 32 unread sample 1 1 1 0 0 0 0 0 At least one sample has been overwritten (1) -- ... 1. When the number of unread samples in FIFO is greater than the threshold level set in register FIFO_CTRL (2Eh), the FTH value is ‘1’. 7.35 INT_GEN_CFG_G (30h) Angular rate sensor interrupt generator configuration register. Table 84. INT_GEN_CFG_G register AOI_G LIR_G ZHIE_G ZLIE_G YHIE_G YLIE_G XHIE_G XLIE_G Table 85. INT_GEN_CFG_G register description AOI_G AND/OR combination of gyroscope’s interrupt events. Default value: 0 (0: OR combination; 1: AND combination) LIR_G Latch gyroscope interrupt request. Default value: 0 (0: interrupt request not latched; 1: interrupt request latched) ZHIE_G Enable interrupt generation on gyroscope’s yaw (Z) axis high event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) ZLIE_G Enable interrupt generation on gyroscope’s yaw (Z) axis low event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold) YHIE_G Enable interrupt generation on gyroscope’s roll (Y) axis high event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) YLIE_G Enable interrupt generation on gyroscope’s roll (Y) axis low event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold) XHIE_G Enable interrupt generation on gyroscope’s pitch (X) axis high event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value higher than preset threshold) XLIE_G Enable interrupt generation on gyroscope’s pitch (X) axis low event. Default value: 0 (0: disable interrupt request; 1: interrupt request on measured angular rate value lower than preset threshold) 52/59 DocID025604 Rev 3 LSM6DS0 7.36 Register description INT_GEN_THS_X_G (31h - 32h) Angular rate sensor interrupt generator threshold registers. The value is expressed as a 15bit word in two’s complement. Table 86. INT_GEN_THS_XH_G register DCRM_G THS_G_ X14 THS_G_ X13 THS_G_ X12 THS_G_ X11 THS_G_ X10 THS_G_ X9 THS_G_ X8 THS_G_ X1 THS_G_ X0 Table 87. INT_GEN_THS_XL_G register THS_G_ X7 THS_G_ X6 THS_G_ X5 THS_G_ X4 THS_G_ X3 THS_G_ X2 Table 88. INT_GEN_THS_X_G register description Decrement or reset counter mode selection. Default value: 0 DCRM_G (0: Reset; 1: Decrement, as per counter behavior in Figure 22 and Figure 23) THS_G_X [14:0] 7.37 Angular rate sensor interrupt threshold on pitch (X) axis. Default value: 0000000 00000000 INT_GEN_THS_Y_G (33h - 34h) Angular rate sensor interrupt generator threshold registers. The value is expressed as a 15bit word in two’s complement. Table 89. INT_GEN_THS_YH_G register 0(1) THS_G_ Y14 THS_G_ Y13 THS_G_ Y12 THS_G_ Y11 THS_G_ Y10 THS_G_ Y9 THS_G_ Y8 THS_G_ Y1 THS_G_ Y0 1. This bit must be set to ‘0’ for the correct operation of the device Table 90. INT_GEN_THS_YL_G register THS_G_ Y7 THS_G_ Y6 THS_G_ Y5 THS_G_ Y4 THS_G_ Y3 THS_G_ Y2 Table 91. INT_GEN_THS_Y_G register description THS_G_Y [14:0] Angular rate sensor interrupt threshold on roll (Y) axis. Default value: 0000000 00000000 DocID025604 Rev 3 53/59 59 Register description 7.38 LSM6DS0 INT_GEN_THS_Z_G (35h - 36h) Angular rate sensor interrupt generator threshold registers. The value is expressed as 15bit word in two’s complement. Table 92. INT_GEN_THS_ZH_G register 0(1) THS_G_ Z14 THS_G_ Z13 THS_G_ Z12 THS_G_ Z11 THS_G_ Z10 THS_G_ Z9 THS_G_ Z8 THS_G_ Z1 THS_G_ Z0 1. This bit must be set to ‘0’ for the correct operation of the device Table 93. INT_GEN_THS_ZL_G register THS_G_ Z7 THS_G_ Z6 THS_G_ Z5 THS_G_ Z4 THS_G_ Z3 THS_G_ Z2 Table 94. INT_GEN_THS_Z_G register description THS_G_Z [14:0] 7.39 Angular rate sensor interrupt thresholds on yaw (Z) axis. Default value: 0000000 00000000 INT_GEN_DUR_G (37h) Angular rate sensor interrupt generator duration register. Table 95. INT_GEN_DUR_G register WAIT_G DUR_G6 DUR_G5 DUR_G4 DUR_G3 DUR_G2 DUR_G1 DUR_G0 Table 96. INT_GEN_DUR_G register description WAIT_G Exit from Interrupt Wait function enable. Default value: 0 (0: wait function off; 1: wait for DUR_G [6:0] samples before exiting interrupt) DUR_G [6:0] Enter/exit interrupt duration value. Default value: 000 0000 The DUR_G [6:0] bits set the minimum duration of the interrupt event to be recognized. Duration steps and maximum values depend on the ODR chosen. The WAIT_G bit has the following meaning: ‘0’: the interrupt falls immediately if the signal crosses the selected threshold ‘1’: if the signal crosses the selected threshold, the interrupt falls after a number of samples equal to the value of the duration counter register. For further details refer to Figure 22 and Figure 23. 54/59 DocID025604 Rev 3 LSM6DS0 Register description Figure 22. Wait bit disabled • Wait bit = ‘0’  Interrupt disabled as soon as condition is no longer valid (ex: Rate value below threshold) Rate (dps) 0 t(n) Rate Threshold Counter Duration Value t(n) Interrupt “Wait” Disabled t(n) Figure 23. Wait bit enabled • Wait bit = ‘1’  Interrupt disabled after duration sample (sort of hysteresis) Rate (dps) 0 t(n) Rate Threshold Counter Duration Value t(n) Interrupt “Wait” Enabled t(n) Duration value is the same used to validate interrupt DocID025604 Rev 3 55/59 59 Soldering information 8 LSM6DS0 Soldering information The LGA package is compliant with the ECOPACK®, RoHS and “Green” standard. It is qualified for soldering heat resistance according to JEDEC J-STD-020. Leave “Pin 1 Indicator” unconnected during soldering. Land pattern and soldering recommendations are available at www.st.com/mems. 56/59 DocID025604 Rev 3 LSM6DS0 9 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Figure 24. LGA 3x3x0.86 16L package outline and dimensions Dimensions are in millimeter unless otherwise specified General Tolerance is +/-0.1mm unless otherwise specified OUTER DIMENSIONS ITEM Length [L] W idth [W ] Height [H] DIMENSION [mm] 3.00 3.00 0.86 DocID025604 Rev 3 TOLERANCE [mm] ±0.1 ±0.1 MA X 57/59 59 Revision history 10 LSM6DS0 Revision history Table 97. Document revision history Date Revision 28-Nov-2013 1 Initial release 2 Updated Vdd to 2.2 V in Section 2: Module specifications Updated SW_RESET bit in Table 69: CTRL_REG8 register description Updated dimensions and revised package presentation in Section 9: Package information 3 Document status promoted from preliminary to production data Added ±16 g linear acceleration full scale throughout datasheet Updated footnote 2 of Table 2: Pin description Updated Figure 20: LSM6DS0 electrical connections 31-Mar-2014 03-Nov-2014 58/59 Changes DocID025604 Rev 3 LSM6DS0 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID025604 Rev 3 59/59 59