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M24C04-MN6

M24C04-MN6

  • 厂商:

    STMICROELECTRONICS(意法半导体)

  • 封装:

    SO-8_4.9X3.9MM

  • 描述:

    IC EEPROM 4KBIT I2C 400KHZ 8SO

  • 数据手册
  • 价格&库存
M24C04-MN6 数据手册
M24C04-W M24C04-R M24C04-F Datasheet 4-Kbit serial I²C bus EEPROMs Features • SO8N (MN) TSSOP8 (DW) 150 mil width 169 mil width • • UFDFPN8 (MC) UFDFPN5 (MH) DFN8 - 2 x 3 mm DFN5 - 1.7 x 1.4 mm • Product status link • M24C04-W M24C04-R M24C04-F • • • • • Compatible with following I2C bus modes: – 400 kHz – 100 kHz Memory array: – 4 Kbit (512 byte) of EEPROM – Page size: 16 byte Single supply voltage: – M24C04-W: 2.5 V to 5.5 V – M24C04-R: 1.8 V to 5.5 V – M24C04-F: 1.7 V to 5.5 V 1.6 V to 5.5 V (under temperature constraint) Write: – Byte write within 5 ms – Page write within 5 ms Operating temperature range: – from -40 °C up to +85 °C Random and sequential read modes Write protect of the whole memory array Enhanced ESD/latch-Up protection More than 4 million write cycles More than 200-years data retention Packages Packages RoHS-compliant and Halogen-free • SO8N (ECOPACK2) • TSSOP8 (ECOPACK2) • UFDFPN8 (ECOPACK2) • UFDFPN5 (ECOPACK2) DS9387 - Rev 6 - June 2022 For further information contact your local STMicroelectronics sales office. www.st.com M24C04-W M24C04-R M24C04-F Description 1 Description The M24C04 is a 4-Kbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as 512 × 8 bits. The M24C04-W can be accessed with a supply voltage from 2.5 V to 5.5 V, the M24C04-R can be accessed with a supply voltage from 1.8 V to 5.5 V, and the M24C04-F can be accessed either with a supply voltage from 1.7 V to 5.5 V (over the full temperature range) or with an extended supply voltage from 1.6 V to 5.5 V under some restricted conditions. All these devices operate with a clock frequency of 400 kHz, over an ambient temperature range of -40 °C / +85 °C. Figure 1. Logic diagram VCC 2 E2-E1 SDA M24xxx SCL WC VSS Table 1. Signal names Signal name Function Direction E2, E1(1) Chip enable Input SDA Serial data I/O SCL Serial clock Input WC Write control Input VCC Supply voltage - VSS Ground - 1. Signal not connected in the DFN5 package. Figure 2. 8-pin package connections, top view NC E1 E2 V SS 1. 2. DS9387 - Rev 6 1 2 3 4 8 7 6 5 V CC WC SCL SDA NC: not connected. See Section 9 Package information for package dimensions, and how to identify pin 1 page 2/40 M24C04-W M24C04-R M24C04-F Description Figure 3. UFDFPN5 (DFN5) package connections 1. DS9387 - Rev 6 VCC 1 VSS 2 SDA 3 ABCD XYZW 5 WC 5 1 2 VSS 2 2 4 SCL 4 3 Top view Bottom view (marking side) (pads side) Inputs E2 and E1 are not connected. Refer to Section 4.5 Device addressing for further explanations. page 3/40 M24C04-W M24C04-R M24C04-F Signal description 2 Signal description 2.1 Serial clock (SCL) The signal applied on the SCL input is used to strobe the data available on SDA(in) and to output the data on SDA(out). 2.2 Serial data (SDA) SDA is an input/output used to transfer data in or data out of the device. SDA(out) is an open drain output that may be wired-AND with other open drain or open collector signals on the bus. A pull-up resistor must be connected from serial data (SDA) to VCC (Figure 11 indicates how to calculate the value of the pull-up resistor). 2.3 Chip enable (E1, E2) These input signals are used to set the value that is to be looked for on the two bits (b3, b2) of the 7-bit device select code. These inputs must be tied to VCC or VSS to establish the device select code as shown in Table 6. When not connected (left floating), these inputs are read as low (0, 0). For the UFDFPN5 package, the (E1,E2) inputs are not connected. 2.4 Write control (WC) This input signal is useful for protecting the entire contents of the memory from inadvertent write operations. Write operations are disabled to the entire memory array when write control (WC) is driven high. Write operations are enabled when write control (WC) is either driven low or left floating. When write control (WC) is driven high, device select and address bytes are acknowledged, data bytes are not acknowledged. 2.5 VSS (ground) VSS is the reference for all signals, including the VCC supply voltage. 2.6 Supply voltage (VCC) 2.6.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8 DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW). DS9387 - Rev 6 page 4/40 M24C04-W M24C04-R M24C04-F Supply voltage (VCC) 2.6.2 Power-up conditions The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). 2.6.3 Device reset In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8 DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it. 2.6.4 Power-down conditions During power-down (continuous decrease in VCC), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress). DS9387 - Rev 6 page 5/40 M24C04-W M24C04-R M24C04-F Block diagram 3 Block diagram The block diagram of the device is described below. Figure 4. Block diagram SENSE AMPLIFIERS DATA REGISTER PAGE LATCHES X DECODER ARRAY SDA I/O CONTROL LOGIC WC E1, E2 Y DECODER SCL START & STOP DETECT HV GENERATOR + SEQUENCER ADDRESS REGISTER DS9387 - Rev 6 page 6/40 M24C04-W M24C04-R M24C04-F Device operation 4 Device operation The device supports the I2C protocol. This is summarized in Figure 5. Any device that sends data on to the bus is defined to be a transmitter, and any device that reads the data to be a receiver. The device that controls the data transfer is known as the bus master, and the other as the slave device. A data transfer can only be initiated by the bus master, which also provides the serial clock for synchronization. The device is always a slave in all communications. Figure 5. I2C bus protocol SCL SDA SDA Input START Condition SCL 1 SDA MSB 2 SDA Change STOP Condition 3 7 8 9 ACK START Condition SCL 1 SDA MSB 2 3 7 8 9 ACK STOP Condition DS9387 - Rev 6 page 7/40 M24C04-W M24C04-R M24C04-F Start condition 4.1 Start condition Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start condition must precede any data transfer instruction. The device continuously monitors (except during a write cycle) serial data (SDA) and serial clock (SCL) for a start condition. 4.2 Stop condition Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A stop condition terminates communication between the device and the bus master. A read instruction that is followed by NoAck can be followed by a stop condition to force the device into the standby mode. A stop condition at the end of a write instruction triggers the internal write cycle. 4.3 Data input During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data (SDA) signal must change only when serial clock (SCL) is driven low. 4.4 Acknowledge bit (ACK) The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits. DS9387 - Rev 6 page 8/40 M24C04-W M24C04-R M24C04-F Device addressing 4.5 Device addressing To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the device select code, shown in Table 2 (most significant bit first). Note: When using the DFN5 package: • • The E1 and E2 pins are not accessible. To properly communicate with the device, the E1 and E2 bits must always be set to logic 0 for any operation. See Table 2. • No other I2C device using address 1010 xxxx (x = don't care) can be connected to the same bus. Table 2. Device select code Package Device type identifier(1) Chip Enable address RW b7 b6 b5 b4 b3 b2 b1 b0 TSSOP8,SO8N, UFDFPN8 1 0 1 0 E2 E1 A8 RW DFN5 1 0 1 0 0 0 A8 RW 1. The MSB, b7, is sent first. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for read and 0 for write operations. If a match occurs on the device select code, the corresponding device gives an acknowledgement on serial data (SDA) during the 9th bit time. If the device does not match the device select code, it deselects itself from the bus, and goes into standby mode. DS9387 - Rev 6 page 9/40 M24C04-W M24C04-R M24C04-F Instructions 5 Instructions 5.1 Write operations Following a start condition the bus master sends a device select code with the R/W bit (RW) reset to 0. The device acknowledges this, as shown in Figure 6, and waits for the address byte. The device responds to each address byte with an acknowledge bit, and then waits for the data byte. Table 3. Address byte A7 A6 A5 A4 A3 A2 A1 A0 When the bus master generates a stop condition immediately after a data byte Ack bit (in the “10th bit” time slot), either at the end of a byte write or a page write, the internal write cycle tW is triggered. A stop condition at any other time slot does not trigger the internal write cycle. After the stop condition and the successful completion of an internal write cycle (tW), the device internal address counter is automatically incremented to point to the next byte after the last modified byte. During the internal write cycle, serial data (SDA) is disabled internally, and the device does not respond to any requests. If the write control input (WC) is driven high, the write instruction is not executed and the accompanying data bytes are not acknowledged, as shown in Figure 7. DS9387 - Rev 6 page 10/40 M24C04-W M24C04-R M24C04-F Write operations 5.1.1 Byte write After the device select code and the address byte, the bus master sends one data byte. If the addressed location is write-protected, by write control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not write-protected, the device replies with Ack. The bus master terminates the transfer by generating a stop condition, as shown in Figure 6. Figure 6. Write mode sequences with WC = 0 (data write enabled) WC ACK ACK Data in Stop Byte address Dev Select Start Byte Write ACK R/W WC ACK Dev Select Start Page Write ACK Byte address ACK Data in 1 ACK Data in 2 Data in 3 R/W WC (cont'd) ACK Data in N Stop Page Write(cont'd) ACK DS9387 - Rev 6 page 11/40 M24C04-W M24C04-R M24C04-F Write operations 5.1.2 Page write The page write mode allows up to 16 byte to be written in a single write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits, A8/A4, are the same. If more bytes are sent than fit up to the end of the page, a “roll-over” occurs, i.e. the bytes exceeding the page end are written on the same page, from location 0. The bus master sends from 1 to 16 byte of data, each of which is acknowledged by the device if write control (WC) is low. If write control (WC) is high, the contents of the addressed memory location are not modified, and each data byte is followed by a NoAck, as shown in Figure 7. After each transferred byte, the internal page address counter is incremented. The transfer is terminated by the bus master generating a stop condition. Figure 7. Write mode sequences with WC = 1 (data write inhibited) WC ACK Byte address NO ACK Data in Stop Dev select Start Byte Write ACK R/W WC ACK Dev select Start Page Write ACK Byte address NO ACK Data in 1 NO ACK Data in 2 Data in 3 R/W WC (cont'd) NO ACK Data in N Stop Page Write(cont'd) NO ACK AI02803d_dita DS9387 - Rev 6 page 12/40 M24C04-W M24C04-R M24C04-F Write operations 5.1.3 Minimizing write delays by polling on ACK The maximum write time (tw) is shown in AC characteristics tables in Section 8 DC and AC parameters, but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 8, is: • • • Initial condition: a write cycle is in progress. Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction). Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1). Figure 8. Write cycle polling flowchart using ACK Write cycle in progress Start condition Device select with RW = 0 NO ACK returned YES First byte of instruction with RW = 0 already decoded by the device NO Next operation is addressing the memory YES Send address and receive ACK Re-start Stop 1. DS9387 - Rev 6 NO StartCondition YES Data for the write operation Device select with RW = 1 Continue the write operation Continue the random read operation The seven most significant bits of the device select code of a random read (bottom right box in the Figure 8) must be identical to the seven most significant bits of the device select code of the write (polling instruction in the Figure 8). page 13/40 M24C04-W M24C04-R M24C04-F Read operations 5.2 Read operations Read operations are performed independently of the state of the write control (WC) signal. After the successful completion of a read operation, the device internal address counter is incremented by one, to point to the next byte address. For the read instructions, after each byte read (data out), the device waits for an acknowledgement (data in) during the 9th bit time. If the bus master does not acknowledge during this 9th time, the device terminates the data transfer and switches to its standby mode after a stop condition. Figure 9. Read mode sequences ACK Data out Stop Start Dev select R/W ACK Start Dev select * Byte address R/W ACK Sequential Current Read Dev select * NO ACK Data out R/W ACK ACK Data out 1 NO ACK Data out N Stop Start Dev select R/W ACK Start Dev select * ACK Byte address R/W ACK ACK Dev select * Start Sequential Random Read ACK Start Random Address Read ACK Stop Current Address Read NO ACK ACK Data out 1 R/W NO ACK Stop Data out N Note: DS9387 - Rev 6 The seven most significant bits of the first device select code of a random read must be identical to the seven most significant bits of the device select code of the write. page 14/40 M24C04-W M24C04-R M24C04-F Read operations 5.2.1 Random address read A dummy write is first performed to load the address into this address counter (as shown in Figure 9) but without sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a stop condition. 5.2.2 Current address read For the current address read operation, following a start condition, the bus master only sends a device select code with the R/W bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in Figure 9, without acknowledging the byte. 5.2.3 Sequential read This operation can be used after a current address read or a random address read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 9. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h. Note: DS9387 - Rev 6 For device delivered in DFN5 package, after the last memory address (1FFh), the address counter doesn't roll-over to the memory address 00h. The next addresses and data bytes outputted are therefore undefined and not guarantee. The address counter contains meaningful address value only after a random address read (with address value between 0 and 1FE) has been performed. page 15/40 M24C04-W M24C04-R M24C04-F Initial delivery state 6 Initial delivery state The device is delivered with all the memory array bits set to 1 (each byte contains FFh). DS9387 - Rev 6 page 16/40 M24C04-W M24C04-R M24C04-F Maximum rating 7 Maximum rating Stressing the device outside the ratings listed in Table 4 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Absolute maximum ratings Symbol Min. Max. Unit Ambient operating temperature -40 130 °C TSTG Storage temperature –65 150 °C TLEAD Lead temperature during soldering - Parameter IOL DC output current (SDA = 0) VIO see note (1) °C – 5 mA Input or output range –0.50 6.5 V VCC Supply voltage -0.50 6.5 V VESD Electrostatic pulse (human body model)(2) – 3000 V 1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions of Hazardous Substances (RoHS directive 2011/65/EU of July 2011). 2. Positive and negative pulses applied on different combinations of pin connections, according to ANSI/ESDA/JEDEC JS-001 (C1=100 pF, R1=1500 Ω). DS9387 - Rev 6 page 17/40 M24C04-W M24C04-R M24C04-F DC and AC parameters 8 DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 5. Operating conditions (voltage range W) Symbol Min. Max. Unit Supply voltage 2.5 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 400 kHz Min. Max. Unit Supply voltage 1.8 5.5 V TA Ambient operating temperature –40 85 °C fC Operating clock frequency - 400 kHz VCC Parameter Table 6. Operating conditions (voltage range R) Symbol VCC Parameter Table 7. Operating conditions (voltage range F) Symbol VCC TA fC Parameter Min. Max. Unit V Supply voltage 1.60 1.65 1.70 5.5 Ambient operating temperature: READ -40 -40 -40 85 Ambient operating temperature: WRITE 0 -20 -40 85 Operating clock frequency - - - 400 °C kHz Table 8. AC measurement conditions Symbol Min. Max. Unit Load capacitance 0 100 pF - SCL input rise/fall time, SDA input fall time - 50 ns - Input levels 0.2 VCC to 0.8 VCC V - Input and output timing reference levels 0.3 VCC to 0.7 VCC V Cbus Parameter Figure 10. AC measurement I/O waveform Input voltage levels 0.8VCC 0.2VCC DS9387 - Rev 6 Input and output Timing reference levels 0.7VCC 0.3V CC page 18/40 M24C04-W M24C04-R M24C04-F DC and AC parameters Table 9. Input parameters Parameter(1) Symbol Test condition Min. Max. Unit CIN Input capacitance (SDA) - - 8 pF CIN Input capacitance (other pins) - - 6 pF VIN < 0.3 VCC 15 70 kΩ VIN > 0.7 VCC 500 - kΩ ZL Input impedance (WC) ZH 1. Evaluated by characterization – Not tested in production. Table 10. Cycling performance Symbol Ncycle Parameter Write cycle endurance(1) Test condition Max. TA ≤ 25 °C, VCC(min) < VCC < VCC(max) 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) 1,200,000 Unit Write cycle 1. A write cycle is executed when either a page write or a byte write instruction is decoded. Table 11. Memory cell data retention Parameter Data retention(1) Test condition TA = 55 °C Min. Unit 200 Year 1. The data retention behaviour is checked in production, while the 200-year limit is defined from characterization and qualification results. DS9387 - Rev 6 page 19/40 M24C04-W M24C04-R M24C04-F DC and AC parameters Table 12. DC characteristics (M24C04-W) Symbol ILI Parameter Input leakage current (E2, E1, SCL, SDA) Test conditions (in addition to those in Table 5 and Table 8) Min. Max. Unit VIN = VSS or VCC, device in standby mode - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA ICC Supply current (Read) fC = 400 kHz, 2.5 V ≤ VCC ≤ 5.5 V - 1 mA ICC0(1) Supply current (Write) - 0.5 mA - 2 μA - 3 μA - –0.45 0.3 VCC V - 0.7 VCC VCC+1 V - 0.4 V During tW, 2.5 V ≤ VCC ≤ 5.5 V Device not selected(2), ICC1 Standby supply current VIN = VSS or VCC, VCC = 2.5 V Device not selected(2), VIN = VSS or VCC, VCC = 5.5 V VIL VIH VOL Input low voltage (SCL, SDA, WC) Input high voltage (SCL, SDA, WC) Output low voltage IOL = 2.1 mA, VCC = 2.5 V or IOL = 3 mA, VCC = 5.5 V 1. Evaluated by characterization - Not tested in production. 2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). DS9387 - Rev 6 page 20/40 M24C04-W M24C04-R M24C04-F DC and AC parameters Table 13. DC characteristics (M24C04-R) Symbol ILI Parameter Input leakage current (E2, E1, SCL, SDA) Test conditions(1) (in addition to those in Table 6 and Table 8) VIN = VSS or VCC, device in standby mode ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC ICC Supply current (Read) ICC0(2) Supply current (Write) ICC1 Standby supply current VIL 1.8 V ≤ VCC ≤ 2.5 V Device not selected,(3) VIN = VSS or VCC, VCC = 1.8 V Unit - ±2 µA - ±2 µA - 0.8 mA - 0.5 mA - 1 µA 2.5 V ≤ VCC -0.45 0.3 VCC (SCL, SDA, WC) VCC < 2.5 V -0.45 0.25 VCC VCC < 2.5 V 0.75 VCC 6.5 VCC < 2.5 V 0.75 VCC VCC + 0.6 (SCL, SDA) Input high voltage (WC) VOL During tW Max. Input low voltage Input high voltage VIH VCC = 1.8 V, fc= 400 kHz Min. Output low voltage IOL = 0.7 mA, VCC = 1.8 V - V V 0.2 V V 1. If the application uses the voltage range R device with 2.5 V ≤ Vcc ≤ 5.5 V and -40 °C < TA < +85 °C, refer to Table 12 instead of this table. 2. Evaluated by characterization - Not tested in production. 3. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). DS9387 - Rev 6 page 21/40 M24C04-W M24C04-R M24C04-F DC and AC parameters Table 14. DC characteristics (M24C04-F) Symbol ILI Parameter Test conditions(1) (in addition to those in Table 7 and Table 8) Input leakage current VIN = VSS or VCC (E2, E1, SCL, SDA) device in Standby mode Min. Max. Unit - ±2 µA ILO Output leakage current SDA in Hi-Z, external voltage applied on SDA: VSS or VCC - ±2 µA ICC Supply current (Read) VCC = 1.6 V or 1.7 V, fc= 400 kHz - 0.8 mA ICC0(2) Supply current (Write) - 0.5 mA ICC1 Standby supply current - 1 µA VIL Device not selected(3), VIN = VSS or VCC, VCC ≤ 1.8 V 2.5 V ≤ VCC -0.45 0.3 VCC (SCL, SDA, WC) VCC < 2.5 V -0.45 0.25 VCC VCC < 2.5 V 0.75 VCC 6.5 VCC < 2.5 V 0.75 VCC VCC + 0.6 (SCL, SDA) Input high voltage (WC) VOL VCC ≤ 1.8 V Input low voltage Input high voltage VIH During tW Output low voltage IOL = 0.7 mA, VCC = 1.8 V - V V 0.2 V V 1. If the application uses the voltage range F device with 2.5 V ≤ VCC ≤ 5.5 V , refer to Table 12 instead of this table. 2. Evaluated by characterization - Not tested in production. 3. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the internal write cycle tW (tW is triggered by the correct decoding of a write instruction). DS9387 - Rev 6 page 22/40 M24C04-W M24C04-R M24C04-F DC and AC parameters Table 15. 400 kHz AC characteristics (I2C Fast-mode) Symbol Alt. Min. Max. Unit fC fSCL Clock frequency - 400 kHz tCHCL tHIGH Clock pulse width high 600 - ns tCLCH tLOW Clock pulse width low 1300 - ns tF SDA (out) fall time 20(2) 300 ns tXH1XH2 tR Input signal rise time (3) (3) ns tXL1XL2 tF Input signal fall time (3) (3) ns tDXCH tSU:DAT Data in set up time 100 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX(4) tDH Data out hold time 100 - ns tCLQV(5) tAA Clock low to next data valid (access time) - 900 ns tCHDL tSU:STA Start condition setup time 600 - ns tDLCL tHD:STA Start condition hold time 600 - ns tCHDH tSU:STO Stop condition set up time 600 - ns tDHDL tBUF Time between Stop condition and next Start condition 1300 - ns tW tWR Write time - 5 ms Pulse width ignored (input filter on SCL and SDA) - single glitch - 100 ns tQL1QL2 (1) tNS (1) - Parameter 1. Evaluated by characterization - Not tested in production. 2. With CL = 10 pF. 3. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz. 4. The min value for tCLQX (data out hold time) of the M24xxx devices offers a safe timing to bridge the undefined region of the falling edge SCL. 5. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that Rbus × Cbus time constant is within the values specified in Figure 11. DS9387 - Rev 6 page 23/40 M24C04-W M24C04-R M24C04-F DC and AC parameters Table 16. 100 kHz AC characteristics (I2C standard-mode) Symbol Alt. fC fSCL tCHCL Parameter Min. Max. Unit Clock frequency - 100 kHz tHIGH Clock pulse width high 4 - μs tCLCH tLOW Clock pulse width low 4.7 - μs tXH1XH2 tR Input signal rise time - 1 μs tXL1XL2 tF Input signal fall time - 300 ns tQL1QL2(1) tF SDA (out) fall time - 300 ns tDXCH tSU:DAT Data in setup time 250 - ns tCLDX tHD:DAT Data in hold time 0 - ns tCLQX(2) tDH Data out hold time 200 - ns tCLQV(3) tAA Clock low to next data valid (access time) - 3450 ns tCHDL(4) tSU:STA Start condition setup time 4.7 - μs tDLCL tHD:STA Start condition hold time 4 - μs tCHDH tSU:STO Stop condition setup time 4 - μs tDHDL tBUF Time between Stop condition and next Start condition 4.7 - μs tW tWR Write time - 5 ms tNS(1) - Pulse width ignored (input filter on SCL and SDA), single glitch - 100 ns 1. Evaluated by characterization - Not tested in production. 2. To avoid spurious start ands top conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. 3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming that the Rbus × Cbus time constant is within the values specified in Figure 11. 4. For a reStart condition, or following a write cycle. DS9387 - Rev 6 page 24/40 M24C04-W M24C04-R M24C04-F DC and AC parameters Figure 11. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz Bus line pull-up resistor (kΩ) 100 Rb us xC bu 10 4k VCC The Rbus x Cbus time constant must be below the 400 ns time constant line represented on the left. s =4 Here Rbus x Cbus = 120 ns 00 Rbus I²C bus master ns SCL M24xxx SDA Cbus 1 10 30 100 1000 Bus line capacitor (pF) Figure 12. AC waveforms Start condition Start Stop condition condition tXL1XL2 tXH1XH2 tCHCL tCLCH SCL tDLCL tXL1XL2 SDA In tCHDL tXH1XH2 SDA Input tCLDX SDA tDXCH Change tCHDH tDHDL WC tDHWH tWLDL Stop condition Start condition SCL SDA In tW tCHDH tCHDL Write cycle tCHCL SCL tCLQV SDA Out DS9387 - Rev 6 tCLQX Data valid tQL1QL2 Data valid page 25/40 M24C04-W M24C04-R M24C04-F Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 UFDFPN5 (DFN5) package information UFDFPN5 is a 5-lead, 1.7 × 1.4 mm, 0.55 mm thickness, ultra thin fine pitch dual flat package. Figure 13. UFDFPN5 - Outline Package UFDFN5 (package code A0UK) D k L Pin 1 Pin 1 b X E E1 Y D1 Top view (marking side) e L1 Bottom view (pads side) A A1 Side view 1. 2. 3. 4. DS9387 - Rev 6 A0UK_UFDFN5_ME_V3 Maximum package warpage is 0.05 mm. Exposed copper is not systematic and can appear partially or totally according to the cross section. Drawing is not to scale. On the bottom side, pin 1 is identified by the specific pad shape and, on the top side, pin 1 is defined from the orientation of the marking. When reading the marking, pin 1 is below the upper left package corner. page 26/40 M24C04-W M24C04-R M24C04-F UFDFPN5 (DFN5) package information Table 17. UFDFPN5 - Mechanical data Symbol millimeters inches Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 - 0.050 0.0000 - 0.0020 b(1) 0.175 0.200 0.225 0.0069 0.0079 0.0089 D 1.600 1.700 1.800 0.0630 0.0669 0.0709 D1 1.400 1.500 1.600 0.0551 0.0591 0.0630 E 1.300 1.400 1.500 0.0512 0.0551 0.0591 E1 0.175 0.200 0.225 0.0069 0.0079 0.0089 X - 0.200 - - 0.0079 - Y - 0.200 - - 0.0079 - e - 0.400 - - 0.0157 - L 0.500 0.550 0.600 0.0197 0.0217 0.0236 L1 - 0.100 - - 0.0039 - k - 0.400 - - 0.0157 - 1. Dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from the terminal tip. 9.1.1 UFDFPN5 recommended footprint Figure 14. UFDFPN5 - Recommended footprint Pin 1 0.400 0.600 0.200 0.200 0.200 0.200 0.400 1.600 1. DS9387 - Rev 6 Dimensions are expressed in millimeters. page 27/40 M24C04-W M24C04-R M24C04-F UFDFPN8 (DFN8) package information 9.2 UFDFPN8 (DFN8) package information This UFDFPN is a 8-lead, 2 x 3 mm, 0.5 mm pitch ultra thin profile fine pitch dual flat package. Figure 15. UFDFPN8 - Outline D N A B Package UFDFN8 (package code ZW) A ccc C Pin #1 ID marking E A1 C eee C Seating plane A3 Side view 2x aaa C 1 aaa C 2x 2 Top view D2 e 1 2 L3 Datum A b L1 L L3 Pin #1 ID marking E2 K e/2 L1 e Terminal tip L Detail “A” Even terminal ND-1 x e See Detail “A” Bottom view 1. 2. 3. 4. DS9387 - Rev 6 Maximum package warpage is 0.05 mm. Exposed copper is not systematic and can appear partially or totally according to the cross section. Drawing is not to scale. The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating (not connected) in the end application. page 28/40 M24C04-W M24C04-R M24C04-F UFDFPN8 (DFN8) package information Table 18. UFDFPN8 - Mechanical data Symbol inches(1) millimeters Min Typ Max Min Typ Max A 0.450 0.550 0.600 0.0177 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 b(2) 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 1.900 2.000 2.100 0.0748 0.0787 0.0827 D2 1.200 - 1.600 0.0472 - 0.0630 E 2.900 3.000 3.100 0.1142 0.1181 0.1220 E2 1.200 - 1.600 0.0472 - 0.0630 e - 0.500 - - 0.0197 - K 0.300 - - 0.0118 - - L 0.300 - 0.500 0.0118 - 0.0197 L1 - - 0.150 - - 0.0059 L3 0.300 - - 0.0118 - - aaa - - 0.150 - - 0.0059 bbb - - 0.100 - - 0.0039 ccc - - 0.100 - - 0.0039 ddd - - 0.050 - - 0.0020 eee(3) - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring. 9.2.1 UFDFPN8 recommended footprint Figure 16. UFDFPN8 - Recommended footprint 1.600 0.500 0.300 0.600 1.600 1.400 1. DS9387 - Rev 6 Dimensions are expressed in millimeters. page 29/40 M24C04-W M24C04-R M24C04-F TSSOP8 package information 9.3 TSSOP8 package information This TSSOP is an 8-lead, 3 x 6.4 mm, 0.65 mm pitch, thin shrink small outline package. Figure 17. TSSOP8 – Outline D 8 Package TSSOP8 (package code 6P) 5 k E1 E A1 1 L L1 4 A2 A c 1. 6P_TSSOP8_ME_V3 e b Drawing is not to scale. Table 19. TSSOP8 – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.200 - - 0.0472 A1 0.050 - 0.150 0.0020 - 0.0059 A2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 D(2) 2.900 3.000 3.100 0.1142 0.1181 0.1220 e - 0.650 - - 0.0256 - E 6.200 6.400 6.600 0.2441 0.2520 0.2598 E1(3) 4.300 4.400 0.0177 0.1693 0.1732 0.1772 L 0.450 0.600 0.750 0.0181 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0° - 8° 0° - 8° aaa - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: DS9387 - Rev 6 The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. page 30/40 M24C04-W M24C04-R M24C04-F TSSOP8 package information 9.3.1 TSSOP8 recommended footprint Figure 18. TSSOP8 – Recommended footprint 1.55 0.65 0.40 2.35 5.80 7.35 1. DS9387 - Rev 6 6P_TSSOP8_FP_V2 Dimensions are expressed in millimeters. page 31/40 M24C04-W M24C04-R M24C04-F SO8N package information 9.4 SO8N package information This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 19. SO8N – Outline Package SO8N (package code O7) A2 h x 45˚ A c b ccc e D 0.25 mm GAUGE PLANE SEATING PLANE C k 8 E1 E 1 L A1 L1 1. Drawing is not to scale. Table 20. SO8N – Mechanical data Symbol inches (1) millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.750 - - 0.0689 A1 0.100 - 0.250 0.0039 - 0.0098 A2 1.250 - - 0.0492 - - b 0.280 - 0.480 0.0110 - 0.0189 c 0.100 - 0.230 0.0030 - 0.0091 D(2) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e - 1.270 - - 0.0500 - h 0.250 - 0.500 0.0098 - 0.0197 k 0° - 8° 0° - 8° L 0.400 - 1.270 0.0157 - 0.0500 L1 - 1.040 - - 0.0409 - ccc - - 0.100 - - 0.0039 1. Values in inches are converted from mm and rounded to four decimal digits. 2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side 3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm per side. Note: DS9387 - Rev 6 The package top may be smaller than the package bottom. Dimensions D and E1 are determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interleads flash, but including any mismatch between the top and bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom side. page 32/40 M24C04-W M24C04-R M24C04-F SO8N package information 9.4.1 SO8N recommended footprint Figure 20. SO8N - Recommended footprint 3.9 6.7 0.6 (x8) 1.27 1. DS9387 - Rev 6 Dimensions are expressed in millimeters. page 33/40 M24C04-W M24C04-R M24C04-F Ordering information 10 Ordering information Table 21. Ordering information scheme Example: M24 C04 -W MC 6 T P Device type M24 = I2C serial access EEPROM Device function C04 =4 Kbit (512 x 8 bit) Operating voltage W = VCC = 2.5 V to 5.5 V R = VCC = 1.8 V to 5.5 V F = VCC = 1.6 or 1.7 V to 5.5 V Package(1) MN = SO8N (150 mil width) DW = TSSOP8 (169 mil width) MC = UFDFPN8 (DFN8) MH = UFDFPN5 (DFN5) Device grade 6 = Industrial: device tested with standard test flow over -40 to 85 °C Option T = Tape and reel packing blank = tube packing Plating technology P or G = RoHS compliant and halogen-free (ECOPACK2) 1. All packages are ECOPACK2 (RoHS-compliant and free of brominated, chlorinated and antimony-oxide flame retardants). Note: For a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact your nearest ST sales office. Note: Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DS9387 - Rev 6 page 34/40 M24C04-W M24C04-R M24C04-F Revision history Table 22. Document revision history Date Revision Changes New single product M24C04 datasheet resulting from splitting the previous datasheet M24C08-x M24C04-x M24C02-x M24C01-x (revision 18) into separate datasheets. 17-Dec-2012 1 Updated ESD value in Table 14. Updated standby supply current values (ICCI) in Table 32, Table 33 and Table 35. 24-Jan-2013 2 Updated M24C04-F single supply voltage value in Features and Supply current (Read) value in Table 32. Updated: 12-Sep-2013 3 • M24C04-F single supply voltage value in Features • Note (2) under Table 14: Absolute maximum ratings • Section 5.1.2: Page Write Added “ICC0 Supply current (Write)” in Table 32: DC characteristics (M24128-BWvoltage range W, device grade 6), Table 33: DC characteristics (voltage range M24128M24128BR, M24128-DR device grade 6) and Table 35: DC characteristics (M24C32M24C02-F, device grade 6 and grade 5). Added: Table 17: Operating conditions (voltage range F, for devices identified by process letter T), Table 18: Operating conditions (voltage range F, for all other devices), Table 29: Cycling performance and Table 30: Memory cell data retention. Renamed Figure 52 and Table 59. Added: UFDFPN5 in cover page and in Section 9: Package information, note 1 on Table 1: Signal names, Figure 3: UFDFPN5 (DFN5) package connections, Engineering samples reference. 04-May-2017 02-Oct-2017 4 5 Updated: • Section 2.3: Chip Enable (E1, E2), Section 2.6.2: Power-up conditions, Section 4.5: Device addressing, Section 5.2.3: Sequential Read. • Table 2: Device select code, Table 23: Ordering information scheme. Added reference to DFN8 and DFN5 in: Figure 3: UFDFPN5 (DFN5) package connections, Section 9.1: UFDFPN5 (DFN5) package information, Section 9.2: UFDFPN8 (DFN8) package information. Updated Table 4: Absolute maximum ratings, Figure 9: Read mode sequences, Table 23: Ordering information scheme. Updated: 16-Jun-2022 6 • Section Features, Section 1 Description, Section 2.2 Serial data (SDA), Section 2.3 Chip enable (E1, E2), Section 3 Block diagram, Section 4.5 Device addressing, Section 5.1.3 Minimizing write delays by polling on ACK, Section 5.2 Read operations, Section 9.1 UFDFPN5 (DFN5) package information, Section 9.4 SO8N package information, Section 9.3 TSSOP8 package information, Section 9.2 UFDFPN8 (DFN8) package information, Section 10 Ordering information • Table 4. Absolute maximum ratings, title of Table 7. Operating conditions (voltage range F), note in Table 9. Input parameters and in Table 10. Cycling performance and in Table 11. Memory cell data retention , Table 12. DC characteristics (M24C04-W), Table 13. DC characteristics (M24C04-R), Table 14. DC characteristics (M24C04-F), Table 15. 400 kHz AC characteristics (I2C Fast-mode), Table 16. 100 kHz AC characteristics (I2C standard-mode) Removed PDIP8 package DS9387 - Rev 6 page 35/40 M24C04-W M24C04-R M24C04-F Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Chip enable (E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.4 Write control (WC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.5 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.6.1 Operating supply voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 4.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 Data input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.4 Acknowledge bit (ACK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.5 Device addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.1 5.2 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.1.2 Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.3 Minimizing write delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.1 Random address read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.2 Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2.3 Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 7 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 8 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 9 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 9.1 UFDFPN5 (DFN5) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1.1 DS9387 - Rev 6 UFDFPN5 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 page 36/40 M24C04-W M24C04-R M24C04-F Contents 9.2 UFDFPN8 (DFN8) package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.2.1 9.3 TSSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.3.1 9.4 TSSOP8 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SO8N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.4.1 10 UFDFPN8 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SO8N recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 DS9387 - Rev 6 page 37/40 M24C04-W M24C04-R M24C04-F List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . Device select code . . . . . . . . . . . . . . . Address byte . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . Operating conditions (voltage range W) Operating conditions (voltage range R) . Operating conditions (voltage range F) . AC measurement conditions . . . . . . . . Input parameters . . . . . . . . . . . . . . . . Cycling performance . . . . . . . . . . . . . Memory cell data retention . . . . . . . . . DC characteristics (M24C04-W). . . . . . DC characteristics (M24C04-R) . . . . . . DC characteristics (M24C04-F) . . . . . . Table 15. 400 kHz AC characteristics (I2C Fast-mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. 100 kHz AC characteristics (I2C standard-mode) UFDFPN5 - Mechanical data . . . . . . . . . . . . . . UFDFPN8 - Mechanical data . . . . . . . . . . . . . . TSSOP8 – Mechanical data . . . . . . . . . . . . . . SO8N – Mechanical data . . . . . . . . . . . . . . . . Ordering information scheme. . . . . . . . . . . . . . Document revision history . . . . . . . . . . . . . . . . DS9387 - Rev 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 9 10 17 18 18 18 18 19 19 19 20 21 22 24 27 29 30 32 34 35 page 38/40 M24C04-W M24C04-R M24C04-F List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Logic diagram. . . . . . . . . . . . . . . . . . . 8-pin package connections, top view . . . UFDFPN5 (DFN5) package connections Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write mode sequences with WC = 0 (data write enabled) . Write mode sequences with WC = 1 (data write inhibited). Write cycle polling flowchart using ACK . . . . . . . . . . . . . Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 12 13 14 18 Figure 11. Maximum Rbus value versus bus parasitic capacitance (Cbus) for an I2C bus at maximum frequency fC = 400 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 UFDFPN5 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 UFDFPN5 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 UFDFPN8 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 UFDFPN8 - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TSSOP8 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TSSOP8 – Recommended footprint. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SO8N – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SO8N - Recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. DS9387 - Rev 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3 6 page 39/40 M24C04-W M24C04-R M24C04-F IMPORTANT NOTICE – READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgment. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2022 STMicroelectronics – All rights reserved DS9387 - Rev 6 page 40/40
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