M36D0R6040T0ZAI

M36D0R6040T0 M36D0R6040B0 64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 64 Mbit (4Mb x 16) Flash Memory – 1 die of 16 Mbit (1Mb x 16) Pseudo SRAM ■ SUPPLY VOLTAGE – VDDF = VDDP = 1.7V to 1.95V ■ LOW POWER CONSUMPTION ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Device Code (Top Flash Configuration), M36D0R6040T0: 8810h – Device Code (Bottom Flash Configuration), M36D0R6040B0: 8811h ■ PACKAGE – Compliant with Lead-Free Soldering Processes – Lead-Free Versions FLASH MEMORY ■ PROGRAMMING TIME – 8µs by Word typical for Fast Factory Program – Double/Quadruple Word Program option – Enhanced Factory Program options ■ MEMORY BLOCKS – Multiple Bank Memory Array: 4 Mbit Banks – Parameter Blocks (Top location) ■ ASYNCHRONOUS READ – Asynchronous Page Read mode – Random Access: 70ns ■ DUAL OPERATIONS – Program Erase in one Bank while Read in others – No delay between Read and Write operations ■ BLOCK LOCKING – All blocks locked at Power-up – Any combination of blocks can be locked – WPF for Block Lock-Down ■ Figure 1. Package FBGA Stacked TFBGA67 (ZAI) 12 x 8mm SECURITY – 128-bit user programmable OTP cells – 64-bit unique device number ■ COMMON FLASH INTERFACE (CFI) ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK PSRAM ■ ACCESS TIME: 70ns ■ LOW STANDBY CURRENT: 110µA ■ DEEP POWER DOWN CURRENT: 10µA ■ December 2004 1/18 M36D0R6040T0, M36D0R6040B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A20-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Chip Enable (EF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Output Enable (GF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Enable (WF).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Write Protect (WPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Flash Reset (RPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Chip Enable (E1P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Chip Enable (E2P).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Output Enable (GP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Write Enable (WP).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Upper Byte Enable (UBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PSRAM Lower Byte Enable (LBP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VDDP Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VPPF Program Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VSS Ground.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Main Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FLASH MEMORY COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PSRAM COMPONENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/18 M36D0R6040T0, M36D0R6040B0 Table 5. Table 6. Table 7. Table 8. Table 9. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PSRAM DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Stacked TFBGA67 12x8mm - 8x8 active ball array, 0.8mm pitch, Package Outline . . . 15 Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data . 15 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 11. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3/18 M36D0R6040T0, M36D0R6040B0 SUMMARY DESCRIPTION The M36D0R6040T0 and M36D0R6040B0 combine two memory devices in a Multi-Chip Package: a 64-Mbit, Multiple Bank Flash memory, the M58WR064FT/B, and a 16-Mbit Pseudo SRAM, the M69AR024B. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA67 (12 x 8mm, 8x8 ball array, 0.8mm pitch) package. In addition to the standard version, the packages are also available in Lead-free version, in compliance with JEDEC Std J-STD-020B, the ST ECOPACK 7191395 Specification, and the RoHS (Restriction of Hazardous Substances) directive. All packages are compliant with Lead-free soldering processes. The memory is supplied with all the bits erased (set to ‘1’). Figure 2. Logic Diagram VPPF VDDF 22 A0-A21 DQ0-DQ15 EF GF WF RPF WPF E1P GP WP E2P UBP LBP M36D0R6040T M36D0R6040B WP E2P UBP LBP Write Enable input Power-down input Upper Byte Enable input Lower Byte Enable input Table 1. Signal Names A0-A19 DQ0-DQ15 VDDF VPPF VSS VDDP NC Common Address Inputs Common Data Input/Output Flash Memory Power Supply Common Flash Optional Supply Voltage for Fast Program & Erase Ground PSRAM Power Supply Not Connected Internally Flash Memory Signals A21-A20 EF GF WF RPF Address Inputs for the Flash memory only Chip Enable input Output Enable input Write Enable input Reset input Write Protect input VDDP 16 WPF PSRAM Signals E1P GP Chip Enable input Output Enable input VSS AI09200 4/18 1 2 3 4 5 6 7 8 9 10 11 12 A NC NC NC A12 A20 A11 A15 A13 VSSF NC A14 NC B DQ14 DQ7 A16 A8 A9 DQ15 WP A10 C A21 WF DQ4 NC DQ13 DQ6 DQ5 D VSSP RPF DQ12 E2P VDDP VDDF Figure 3. TFBGA Connections (Top view through package) E WPF VPPF A19 DQ11 DQ10 DQ2 DQ3 F LBP UBP GP DQ9 DQ8 DQ0 DQ1 G A18 A17 A7 A6 A3 A2 A1 E1P H NC NC NC A5 A4 A0 EF VSSF GF NC NC NC M36D0R6040T0, M36D0R6040B0 AI09201 5/18 M36D0R6040T0, M36D0R6040B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A19). Addresses A0-A19 are common inputs for the Flash Memory and PSRAM components. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory internal state machine and they select the cells to access in the PSRAM. The Flash memory is accessed through the Chip Enable signal (EF) and through the Write Enable (WF) signal, while the PSRAM is accessed through two Chip Enable signals (E1P and E2P) and the Write Enable signal (WP). Address Inputs (A20-A21). Addresses A20-A21 are inputs for the Flash Memory component only. The Flash Memory is accessed through the Chip Enable signals (EF) and through the Write Enable (WF) signal. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. Flash Chip Enable (EF). The Chip Enable inputs activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. Flash Output Enable (GF). The Output Enable pins control data outputs during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR064F(T/B) datasheet). Flash Reset (RPF). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 7., Flash Memory DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 8., Flash Memory DC Characteristics - Voltages). asserted PSRAM Chip Enable (E1P). When (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. PSRAM Chip Enable (E2P). The Chip Enable, E2P, puts the device in Deep Power-down mode when it is driven Low. This is the lowest power mode. PSRAM Output Enable (GP). The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. PSRAM Write Enable (WP). The Write Enable, WP, controls the Bus Write operation of the memory’s Command Interface. PSRAM Upper Byte Enable (UBP). The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. PSRAM Lower Byte Enable (LBP). The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VDDF Supply Voltage. VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supplies for all Flash memory operations (Read, Program and Erase). VDDP Supply Voltage. The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed. VPPF Program Supply Voltage. VPPF is both a Flash Memory control input and a Flash Memory power supply pin. The two functions are selected by the voltage range applied to the pin. 6/18 M36D0R6040T0, M36D0R6040B0 If VPPF is kept in a low voltage range (0V to VDDF) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1F enables these functions (see Tables 7 and 8, DC Characteristics for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS is the common ground reference for all voltage measurements in the Flash (core and I/O Buffers) and PSRAM chips. Note: Each Flash memory device in a system should have its supply voltage (VDDF) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Table 5., AC Measurement Load Circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. 7/18 M36D0R6040T0, M36D0R6040B0 FUNCTIONAL DESCRIPTION The Flash memory and PSRAM components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1P and E2P for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The Figure 4. Functional Block Diagram VDDF VPPF most common example is simultaneous read operations on the Flash memory and the PSRAM, which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. A20-A21 EF GF WF RPF A0-A19 WPF 64 Mbit Flash Memory DQ0-DQ15 VDDP E1P GP WP E2P UBP LBP 16 Mbit PSRAM VSS AI09204 8/18 M36D0R6040T0, M36D0R6040B0 Table 2. Main Operating modes Operation Flash Read Flash Write Flash Address Latch Flash Output Disable Flash Standby Flash Reset PSRAM Read Flash Memory must be disabled PSRAM Write Output Disable PSRAM Standby PSRAM Deep Power-Down Note: 1. 2. 3. 4. EF VIL VIL VIL VIL VIH X GP VIL VIH X VIH X X WP VIH VIL VIH VIH X X LF VIL(2) VIL(2) VIL X X X RPF VIH VIH VIH VIH VIH VIL WAITF(4) E1P E2P GP WP UBP LBP DQ15-DQ0 Flash Data Out PSRAM must be disabled Flash Data In Flash Data Out or Hi-Z (3) Flash Hi-Z Hi-Z Hi-Z VIL VIL VIL Any PSRAM mode is allowed Flash Hi-Z Flash Hi-Z VIH VIH VIH VIH VIL VIL VIH VIH X X VIH VIL VIH X X VIL VIL X X X VIL VIL X X X PSRAM data out PSRAM data in PSRAM Hi-Z PSRAM Hi-Z PSRAM Hi-Z Any Flash mode is allowed. VIH X X = Don't care. LF can be tied to VIH if the valid address has been previously latched. Depends on GF. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064F(T/B) datasheet for details. 9/18 M36D0R6040T0, M36D0R6040B0 FLASH MEMORY COMPONENT The M36D0R6040T0 and M36D0R6040B0 contain a 64Mbit Flash memory, the M58WR064F(T/ B). The burst mode of this device is not available in the M36D0R6040(T/B). For detailed information on how to use the Flash memory, see the M58WR064F(T/B) datasheet which is available from your local STMicroelectronics distributor. PSRAM COMPONENT The M36D0R6040T0 and M36D0R6040B0 contain a 16Mbit PSRAM. For detailed information on how to use it, see the M69AR024B datasheet which is available from the internet site http:// www.st.com or from your local STMicroelectronics distributor. 10/18 M36D0R6040T0, M36D0R6040B0 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 3. Absolute Maximum Ratings Value Symbol TA TBIAS TSTG TLEAD VIO VDDF VDDP VPPF IO tVPPFH Parameter Min Ambient Operating Temperature Temperature Under Bias Storage Temperature Lead Temperature during Soldering Input or Output Voltage Flash Memory Core Supply Voltage PSRAM Supply Voltage Flash Memory Program Voltage Output Short Circuit Current Time for VPPF at VPPFH –0.5 –0.2 –0.2 –0.2 –30 –40 –65 Max 85 125 155 (1) plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Unit °C °C °C °C V V V V mA hours VDD(1)+0.6 2.45 3.3 14 100 100 Note: 1. VDDF = VDDP = VDD. 2. Compliant with the JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. 11/18 M36D0R6040T0, M36D0R6040B0 DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and AC Measurement Conditions Flash Memory Parameter Min VDDF Supply Voltage VDDP Supply Voltage 1.7 – 11.4 –0.4 –40 30 5 0 to VDD VDD/2 0 to VDD VDD/2 Max 1.95 – 12.6 VDDF +0.4 85 Min – 1.7 – – –30 50 Max – 1.95 – – 85 V V V V °C pF ns V V PSRAM Unit VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages(1) Input and Output Timing Ref. Voltages(1) Note: 1. VDDF = VDDP = VDD. Figure 5. AC Measurement I/O Waveform Table 5. AC Measurement Load Circuit VDD VDD VDD/2 0V VDDF 16.7kΩ DEVICE UNDER TEST 0.1µF CL 16.7kΩ AI09202 Note: VDDF = VDDP = VDD. CL includes JIG capacitance I09203 Note: VDDF = VDDP = VDD. Table 6. Device Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 12 15 Unit pF pF Note: Sampled only, not 100% tested. 12/18 M36D0R6040T0, M36D0R6040B0 Table 7. Flash Memory DC Characteristics - Currents Symbol ILI ILO IDD1 IDD2 IDD3 IDD4 Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=6MHz) Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Program) IDD5 (1) Supply Current (Erase) VPPF = VDDF Supply Current IDD6 (1,2) (Dual Operations) IDD7(1) Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program) IPP1(1) VPPF Supply Current (Erase) IPP2 IPP3(1) VPPF Supply Current (Read) VPPF Supply Current (Standby) Program/Erase in one Bank, Asynchronous Read in another Bank EF = VDDF ± 0.2V VPPF = VPPH VPPF = VDDF VPPF = VPPH VPPF = VDDF VPPF ≤ VDDF VPPF ≤ VDDF 10 13 20 26 mA mA VPPF = VDDF VPPF = VPPH 10 8 20 15 mA mA Test Condition 0V ≤ VIN ≤ VDDF 0V ≤ VOUT ≤ VDDF EF = VIL, GF = VIH RPF = VSSF ± 0.2V EF = VDDF ± 0.2V EF = VIL, GF = VIH VPPF = VPPH 3 10 10 10 8 Min Typ Max ±1 ±1 6 50 50 50 15 Unit µA µA mA µA µA µA mA 10 2 0.2 2 0.2 0.2 0.2 50 5 5 5 5 5 5 µA mA µA mA µA µA µA Note: 1. Sampled only, not 100% tested. 2. VDDF Dual Operation current is the sum of read and program or erase currents. Table 8. Flash Memory DC Characteristics - Voltages Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPPF Program Voltage-Logic VPPF Program Voltage Factory Program or Erase Lockout VDDF Lock Voltage RPF pin Extended High Voltage 1 3.3 IOL = 100µA IOH = –100µA Program, Erase Program, Erase VDDF –0.1 1 11.4 1.8 12 3.3 12.6 0.4 Test Condition Min –0.5 VDDF –0.4 Typ Max 0.4 VDDF + 0.4 0.1 Unit V V V V V V V V V 13/18 M36D0R6040T0, M36D0R6040B0 Table 9. PSRAM DC Characteristics Symbol ICC1 VCC Active Current ICC2 ILI ILO IPD Input Leakage Current Output Leakage Current Deep Power Down Current Parameter Test Condition VDDP = 1.95V, VIN = VIH or VIL, E1P = VIL and E2P = VIH, IOUT = 0mA 0V ≤ VIN ≤ VDDP 0V ≤ VOUT ≤ VDDP VDDP = 1.95V, E1P ≥ VDDP – 0.2V or E1P ≤ VIL, VIN ≥ VDDP – 0.2V or VIN ≤ 0.2V VDDP = 1.95V, E1P = E2P ≥ VDDP – 0.2V, IOUT = 0mA 0.8VDDP –0.3 IOH = –0.5mA IOL = 1mA VDDP – 0.2 0.2 tAVAV Read / tAVAV Write = minimum tAVAV Read / tAVAV Write = maximum –1 –1 Min Max 20 Unit mA 3 1 1 10 mA µA µA µA ISB Standby Supply Current CMOS Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage 110 VDDP + 0.2 0.4 µA VIH (1) VIL (2) VOH VOL V V V V Note: 1. The maximum DC voltage on input and I/O pins is VDDP+0.2V. During voltage transitions, inputs may overshoot VDDP by 1.0V for periods of up to 5ns. 2. The minimum DC voltage on input or I/O pins is –0.3V. During voltage transitions, inputs may undershoot VSS by 1.0V for periods of up to 5ns. 14/18 M36D0R6040T0, M36D0R6040B0 PACKAGE MECHANICAL Figure 6. Stacked TFBGA67 12x8mm - 8x8 active ball array, 0.8mm pitch, Package Outline D D2 D1 SE E E1 BALL "A1" b e FE FD1 FD A SD e ddd A2 A1 BGA-Z41 Note: Drawing is not to scale. Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, 0.8mm pitch, Package Mechanical Data Symbol Symbol A A1 A2 b D D1 D2 ddd E E1 e FD FD1 FE SD SE 8.000 5.600 0.800 3.200 1.600 1.200 0.400 0.400 7.900 – – – – – – – 0.810 0.400 12.000 5.600 8.800 0.350 11.900 – – 0.450 12.100 – – 0.100 8.100 – – – – – – – 0.3150 0.2205 0.0315 0.1260 0.0630 0.0472 0.0157 0.0157 0.3110 – – – – – – – 0.200 0.0319 0.0157 0.4724 0.2205 0.3465 0.0138 0.4685 – – 0.0177 0.4764 – – 0.0039 0.3189 – – – – – – – millimeters Typ Typ Min Min Max Max 1.200 0.0079 Typ Typ inches Min Min Max Max 0.0472 15/18 M36D0R6040T0, M36D0R6040B0 PART NUMBERING Table 11. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture D = Multiple Bank, Page mode Flash 2 Architecture 0 = none present Operating Voltage R = VDDF = VDDP = 1.7V to 1.95V Flash 1 Density 6 = 64 Mbit Flash 2 Density 0 = none present RAM 1 Density 4 = 16 Mbit RAM 0 Density 0 = none present Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 0 = 0.13µm Flash technology, 70ns; 0.18µm RAM, 70ns speed Package ZAI = Stacked TFBGA67 12 x 8mm - 8x8 active ball array, 0.8mm pitch Option Blank = Standard Packing T = Tape & Reel Packing E = Lead-Free and RoHS Package, Standard Packing F = Lead-Free and RoHS Package, Tape & Reel Packing M36 D 0 R 6 0 4 0 T 0 ZAI T Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 16/18 M36D0R6040T0, M36D0R6040B0 REVISION HISTORY Table 12. Document Revision History Date 26-Nov-2003 Version 1.0 First Issue Document status promoted from Target Specification to full Datasheet. TFBGA67 package fully compliant with the ST ECOPACK specification. Flash memory and PSRAM data updated to the revision 5.0 of the M58WR064F(T/B) datasheet and to the revision 6.0 of the M69AR024B datasheet. Revision Details 07-Dec-2003 2.0 17/18 M36D0R6040T0, M36D0R6040B0 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. ECOPACK is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 18/18