M74HC670

M74HC670 4 WORD x 4 BIT REGISTER FILE (3 STATE) s s s s s s s HIGH SPEED : tPD = 22 ns (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 670 DIP SOP TSSOP ORDER CODES PACKAGE DIP SOP TSSOP TUBE M74HC670B1R M74HC670M1R T&R M74HC670RM13TR M74HC670TTR DESCRIPTION The M74HC670 is an high speed CMOS 4WORD x 4 BIT REGISTER FILE (3 STATE) fabricated with silicon gate C2MOS technology. The M74HC670 is 4 x 4 Register File organized as four words by four bits. Separate read and write inputs, both address and enable, allow simultaneous read and write operation. The 3-state outputs make it possible to connect up to 128 outputs to increase the word capacity up to 512 words. Any number of these devices can be operated in parallel to generate an n-bit length. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS August 2001 1/11 M74HC670 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 5, 4 10, 9, 7, 6 11 12 14, 13 15, 1, 2, 3 8 16 SYMBOL RA, RB Q1 to Q4 RE WE WA, WB D1 to D4 GND Vcc NAME AND FUNCTION Read Address Inputs Data Outputs 3 - State Output Read Enable Input Write Enable Input (Active LOW) Write Address Inputs Data Inputs Ground (0V) Positive Supply Voltage WRITE FUNCTION TABLE WRITE INPUTS WB L L H H X WA L H L H X WE L L L L H 0 Q=D Q0 Q0 Q0 Q0 1 Q0 Q=D Q0 Q0 Q0 WORDS 2 Q0 Q0 Q=D Q0 Q0 3 Q0 Q0 Q0 Q=D Q0 READ FUNCTION TABLE READ INPUTS RB L L H H X RA L H L H X RE L L L L H Q0 W0B1 W1B1 W2B1 W3B1 Z Q1 W0B2 W1B2 W2B2 W3B2 Z OUTPUTS Q2 W0B3 W1B3 W2B3 W3B3 Z Q3 W0B4 W1B4 W2B4 W3B4 Z X : Don’t Care Z : High Impedance (Q = D) = The four select internal flip-flop outputs will assume the states applied to the four external data inputs. Q0 = The level of Q before the indicated input conditions were established. W0B1 = The firs bit of word 0, etc. 2/11 M74HC670 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 ± 20 ± 20 ± 25 ± 50 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW °C °C ICC or IGND DC VCC or Ground Current Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C 3/11 M74HC670 RECOMMENDED OPERATING CONDITIONS Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V °C ns ns ns DC SPECIFICATIONS Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II IOZ Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current 6.0 6.0 6.0 IO=-20 µA IO=-20 µA IO=-20 µA IO=-4.0 mA IO=-5.2 mA IO=20 µA IO=20 µA IO=20 µA IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VIH or VIL VO = VCC or GND VI = VCC or GND TA = 25°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 ± 0.1 ± 0.5 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 ±1 ±5 40 Typ. Max. Value -40 to 85°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 ±1 ±5 80 µA µA µA V V Max. -55 to 125°C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit VIH High Level Input Voltage Low Level Input Voltage High Level Output Voltage VIL V VOH ICC 4/11 M74HC670 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25°C Min. Typ. 30 8 7 96 24 20 108 27 23 104 26 22 42 13 11 25 13 11 16 4 3 12 3 3 Max. 75 15 13 185 37 31 220 44 37 185 37 31 110 22 19 95 19 16 75 15 13 50 10 9 0 0 0 5 5 5 5 5 5 Value -40 to 85°C Min. Max. 95 19 16 230 46 39 275 55 47 230 46 39 140 28 24 120 24 20 95 19 16 65 13 11 0 0 0 5 5 5 5 5 5 -55 to 125°C Min. Max. 110 22 19 280 56 48 330 66 56 280 56 48 165 33 28 145 29 25 110 22 19 75 15 13 0 0 0 5 5 5 5 5 5 ns Unit tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (RA, RB - Qn) tPLH tPHL Propagation Delay Time (WE - Qn) tPLH tPHL Propagation Delay Time (Dn - Qn) tPZL tPZH High Impedance Output Enable Time tPLZ tPHZ High Impedance Output Disable Time tW(L) Minimum Pulse Width (WE) Minimum Set-up Time (Dn -WE) (WA, WB - WE) Minimum Hold Time (Dn - WE) Minimum Hold Time (WA, WB - WE) Minimum Latch Time (WE - RA, RB) ns ns ns RL = 1 KΩ ns RL = 1 KΩ ns ns ts ns th ns th ns tlatch ns CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25°C Min. Typ. 5 96 Max. 10 Value -40 to 85°C Min. Max. 10 -55 to 125°C Min. Max. 10 pF pF Unit CIN CPD Input Capacitance Power Dissipation Capacitance (note 1) 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC 5/11 M74HC670 TEST CIRCUIT TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) SWITCH Open VCC GND WAVEFORM 1 : PROPAGATION DELAY, MINIMUM PULSE WIDTH, SETUP AND HOLD TIME, MINIMUM LATCH TIME (f=1MHz; 50% duty cycle) 6/11 M74HC670 WAVEFORM 2 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) W AVEFORM 3 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) 7/11 M74HC670 Plastic DIP-16 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch P001C 8/11 M74HC670 SO-16 MECHANICAL DATA DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8° (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45° (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010 PO13H 9/11 M74HC670 TSSOP16 MECHANICAL DATA mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0° 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8° 0.75 0° 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8° 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch A A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080338D 10/11 M74HC670 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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