M74HCT374B1R

M74HCT374 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 50 MHz (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 DESCRIPTION The M74HCT374 is an high speed CMOS OCTAL D-TYPE FLIP FLOP WITH 3-STATE OUTPUTS NON INVERTING fabricated with silicon gate C2MOS technology. This 8 bit D-TYPE FLIP FLOP is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic state that were setup at the D inputs. While the OE input is at low level, the eight outputs will be in a normal logic state (high or low logic level) and while OE is at high level the outputs will be in a high impedance state. ) (s t c u d o r P e DIP PACKAGE TUBE t e l o s b O TSSOP u d o r P e ORDER CODES DIP SOP TSSOP ) s ( ct SOP M74HCT374B1R M74HCT374M1R T&R M74HCT374RM13TR M74HCT374TTR The output control does not affect the internal operation of flip-flops; that is, the old data can be retained or the new data can be entered even while the outputs are off. The M74HCT374 is designed to directly interface HSC2MOS systems with TTL and NMOS components. All inputs are equipped with protection circuits against static discharge and transient excess voltage. t e l o s b O PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/11 M74HCT374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 OE 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 Q0 to Q7 3 State Output Enable Input (Active LOW) 3 State Outputs D0 to D7 Data Inputs 10 20 GND VCC CK NAME AND FUNCTION TRUTH TABLE Clock Input (LOW to HIGH, edge triggered) Ground (0V) Positive Supply Voltage u d o INPUTS OE CK H X OUTPUT D X e t e ol L X L bs L X: Don’t Care Z: High Impedance O ) LOGIC DIAGRAM s ( t c u d o r P e t e l o s b O This logic diagram has not be used to estimate propagation delays 2/11 ) s ( ct Pr Q Z NO CHANGE L L H H M74HCT374 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA ± 70 mA 500(*) mW VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V ) s ( t -65 to +150 300 c u d °C °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/°C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC e t e l Parameter Supply Voltage o s b VI Input Voltage VO Output Voltage Top Operating Temperature tr, tf Input Rise and Fall Time (VCC = 4.5 to 5.5V) s ( t c O ) o r P Value Unit 4.5 to 5.5 V 0 to VCC V 0 to VCC V -55 to 125 °C 0 to 500 ns u d o r P e t e l o s b O 3/11 M74HCT374 DC SPECIFICATION Test Condition Symbol VIH Parameter High Level Input Voltage VIL Low Level Input Voltage VOH VOL II IOZ ICC ∆ ICC TA = 25°C VCC (V) Min. 4.5 to 5.5 4.5 to 5.5 High Level Output Voltage 4.5 Low Level Output Voltage 4.5 Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Value Typ. Max. 2.0 -40 to 85°C -55 to 125°C Min. Min. Max. 2.0 0.8 4.4 4.5 4.4 4.4 IO=-6.0 mA 4.18 4.31 4.13 4.10 0.1 IO=6.0 mA 0.17 0.26 5.5 VI = VCC or GND ± 0.1 5.5 VI = VIH or VIL VO = VCC or GND 5.5 VI = VCC or GND 5.5 Per Input pin VI = 0.5V or VI = 2.4V Other Inputs at VCC or GND IO = 0 ) (s 0.1 V (s) ct u d o 0.33 V 0.8 IO=-20 µA 0.0 Max. 2.0 0.8 IO=20 µA Unit 0.1 0.40 V V ±1 ±1 µA ± 0.5 ±5 ± 10 µA 4 40 80 µA 2.0 2.9 3.0 mA r P e t e l o s b O t c u d o r AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Symbol P e Parameter t e l o tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (CLOCK-Q,Q) s b O tPZL tPZH Output Enable Time tPLZ tPHZ Output Disable Time fMAX Maximum Clock Frequency tW(L) Minimum Pulse Width (CLOCK) tW(H) ts th 4/11 Minimum Set-Up Time Minimum Hold Time Test Condition VCC (V) CL (pF) 4.5 Value TA = 25°C Min. -40 to 85°C -55 to 125°C Min. Min. Typ. Max. 50 7 12 15 18 4.5 4.5 4.5 4.5 50 150 50 150 20 25 17 25 30 38 30 38 38 48 38 48 45 57 45 57 4.5 50 16 28 35 42 4.5 50 4.5 50 15 19 23 ns 4.5 50 15 19 23 ns 4.5 50 0 0 0 ns RL = 1 KΩ RL = 1 KΩ 31 50 Max. Unit 25 Max. 21 ns ns ns ns MHz M74HCT374 CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter CIN Input Capacitance COUT Output Capacitance Power Dissipation Capacitance (note 1) CPD Value TA = 25°C VCC (V) Min. Typ. Max. 5 10 -40 to 85°C -55 to 125°C Min. Min. Max. Unit Max. 10 10 pF 10 pF 48 pF ) s ( ct 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip Flop) and the CPD when n pcs of Flip Flop operate, can be gained by the following equation: CPD(TOTAL) = 30 + 18 x n (pF) u d o TEST CIRCUIT r P e t e l o ) (s s b O t c u d o r P e tPLH, tPHL let tPZL, tPLZ tPZH, tPHZ o s b TEST SWITCH Open VCC GND CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) O 5/11 M74HCT374 WAVEFORM 1: CK TO Qn PROPAGATION DELAYS, MAXIMUM CK FREQUENCY, Dn TO CK SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 6/11 s b O M74HCT374 WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O WAVEFORM 3: MINIMUM PULSE WIDTH (CK) (f=1MHz; 50% duty cycle) t c u d o r P e t e l o s b O 7/11 M74HCT374 Plastic DIP-20 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.254 B 1.39 TYP MAX. MIN. TYP. MAX. 0.010 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 D ) s ( ct 25.4 E 8.5 e 2.54 e3 22.86 u d o 0.335 7.1 I 3.93 s ( t c 1.34 e t e ol bs O ) 3.3 Z Pr 0.100 F L 1.000 0.900 0.280 0.155 0.130 0.053 u d o r P e t e l o s b O P001J 8/11 M74HCT374 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. a1 2.65 MAX. 0.1 0.104 0.2 a2 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0.5 0.019 ) s ( ct 0.012 0.020 c1 u d o 45° (typ.) D 12.60 13.00 0.496 E 10.00 10.65 0.393 e 1.27 e3 11.43 F 7.40 7.60 L 0.50 1.27 M ) (s S e t e ol s b O 0.75 Pr 0.512 0.419 0.050 0.450 0.291 0.300 0.020 0.050 0.029 8° (max.) t c u d o r P e t e l o s b O PO13L 9/11 M74HCT374 TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 c 0.09 0.20 0.004 D 6.4 6.5 6.6 0.252 E 6.2 6.4 6.6 0.244 E1 4.3 4.4 4.48 1 e bs 0.65 BSC K 0° L 0.45 let o s b 0.60 s ( t c 0.75 du ro P e A2 A1 b 0.260 0.252 0.260 0.173 0.176 0.0256 BSC 0° 8° 0.018 0.024 O K e 0.030 L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 10/11 0.0089 0.256 u d o r P e A O ) 8° 0.012 t e l o 0.169 ) s ( ct M74HCT374 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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