M74HCT646RM13TR

M74HCT646 OCTAL BUS TRANSCEIVER/REGISTER WITH 3 STATE OUTPUTS ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 60 MHz (TYP.) at VCC = 4.5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS : VIH = 2V (MIN.) VIL = 0.8V (MAX) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 646 DESCRIPTION The 74HCT646 is an advanced high-speed CMOS OCTAL BUS TRANSCEIVER AND REGISTER (3-STATE) fabricated with silicon gate C2MOS technology. This device consists of bus transceiver circuits with 3 state, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into register on the low to high transition of the appropriate clock pin (Clock AB or Clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB ) (s t c u d o r P e t e l o DIP PACKAGE TUBE t e l o s b O TSSOP u d o r P e ORDER CODES DIP SOP TSSOP ) s ( ct SOP M74HCT646B1R M74HCT646M1R T&R M74HCT646RM13TR M74HCT646TTR select BA) can multiplex stored and real time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode (enable G high), "A" data may be stored in one register and/or "B" data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. All inputs are equipped with protection circuits against static discharge and transient excess voltage. s b O PIN CONNECTION AND IEC LOGIC SYMBOLS April 2003 1/15 M74HCT646 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1 CLOCK AB 2 3 4, 5, 6, 7, 8, 9, 10, 11 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 12 24 G DIR CAB CBA SAB SBA X H X X X X X L X L X X* H X X* H X X X L X L X H X H X X X* H t e l o X bs O X* X* L L X* X* X B INPUTS Z B1 to B8 s b O B Data Inputs/Outputs Output Enable Input (Active LOW) SELECT BA Select B to A Source Input CLOCK BA B to A Clock Input (LOW to HIGH, Edge Triggered) GND Ground (0V) VCC Positive Supply Voltage u d o r P e FUNCTION Both the A bus and the B bus are inputs The Output functions of the A and B bus are disabled Both the A and B bus are used for inputs to the internal INPUTS INPUTS flip-flops. Data at the bus will be stored on low to high transition of the clock inputs. INPUTS OUTPUTS The A bus are inputs and the B bus are outputs L L The data at the A bus are displayed at the B bus H H L L The data at the A bus are displayed at the B bus. The data of the A bus are stored to internal flip-flop on low H H to high transition of the clock pulse The data stored to the internal flip-flop are displayed at X Qn the B bus. L L The data at the A bus are stored to the internal flip-flop on low to high transition of the clock pulse. The states H H of the internal flip-flops output directly to the B bus. OUTPUTS INPUTS The B bus are inputs and the A bus are outputs. L L The data at the B bus are displayed at the A bus H H L L The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flip-flop on H H low to high transition of the clock pulse. The data stored to the internal flip-flops are displayed Qn X at the A bus L L The data at the B bus are stored to the internal flip-flop on low to high transition of the clock pulse. The states H H of the internal flip-flops output directly to the A bus. ) (s X : Don’t Care Z : High Impedance Qn : The data stored to the internal flip-flops by most recent low to high transition of the clock inputs * : The data at the A and B bus will be stored to the internal flip-flops on every low to high transition of the clock inputs. 2/15 ) s ( ct G t c u d o r P e X* L A INPUTS Z A to B Clock Input (LOW to HIGH, Edge-Triggered) SELECT AB Select A to B Source Input GAB Direction Control Input A1 to A8 A Data Inputs/Outputs t e l o TRUTH TABLE NAME AND FUNCTION M74HCT646 LOGIC DIAGRAM ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r TIMING CHART P e t e l o s b O 3/15 M74HCT646 ABSOLUTE MAXIMUM RATINGS Symbol VCC Parameter Value Supply Voltage Unit -0.5 to +7 V -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 V DC Input Diode Current ± 20 mA IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA ± 70 mA 500(*) mW VI DC Input Voltage VO DC Output Voltage IIK ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) V ) s ( t -65 to +150 300 c u d °C °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 °C; derate to 300mW by 10mW/ °C from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS Symbol VCC o s b VI Input Voltage VO Output Voltage Top Operating Temperature tr, tf Input Rise and Fall Time (VCC = 4.5 to 5.5V) r P e t e l o 4/15 O ) s ( t c u d o s b O e t e l Parameter Supply Voltage o r P Value Unit 4.5 to 5.5 V 0 to VCC V 0 to VCC V -55 to 125 °C 0 to 500 ns M74HCT646 DC SPECIFICATIONS Test Condition Symbol VIH Parameter High Level Input Voltage VIL Low Level Input Voltage VOH VOL II IOZ ICC ∆ ICC TA = 25°C VCC (V) Min. 4.5 to 5.5 4.5 to 5.5 High Level Output Voltage 4.5 Low Level Output Voltage 4.5 Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Value Typ. Max. 2.0 -40 to 85°C -55 to 125°C Min. Min. Max. 2.0 Unit Max. 2.0 0.8 0.8 V 0.8 IO=-20 µA 4.4 4.5 4.4 4.4 IO=-6.0 mA 4.18 4.31 4.13 4.10 V (s) ct V IO=20 µA 0.0 0.1 IO=6.0 mA 0.17 0.26 0.33 ±1 ±1 µA 0.1 u d o 0.1 0.40 V 5.5 VI = VCC or GND ± 0.1 5.5 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ± 10 µA 5.5 VI = VCC or GND 4 40 80 µA 5.5 Per Input pin VI = 0.5V or VI = 2.4V Other Inputs at VCC or GND IO = 0 2.0 2.9 3.0 mA ) (s r P e s b O t e l o t c u d o r P e t e l o s b O 5/15 M74HCT646 AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time 4.5 4.5 tPLH tPHL Propagation Delay Time (SELECT A,B) tPZL tPZH High Impedance Output Enable Time (G, DIR) tPLZ tPHZ High Impedance Output Disable Time (G, DIR) fMAX Maximum Clock Frequency Minimum Pulse tW(H) Width tW(L) 4.5 e t e l o s b CIN CI/O O CPD Parameter Input Capacitance Bus Terminal Capacitance Power Dissipation Capacitance (note 1) -55 to 125°C Min. Min. Max. 50 7 12 15 19 50 150 50 150 50 20 25 29 34 24 30 38 44 52 34 38 48 55 65 43 48 60 65 75 53 150 29 42 53 Max. 38 48 150 RL = 1 KΩ 31 46 4.5 50 RL = 1 KΩ 26 35 o r P 4.5 50 4.5 50 4.5 50 4.5 50 e t e ol 31 )- s b O ns ns 44 ns 60 70 55 ns ns 55 25 20 MHz 8 15 19 ns 3 t(s 10 13 13 ns 5 5 5 ns Test Condition VCC (V) 58 ns ) s ( ct du 26 Unit Max. 65 RL = 1 KΩ c u d Symbol Min. -40 to 85°C Typ. CAPACITIVE CHARACTERISTICS o r P TA = 25°C 50 4.5 Minimum Set-Up Time Minimum Hold Time th CL (pF) 4.5 tPLH tPHL Propagation Delay Time(CLOCK-A,B) ts VCC (V) Value Value TA = 25°C Min. Typ. Max. 5 10 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF 13 pF 40 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per bit) 6/15 M74HCT646 TEST CIRCUIT ) s ( ct u d o TEST tPLH, tPHL tPZL, tPLZ e t e ol tPZH, tPHZ CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) Pr SWITCH Open VCC GND s b O WAVEFORM 1: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) ) (s t c u d o r P e t e l o s b O 7/15 M74HCT646 WAVEFORM 2 : CLOCK AB, BA MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o s b O WAVEFORM 3: A, B TO CLOCK MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle) ) (s t c u d o r P e t e l o s b O 8/15 M74HCT646 WAVEFORM 4 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) ) s ( ct u d o r P e t e l o ) (s s b O t c u WAVEFORM 5: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle) d o r P e t e l o s b O 9/15 M74HCT646 Plastic DIP-24 (0.25) MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 4.32 A1 0.170 0.38 0.015 A2 3.3 0.130 B 0.41 0.46 0.51 0.016 0.018 B1 1.40 1.52 1.65 0.055 0.060 c 0.20 0.25 0.30 0.008 0.010 D 31.62 31.75 31.88 1.245 E 7.62 8.26 0.300 E1 6.35 6.86 let 6.60 e 2.54 E1 7.62 M 0˚ -O 3.43 (s) bs P e 1.255 0.325 0.260 0.270 0.100 0.300 0˚ 15˚ E A1 E1 L Stand-off B O ro 1.250 t c u t e l o 0.012 0.135 15˚ od r P e du 0.125 A2 3.18 o s b 0.065 A L 0.250 ) s ( ct 0.020 B1 e e1 c D 24 13 .015 0,38 Gage Plane 1 12 M 0034965/D 10/15 M74HCT646 SO-24 MECHANICAL DATA mm. inch DIM. TYP MAX. A MIN. TYP. MAX. 2.65 a1 0.1 0.104 0.2 a2 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0.019 0.5 0.020 c1 u d o 45˚ (typ.) D 15.20 15.60 0.598 E 10.00 10.65 0.393 1.27 e3 13.97 7.40 7.60 L 0.50 1.27 ) (s so b O F S bs O 0.050 0.550 0.291 0.300 0.020 0.050 C c1 A a2 t e l o 0.419 L d o r b 0.614 8 ˚ (max.) t c u P e e t e l Pr e s e3 a1 e ) s ( ct 0.012 b1 MIN. E D 13 F 24 1 1 2 PO13T 11/15 M74HCT646 TSSOP24 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.1 A1 0.05 0.043 0.15 A2 0.002 0.006 0.9 0.035 b 0.19 0.30 0.0075 c 0.09 0.20 0.0035 D 7.7 7.9 0.303 E 6.25 6.5 0.246 E1 4.3 4.5 e bs 0.65 BSC K 0˚ L 0.50 s ( t c let 0.70 du 0.0079 ro P e 0.311 0.256 0.177 0.0256 BSC 0˚ 8˚ 0.020 0.028 u d o r P e A o s b O ) 8˚ 0.0118 t e l o 0.169 ) s ( ct A2 A1 b O K e L E c D E1 PIN 1 IDENTIFICATION 1 7047476A 12/15 M74HCT646 Tape & Reel SO-24 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 330 MAX. 12.992 C 12.8 13.2 D 20.2 0.795 N 60 2.362 T 0.504 0.519 ) s ( ct 30.4 1.197 Ao 10.8 11.0 0.425 Bo 15.7 15.9 0.618 Ko 2.9 3.1 0.114 Po 3.9 4.1 P 11.9 12.1 ) (s let 0.153 so b O P e 0.468 ro du 0.433 0.626 0.122 0.161 0.476 t c u d o r P e t e l o s b O 13/15 M74HCT646 Tape & Reel TSSOP24 MECHANICAL DATA mm. inch DIM. MIN. TYP A TYP. MAX. 12.992 C 12.8 13.2 D 20.2 0.795 N 60 2.362 0.504 0.519 ) s ( ct 22.4 0.882 Ao 6.8 7 0.268 Bo 8.2 8.4 0.323 Ko 1.7 1.9 0.067 Po 3.9 4.1 P 11.9 12.1 ) (s t c u d o r P e t e l o 14/15 MIN. 330 T s b O MAX. let 0.153 so b O P e 0.468 ro du 0.276 0.331 0.075 0.161 0.476 M74HCT646 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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