PM6681A
Dual synchronous step-down controller with adjustable LDO
Features
■
6 V to 36 V input voltage range
■
Adjustable output voltages
■
0.9 - 3.3 V LDO adjustable delivers 100 mA
peak current
■
5 V LDO delivers 100 mA peak current
■
1.237 V ±1 % reference voltage available
■
No RSENSE current sensing using low side
MOSFETs' RDS(on)
■
Negative current limit
■
Soft-start internally fixed at 2 ms
■
Soft output discharge
■
Latched UVP
■
Not-latched OVP
■
Selectable pulse skipping at light loads
■
Selectable minimum frequency (33 kHz) in
pulse skip mode
■
5 mW maximum quiescent power
■
Independent Power Good signals
■
Output voltage ripple compensation
Applications
■
Embedded computer system
■
FPGA system power
■
Industrial applications on 24 V
■
High performance and high density DC-DC
modules
■
Notebook computer
Table 1.
Description
PM6681A is a dual step-down controller
specifically designed to provide extremely high
efficiency conversion, with lossless current
sensing technique. The constant on-time
architecture assures fast load transient response
and the embedded voltage feed-forward provides
nearly constant switching frequency operation. An
embedded integrator control loop compensates
the DC voltage error due to the output ripple.
Pulse skipping technique increases efficiency at
very light load. Moreover a minimum switching
frequency of 33 kHz is selectable to avoid audio
noise issues. The PM6681A provides a selectable
switching frequency, allowing three different
values of switching frequencies for the two
switching sections. The output voltages OUT1
and OUT2 can be adjusted from 0.9 V to 5 V and
from 0.9 V to 3.3 V respectively. The device
provides also 2 LDOs, 5 V fixed and 0.9 V - 3.3 V
adjustable.
Order codes
Order codes
Package
Packaging
PM6681A
VFQFPN-32 (5 mm x 5 mm)
exposed pad
Tray
PM6681ATR
June 2008
VFQFPN-32 (5 mm x 5 mm)
Rev 3
Tape and reel
1/47
www.st.com
47
Contents
PM6681A
Contents
1
Simplified application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
2/47
7.1
Constant on time PWM control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.2
Constant on time architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3
Output ripple compensation and loop stability . . . . . . . . . . . . . . . . . . . . . 20
7.4
Pulse skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.5
No-audible skip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.6
Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.7
soft-start and soft-end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.8
Gate drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.9
Internal linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.10
Power up sequencing and operative modes . . . . . . . . . . . . . . . . . . . . . . . 28
Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1
Power good signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.4
Undervoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PM6681A
9
Contents
Design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.1
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.2
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
9.3
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.4
Input capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.5
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9.6
Closing the integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.7
Other parts design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
9.8
Design example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.8.1
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9.8.2
Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.8.3
Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.8.4
Current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.8.5
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.8.6
Synchronous rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.8.7
Integrator loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.8.8
Output feedback divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10
Layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
11
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3/47
Simplified application schematic
1
Simplified application schematic
Figure 1.
4/47
Application schematic
PM6681A
PM6681A
Pin settings
2
Pin settings
2.1
Connections
Figure 2.
Pin connection (top view)
27
26
EN1
28
PGOOD
29
PGOOD2
30
FB1
31
OUT
COMP1
VCC
VREF
32
25
1
24
2
23
SGND
COMP2
BOOT1
3
FSEL
22
HGATE1
EN2
SHDN
FB2
LDO
OUT2
4
21
PM6681A
PHASE1
5
20
6
19
CSENSE1
VIN
7
18
LDO5
8
17
V5SW
9
10
11
12
13
14
15
16
LDO FB
LGATE1
PGND
LGATE2
CSENSE2
PHASE2
HGATE2
BOOT2
2.2
SKIP
Functions
Table 2.
N°
Pin functions
Pin
Function
1
SGND
Signal ground. Reference for internal logic circuitry. It must be connected to
the signal ground plan of the power supply. The signal ground plan and the
power ground plan must be connected together in one point near the PGND
pin.
2
COMP2
3
FSEL
DC voltage error compensation pin for the switching section 2
Frequency selection pin. It provides a selectable switching frequency,
allowing three different values of switching frequencies for the switching
sections.
5/47
Pin settings
PM6681A
Table 2.
N°
Pin
Function
EN2
Enable input for the switching section 2.
– The section 2 is enabled applying a voltage greater than 2.4 V to this pin.
– The section 2 is disabled applying a voltage lower than 0.8 V.
When the section is disabled the high side gate driver goes low and Low
Side gate driver goes high. If both EN1 and EN2 pins are low and SHDN pin
is high the device enters in standby mode.
5
SHDN
Shutdown control input.
– The device switch off if the SHDN voltage is lower than the device off
threshold (shutdown mode)
– The device switch on if the SHDN voltage is greater than the device on
threshold.
The SHDN pin can be connected to the battery through a voltage divider to
program an undervoltage lockout. In shutdown mode, the gate drivers of the
two switching sections are in high impedance (high-Z).
6
FB2
Feedback input for the switching section 2 This pin is connected to a
resistive voltage-divider from OUT2 to PGND to adjust the output voltage
from 0.9 V to 3.3 V.
7
LDO
Adjustable internal regulator output. It can be set from 0.9 V to 3.3 V.
LDO pin can provide a 100 mA peak current.
8
OUT2
Output voltage sense for the switching section 2. This pin must be directly
connected to the output voltage of the switching section.
9
BOOT2
Bootstrap capacitor connection for the switching section 2. It supplies the
high-side gate driver.
10
HGATE2
High-side gate driver output for section 2. This is the floating gate driver
output.
11
PHASE2
Switch node connection and return path for the high side driver for the
section 2. It is also used as negative current sense input.
4
Positive current sense input for the switching section 2. This pin must be
connected through a resistor to the drain of the synchronous rectifier
(RDS(on) sensing) to obtain a positive current limit threshold for the power
supply controller.
12
CSENSE2
13
LGATE2
14
PGND
15
LGATE1
Low-side gate driver output for the section 1.
16
LDO FB
Feedback input for the adjustable internal linear regulator. This pin is
connected to a resistive voltage-divider from LDO to SGND to adjust the
output voltage from 0.9 V to 3.3 V.
17
6/47
Pin functions (continued)
V5SW
Low-side gate driver output for the section 2.
Power ground. This pin must be connected to the power ground plan of the
power supply.
Internal 5 V regulator bypass connection.
– If V5SW is connected to OUT5 (or to an external 5 V supply) and V5SW is
greater than 4.9 V, the LDO5 regulator shuts down and the LDO5 pin is
directly connected to OUT5 through a 3 W (max) switch.
If V5SW is connected to GND, the LDO5 linear regulator is always on if the
device is not in shutdown mode.
PM6681A
Pin settings
Table 2.
Pin functions (continued)
N°
Pin
18
LDO5
19
VIN
Function
5 V internal regulator output. It can provide up to 100 mA peak current.
LDO5 pin supplies embedded low side gate drivers and an external load.
Device supply voltage input and battery voltage sense. A bypass filter
(4 W and 4.7 µF) between the battery and this pin is recommended.
Positive current sense input for the switching section 1. This pin must be
connected through a resistor to the drain of the synchronous rectifier
(RDS(on) sensing) to obtain a positive current limit threshold for the power
supply controller.
20
CSENSE1
21
PHASE1
Switch node connection and return path for the high side driver for the
section 1. It is also used as negative current sense input.
22
HGATE1
High-side gate driver output for section 1. This is the floating gate driver
output.
23
BOOT1
Bootstrap capacitor connection for the switching section 1. It supplies the
high-side gate driver.
SKIP
Pulse skipping mode control input.
– If the pin is connected to LDO5 the PWM mode is enabled.
– If the pin is connected to GND, the pulse skip mode is enabled.
– If the pin is connected to VREF the pulse skip mode is enabled but the
switching frequency is kept higher than 33 kHz
(No-audible pulse skip mode).
25
EN1
Enable input for the switching section 1.
– The section 1 is enabled applying a voltage greater than 2.4 V to this pin.
– The section 1 is disabled applying a voltage lower than 0.8 V.
when the section is disabled the high side gate driver goes low and low side
gate driver goes high.
26
PGOOD1
Power Good output signal for the section 1. This pin is an open drain output
and when the output of the switching section 1 is out of +/- 10 % of its
nominal value.It is pulled down.
27
PGOOD2
Power Good output signal for the section 2. This pin is an open drain output
and when the output of the switching section 2 is out of +/- 10 % of its
nominal value.It is pulled down.
28
FB1
Feedback input for the switching section 1. This pin is connected to a
resistive voltage-divider from OUT1 to PGND to adjust the output voltage
from 0.9 V to 5.5 V.
29
OUT1
Output voltage sense for the switching section 1.This pin must be directly
connected to the output voltage of the switching section.
30
COMP1
31
VCC
Device supply voltage pin. It supplies all the internal analog circuitry except
the gate drivers (see LDO5). Connect this pin to LDO5.
32
VREF
Internal 1.237 V high accuracy voltage reference. It can deliver 50 µA.
Bypass to SGND with a 100 nF capacitor to reduce noise.
24
DC voltage error compensation pin for the switching section 1.
7/47
Functional block diagram
3
Functional block diagram
Figure 3.
8/47
Functional block diagram
PM6681A
PM6681A
4
Maximum ratings
Maximum ratings
Table 3.
Absolute maximum ratings
Parameter
Value
Unit
V5SW, LDO5 to PGND
-0.3 to 6
V
VIN to PGND
-0.3 to 36
V
HGATEx and BOOTx, to PHASEx
-0.3 to 6
V
-0.6 (1) to36
V
-0.6 to 42
V
-6 to 0.3
V
PHASEx to PGND
CSENSEx, to PGND
CSENSEx to BOOTx
LGATEx to PGND
-0.3
FBx, COMPx, SKIP, FSEL,VREF to SGND, LDO FB
(2)
V
-0.3 to Vcc+0.3
V
-0.3 to 0.3
V
-0.3 to 6
V
2.8
W
VIN
±1000
V
Other pins
±2000
PGND to SGND
SHDN, PGOODx, OUTx, VCC, ENx to SGND
Power dissipation at TA = 25 °C
Maximum withstanding voltage range test condition:
CDF-AEC-Q100-002- “human body model” acceptance
criteria: “normal performance”
to LDO5 +0.3
1. PHASE to PGND up to -2.5 V for t < 10 ns
2. LGATEx to PGND up to -1 V for t < 40 ns
Table 4.
Thermal data
Symbol
Parameter
Value
Unit
-50 to 150
°C
TSTG
Storage temperature range
RthJA
Thermal resistance junction to ambient
35
°C/W
TJ
Junction operating temperature range
-40 to 125
°C
TA
Operating ambient temperature range
-40 to 85
°C
Table 5.
Recommended operating conditions
Value
Symbol
Parameter
Test condition
Unit
Min
VIN
Input voltage range
VCC
IC supply voltage
VV5SW
VV5SW maximum operating
range
LDO5 in regulation
Typ
Max
5.5
36
V
4.5
5.5
V
5.5
V
9/47
Electrical characteristics
PM6681A
5
Electrical characteristics
Table 6.
Electrical characteristics
(VIN = 24 V; TJ = 25 °C, unless otherwise specified)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
4.8
4.9
V
Supply section
Turn-on voltage threshold
VV5SW
RDS(on)
Turn-off voltage threshold
4.6
4.75
V
Hysteresis
20
50
mV
LDO5 internal bootstrap
switch resistance
V5SW > 4.9 V
OUTx, OUTx
discharge-mode
On-resistance
OUTx, OUTx
discharge-mode
Synchronous rectifier
turn-on level
0.2
1.8
3
Ω
18
25
Ω
0.35
0.6
V
4
mW
Pin
Operating power
consumption
FBx > VREF, Vref in regulation,
V5WS to 5 V
Ish
Operating current sunk by
VIN
SHDN connected to GND
20
30
µA
Isb
Operating current sunk by
VIN
ENx to GND, V5SW to GND
250
380
µA
Shutdown section
VSHDN
Device on threshold
1.2
1.5
1.7
V
Device off threshold
0.8
0.85
0.9
V
3.5
ms
110
µA
soft-start section
soft-start ramp time
2
Current limit and zero crossing comparator
ICSENSE
10/47
Input bias current limit (1)
90
100
Comparator offset
VCSENSE - VPGND
-6
6
mV
Zero crossing comparator
offset
VPGND - VPHASE
-1
11
mV
Fixed negative current limit
threshold
VPGND - VPHASE
-120
mV
PM6681A
Table 6.
Electrical characteristics
Electrical characteristics
(VIN = 24 V; TJ = 25 °C, unless otherwise specified) (continued)
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
FSEL to GND
OUT1 = 3.3 V
OUT2 = 1.8 V
575
680
785
195
230
265
FSEL to VREF
OUT1 = 3.3 V
OUT2 = 1.8 V
390
460
530
145
175
205
FSEL to LDO5
OUT1 = 3.3 V
OUT2 =1.8 V
285
340
395
110
135
160
350
500
ns
1.236
1.249
V
4
mV
0.95
mV
+909
mV
On time pulse width
Ton
On time duration_
@VIN = 24 V
ns
OFF time
TOFFMIN
Minimum off time
@VIN = 24 V
Voltage reference
VREF
Voltage accuracy
4 V < VLDO5 < 5.5 V
Load regulation
-100 µA< IREF < 100 µA
Undervoltage lockout fault
threshold
Falling edge of REF
1.224
-4
Integrator
FB
Voltage accuracy
+891
Input bias current
(1)
0.1
COMP
Over voltage clamp
Normal mode
250
COMP
Under voltage clamp
FB
µA
mV
-150
Line regulation
Both SMPS, 6 V < Vin < 36 V (1)
1
%
5.1
V
0.004
%/V
LDO5 linear regulator
LDO5 linear output voltage
6 V < VIN < 36 V,
0 < ILDO5 < 50 mA
LDO5 line regulation
6 V < VIN < 36 V, ILDO5 = 20 mA ,
ILDO5
LDO5 current limit
VLDO5 > UVLO
ULVO
Under voltage lockout of
LDO5
VLDO5
4.9
5.0
270
330
400
mA
3.94
4
4.13
V
0.887
0.905
0.923
V
LDO linear regulator
VLDO
LDO linear output voltage
4.5 V< V5SW < 5.5 V
0.5 mA < ILDO < 50 mA
LDO FB connected to LDO
11/47
Electrical characteristics
Table 6.
Symbol
PM6681A
Electrical characteristics
(VIN = 24 V; TJ = 25 °C, unless otherwise specified) (continued)
Parameter
ILDO
LDO current limit
ILDO FB
Input bias current
Test condition
Min
Typ
Max
Unit
170
220
270
mA
(1)
0.1
HGATEx high state (pull-up)
2.0
3
HGATEx low state (pull-down)
1.6
2.7
LGATEx high state (pull-up)
1.4
2.1
LGATEx low state (pull-down)
0.8
1.2
112
116
120
%
µA
High and low gate drivers
HGATE driver on-resistance
Ω
LGATE driver on-resistance
PGOOD pins UVP/OVP protections
Both SMPS sections with
respect to VREF, OUT1 = 5 V,
OUT2 = 3.3 V
OVP
Over voltage threshold
UVP
Under voltage threshold
65
68
71
%
Upper threshold
(VFB-VREF)
107
110
113
%
Lower threshold
(VFB-VREF)
88
91
94
%
1
uA
250
mV
PGOOD1,2
IPGOOD1,2
PGOOD leakage current
VPGOOD1,2 forced to 5.5 V
VPGOOD1,2
output low voltage
ISink = 4 mA
150
Power management pins
SMPS disabled level
(1)
SMPS enabled level
(1)
Frequency selection range
Low level (1)
EN1,2
Middle level (1)
FSEL
High level (1)
SKIP
Pulse skip mode
(1)
Ultrasonic mode
(1)
PWM mode
(1)
Input leakage current
1. by design
12/47
0.8
V
2.4
0.5
1.0
VLDO5 1.5
V
VLDO5 0.8
0.5
1.0
VLDO5 1.5
V
VLDO5 0.8
VEN1,2 = 0 to 5 V
1
VSKIP = 0 to 5 V
1
VSHDN = 0 to 5 V
1
VFSEL = 0 to 5 V
1
µA
PM6681A
6
Typical operating characteristics
Typical operating characteristics
(FSEL = GND (200/300 kHz), SKIP = GND (skip mode), V5SW = EXT5 V (external 5 V
power supply connected), input voltage VIN = 24 V, SHDN, EN1 and EN2 high,
OUT1 = 3.3 V, OUT2 = 1.8 V, no load, LDO = 3.3 V, (LDO_FB divider = 5.6 k and 15 k)
unless specified)
Figure 4.
Efficiency vs current load
Figure 5.
Efficiency vs current load
\
Figure 6.
PWM no load battery current Figure 7.
vs input voltage
No-audible skip no load
battery current vs input
voltage
\
Figure 8.
Skip no load battery current
vs input voltage
Figure 9.
Shutdown mode input battery
current vs input voltage
\
13/47
Typical operating characteristics
Figure 10. Standby mode input battery
current vs input voltage
PM6681A
Figure 11. Voltage reference vs load
current
\
Figure 12. OUT1 = 3.3 V switching
frequency
Figure 13. OUT2 = 1.8 V switching
frequency
\
Figure 14. OUT1 = 3.3 V load regulation Figure 15. OUT2 = 1.8 V load regulation
\
14/47
PM6681A
Typical operating characteristics
Figure 16. LDO5 vs output current
Figure 17. LDO vs output current
\
Figure 18. SHDN, OUT1, LDO and LDO5 Figure 19. OUT1, OUT2, LDO and LDO5
power-up
power-up
\
Figure 20. OUT1 = 3.3 V load transient
0 to 2 A
Figure 21. OUT2 = 1.8 V load transient
0 to 2 A
\
15/47
Typical operating characteristics
Figure 22. 3.3 V soft-start (1 Ω load)
PM6681A
Figure 23. 1.8 V soft-start (0.6 Ω load)
\
Figure 24. OUT1 = 3.3 V
soft-end (no load)
Figure 25. OUT2 = 1.8 V
soft-end (no load)
\
Figure 26. OUT1 = 3.3 V soft-end
(0.8 Ω load)
Figure 27. OUT2 = 1.8 V soft-end
(0.6 Ω load)
\
16/47
PM6681A
Typical operating characteristics
Figure 28. 3.3 V no-audible skip mode
Figure 29. 1.8 V no-audible skip mode
\
17/47
Device description
7
PM6681A
Device description
The PM6681A is a dual step-down controller dedicated to provide logic voltages for
industrial automation application and notebook computer.
It is based on a constant on time control architecture. This type of control offers a very fast
load transient response with a minimum external component count. A typical application
circuit is shown in Figure 1. The PM6681A regulates two adjustable output voltages: OUT1
and OUT2. The switching frequency of the two sections can be adjusted to three different
values. In order to maximize the efficiency at light load condition, a pulse skipping mode can
be selected. The PM6681A includes also a 5 V linear regulator (LDO5) that can power the
switching drivers. If the output OUT1 regulates 5 V, in order to maximize the efficiency in
higher consumption status, the linear regulator can be turned off and their outputs can be
supplied directly from the switching outputs. Moreover, the PM6681A includes also a linear
regulator with an output voltage adjustable from 0.9 V to 3.3 V. It can provide 100 mA of
peak current. The PM6681A provides protection versus overvoltage, undervoltage and
overtemperature as well as Power Good signals for monitoring purposes.
An external 1.237 V reference is available.
7.1
Constant on time PWM control
If the SKIP pin is tied to 5 V, the device works in PWM mode. Each power section has an
independent on time control.The PM6681A employees a pseudo-fixed switching frequency,
constant on time (COT) controller as core of the switched mode section. Each power section
has an independent COT control.
The COT controller is based on a relatively simple algorithm and uses the ripple voltage due
to the output capacitor's ESR to trigger the fixed on-time one-shot generator. In this way, the
output capacitor's ESR acts as a current sense resistor providing the appropriate ramp
signal to the PWM comparator. On-time one-shot duration is directly proportional to the
output voltage, sensed at the OUT1/OUT2 pins, and inversely proportional to the input
voltage, sensed at the VIN pin, as follows:
Equation 1
Ton = K ×
Vout
Vin
This leads to a nearly constant switching frequency, regardless of input and output voltages.
When the output voltage goes lower than the regulated voltage Vreg, the on-time one shot
generator directly drives the high side MOSFET for a fixed on time allowing the inductor
current to increase; after the on time, an off time phase, in which the low side MOSFET is
turned on, follows. Figure 30 shows the inductor current and the output voltage waveforms
in PWM mode.
18/47
PM6681A
Device description
Figure 30. Constant on time PWM control
".W
)NDUCTOR
CURRENT
/UTPUT
VOLTAGE
6REG
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4ON
T
4OFF
The duty cycle of the buck converter in steady state is:
Equation 2
D=
Vout
Vin
The PWM control works at a nearly fixed frequency fSW:
Equation 3
fsw
D
=
=
Ton
Vout
Vin
= 1
K on
Vout
K on ×
Vin
As mentioned the steady state switching frequency is theoretically independent from battery
voltage and from output voltage.
Actually the frequency depends on parasitic voltage drops that are present during the
charging path (high side switch resistance, inductor resistance (DCR) and discharging path
(low side switch resistance, DCR).
As a result the switching frequency increases as a function of the load current.
Standard switching frequency values can be selected for both sections by connecting pin
FSEL to SGND, VREF or LDO5 pin. The following table shows the typical switching
frequencies that can be obtained as a function of the programmed output voltage. The
measures are referred to switching sections with 2 A load, 12 V input voltage and working in
continuous conduction mode.
Table 7.
FSEL pin selection: typical switching frequency
Fsw @ OUT1 = 1.5 V (kHz)
Fsw @ OUT2 = 1.05 V (kHz)
FSEL = GND
200
325
FSEL = VREF
290
425
FSEL = LDO5
390
590
19/47
Device description
7.2
PM6681A
Constant on time architecture
Figure 31 shows the simplified block diagram of a constant on time controller. A minimum
off-time constrain (350 ns typ.) is introduced to allow inductor valley current sensing on
synchronous switch. A minimum on-time (130 ns) is also introduced to assure the start-up
switching sequence.
PM6681A has a one-shot generator for each power section that turns on the high side
MOSFET when the following conditions are satisfied simultaneously: the PWM comparator
is high, the synchronous rectifier current is below the current limit threshold, and the
minimum off-time has timed out.
Once the on-time has timed out, the high side switch is turned off, while the synchronous
switch is turned on according to the anti-cross conduction circuitry management.
When the negative input voltage at the PWM comparator (Figure 31), which is a scaleddown replica of the output voltage (see the external R1/R2 divider in Figure 32), reaches the
valley limit (determined by internal reference Vr = 0.9 V), the low-side MOSFET is turned off
according to the anti-cross conduction logic once again, and a new cycle begins.
Figure 31. Constant on-time block diagram
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7.3
Output ripple compensation and loop stability
In a classic constant on time control, the system regulates the valley value of the output
voltage and not the average value, as shown in Figure 30. In this condition, the output
voltage ripple is source of a DC static error.
To compensate this error, an integrator network can be introduced in the control loop, by
connecting the output voltage to the COMP1/COMP2 (for the OUT1 and OUT2 sections
respectively) pin through a capacitor CINT as in Figure 32.
20/47
PM6681A
Device description
Figure 32. Circuitry for output ripple compensation
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The integrator amplifier generates a current, proportional to the DC errors between the FB
voltage and Vr, which decreases the output voltage in order to compensate the total static
error, including the voltage drop on PCB traces. In addition, CINT provides an AC path for
the output ripple. In steady state, the voltage on COMP1/COMP2 pin is the sum of the
reference voltage Vr and the output ripple (see Figure 32). In fact when the voltage on the
COMP pin reaches Vr, a fixed Ton begins and the output increases.
For example, we consider Vout = 5 V with an output ripple of ∆V = 50 mV. Considering CINT
>> CFILT, the CINT DC voltage drop VCINT is about 5 V - Vr + 25 mV = 4.125 V.
CINT assures an AC path for the output voltage ripple. Then the COMP pin ripple is a replica
of the output ripple, with a DC value of Vr + 25 mV = 925 mV.
For more details about the output ripple compensation network, see the paragraph “Closing
the integrator loop” in the design guidelines.
In steady state the FB pin voltage is about Vr and the regulated output voltage depends on
the external divider:
Equation 4
⎛ R ⎞
OUT = Vr × ⎜⎜1 + 2 ⎟⎟
R1 ⎠
⎝
7.4
Pulse skip mode
If the SKIP pin is tied to ground, the device works in skip mode.
At light loads a zero-crossing comparator truncates the low-side switch on-time when the
inductor current becomes negative. In this condition the section works in discontinuous
conduction mode. The threshold between continuous and discontinuous conduction mode
is:
21/47
Device description
PM6681A
Equation 5
ILOAD(SKIP) =
VIN − VOUT
× TON
2×L
For higher loads the inductor current doesn't cross the zero and the device works in the
same way as in PWM mode and the frequency is fixed to the nominal value.
Figure 33. PWM and pulse skip mode inductor current
07-MODE
0ULSESKIPMODE
,OZSIDEON
)NDUCTORCURRENT
,OADCURRENT
4O N4OFF
4ON
4ON 4ON
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4OFF
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!-V
Figure 33 shows inductor current waveforms in PWM and SKIP mode. In order to keep
average inductor current equal to load current, in SKIP mode some switching cycles are
skipped. When the output ripple reaches the regulated voltage Vreg, a new cycle begins.
The off cycle duration and the switching frequency depend on the load condition.
As a result of the control technique, losses are reduced at light loads, improving the system
efficiency.
7.5
No-audible skip mode
If SKIP pin is tied to VREF, a no-audible skip mode with a minimum switching frequency of
33 kHz is enabled. At light load condition, If there is not a new switching cycle within a 30 µs
(typ.) period, a no-audible skip mode cycle begins.
Figure 34. No audible skip mode
Inductor current
No audible skip mode
∼30us
Time
0
Low side
22/47
PM6681A
Device description
The low side switch is turned on until the output voltage crosses about Vreg+1 %. Then the
high side MOSFET is turned on for a fixed on time period. Afterwards the low side switch is
enabled until the inductor current reaches the zero-crossing threshold. This keeps the
switching frequency higher than 33 kHz. As a consequence of the control, the regulated
voltage can be slightly higher than Vreg (up to 1 %).
If, due to the load, the frequency is higher than 33 kHz, the device works like in skip mode.
No-audible skip mode reduces audio frequency noise that may occur in pulse skip mode at
very light loads, keeping the efficiency higher than in PWM mode.
7.6
Current limit
The current-limit circuit employs a “valley” current-sensing algorithm. During the conduction
time of the low side MOSFET the current flowing through it is sensed. The current-sensing
element is the low side MOSFET on-resistance (Figure 35).
Figure 35. RDS(on) sensing technique
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An internal 100 µA current source is connected to CSENSE pin and determines a voltage
drop on RCSENSE. If the voltage across the sensing element is greater than this voltage
drop, the controller doesn't initiate a new cycle. A new cycle starts only when the sensed
current goes below the current limit.
Since the current limit circuit is a valley current limit, the actual peak current limit is greater
than the current limit threshold by an amount equal to the inductor ripple current. Moreover
the maximum output current is equal to the valley current limit plus half of the inductor ripple
current:
Equation 6
ILOAD (max) = ILvalley +
∆IL
2
The output current limit depends on the current ripple, as shown in Figure 36:
23/47
Device description
PM6681A
Figure 36. Current waveforms in current limit conditions
Current
Maximum load current is
influenced by the inductor
current ripple
DC current limit = maximum load
Inductor current
Valley current threshold
Time
Being fixed the valley threshold, the greater the current ripple is, greater the DC output
current is:
The valley current limit can be set with resistor RCSENSE:
Equation 7
(RDS(on) sensing technique)
RCSENSE =
RDSon × ILvalley
ICSENSE
Where ICSENSE = 100 µA, RDS(on) is the drain-source on resistance of the low side switch.
Consider the temperature effect and the worst case value in RDS(on) calculation.
The accuracy of the valley current threshold detection depends on the offset of the internal
comparator (∆VOFF) and on the accuracy of the current generator(∆ICSENSE):
Equation 8
∆ILvalley
ILvalley
=
⎤ ∆RCSENSE ∆RSNS
∆ICSENSE ⎡
∆VOFF
+⎢
× 100 ⎥ +
+
ICSENSE
RSNS
⎣ RCSENSE × ICSENSE
⎦ RCSENSE
Where RSNS is the sensing element (RDS(on)).
PM6681A provides also a fixed negative peak current limit to prevent an excessive reverse
inductor current when the switching section sinks current from the load in PWM mode. This
negative current limit threshold is measured between PHASE and SGND pins, comparing
the magnitude drop on the PHASE node during the conduction time of the low side
MOSFET with an internal fixed voltage of 120 mV.
The negative valley-current limit INEG (if the device works in PWM mode) is given by:
Equation 9
INEG =
24/47
120mV
RDSon
PM6681A
7.7
Device description
soft-start and soft-end
Each switching section is enabled separately by asserting high EN1/EN2 pins respectively.
In order to realize the soft-start, at the startup the overcurrent threshold is set 25 % of the
nominal value and the undervoltage protection (see related sections) is disabled. The
controller starts charging the output capacitor working in current limit. The overcurrent
threshold is increased from 25 % to 100 % of the nominal value with steps of 25 % every
700 µs (typ.). After 2.8 ms (typ.) the undervoltage protection is enabled. The s oft start time
is not programmable. A minimum capacitor CINT is required to ensure a soft-start without
any overshoot on the output:
Equation 10
CINT ≥
6uA
× C out
ILvalley ∆IL
+
4
2
Figure 37. Soft-start waveforms
Switching
Current limit threshold
Time
EN1/EN2
When a switching section is turned off (EN1/EN2 pins low), the controller enters in soft-end
mode. The output capacitor is discharged through an internal 18 Ω P-MOSFET switch;
when the output voltage reaches 0.3 V, the low-side MOSFET turns on, keeping the output
to ground. The soft-end time also depends on load condition.
7.8
Gate drivers
The integrated high-current drivers allow to use different power MOSFETs. The high side
driver MOSFET uses a bootstrap circuit which is indirectly supplied by LDO5 output. The
BOOT and PHASE pins work respectively as supply and return rails for the HS driver.
The low side driver uses the internal LDO5 output for the supply rail and PGND pin as return
rail.
An important feature of the gate drivers is the adaptive anti-cross conduction protection,
which prevents high side and low side MOSFETs from being on at the same time. When the
25/47
Device description
PM6681A
high side MOSFET is turned off the voltage at the phase node begins to fall. The low side
MOSFET is turned on when the voltage at the phase node reaches an internal threshold.
When the low side MOSFET is turned off, the high side remains off until the LGATE pin
voltage goes approximately under 1 V.
The power dissipation of the drivers is a function of the total gate charge of the external
power MOSFETs and the switching frequency, as shown in the following equation:
Equation 11
Pdriver = Vdriver × Q g × fsw
Where Vdriver is the 5 V driver supply.
Reference voltage and bandgap
The 1.237 V (typ.) internal bandgap voltage is accurate to 1 % over the temperature range.
It is externally available (VREF pin) and can supply up to 100 µA and can be used as a
voltage threshold for the multifunction pins FSEL and SKIP to select the appropriate working
mode. Bypass VREF to ground with a 100 nF minimum capacitor.
If VREF goes below 0.87 V (typ.), the system detects a fault condition and all the circuitry is
turned off. A toggle on the input voltage (power on reset) or a toggle on SHDN pin is
necessary to restart the device.
An internal divider of the bandgap provides a voltage reference Vr of 0.9 V. This voltage is
used as reference for the linear and the switching regulators outputs. The overvoltage
protection, the undervoltage protection and the Power Good signals are referred to Vr.
7.9
Internal linear regulators
The PM6681A has two linear regulators providing respectively 5 V (LDO5) and an
adjustable voltage (LDO) at ± 2 % accuracy. High side drivers, low side drivers and
MOSFETs of internal circuitry are supplied by LDO5 output through VCC pin (an external
RC filter may be applied between LDO5 and VCC). The linear regulator can provide an
average output current of 50 mA and a peak output current of 100mA. Bypass LDO5 output
with a minimum 1 µF ceramic capacitor and a 4,7 µF tantalum capacitor (ESR ≥ 2 Ω). If the
5 V output goes below 4 V, the system detects a fault condition and all the circuitry is turned
off. A power on reset or a toggle on SHDN pin is necessary to restart the device.
V5SW pin allows to keep the 5 V linear regulator always active or to enable the internal
bootstrap-switch over function: if the 5 V switching output is connected to V5SW, when the
voltage on V5SW pin is above 4.8 V, an internal 3.0 Ω max P-channel MOSFET switch
connects V5SW pin to LDO5 pin and simultaneously LDO5 shuts down. This configuration
allows to achieve higher efficiency. V5SW can be connected also to an external 5 V supply.
LDO5 regulator turns off and LDO5 is supplied externally. If V5SW is connected to ground,
the internal 5 V regulator is always on and supplies LDO5 output.
26/47
PM6681A
Device description
Table 8.
V5SW multifunction pin
V5SW
GND
Description
The 5 V linear regulator is always turned on and supplies LDO5 output.
Switching 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4.8 V and
output
LDO5 output is supplied by the switching 5 V output.
External 5 V
supply
The 5 V linear regulator is turned off when the voltage on V5SW is above 4.8 V and
LDO5 output is supplied by the external 5 V.
The adjustable linear regulator is supplied by LDO5 output. It turns on after LDO5 power up
sequence.
It can provide up to 100 mA peak current. Set up the feedback resistor divider according to
the following formula, to regulate a voltage from 0.9 V to 3.3 V.
Equation 12
Rup
⎛
LDO = Vr × ⎜⎜1 +
⎝ R down
⎞
⎟
⎟
⎠
where LDO is the desired output voltage, Vr = 0.9 V is the internal reference voltage and Rup
and Rdown are the resistors of the feedback divider, as shown in Figure 38:
Figure 38. LDO linear regulator
Bypass LDO5 and LDO output with 1-10 µF ceramic capacitor and a 4,7 µF tantalum
capacitor (ESR ≥ 2 Ω).
27/47
Device description
7.10
PM6681A
Power up sequencing and operative modes
Let’s consider SHDN, EN1 and EN2 low at the beginning. The battery voltage is applied as
input voltage. The device is in shutdown mode.
When the SHDN pin voltage is above the shutdown device on threshold (1.5 V typ.), the
controller begins the power-up sequence. All the latched faults are cleared. LDO5
undervoltage control is blanked for 4 ms and the internal regulator LDO5 turns on. If the
LDO5 output is above the UVLO threshold after this time, the device enters in standby mode
and the adjustable internal linear regulator LDO is turned on.
The switching outputs are kept to ground by turning on the low side MOSFETs. When EN1
and EN2 pins are forced high the switching sections begin their soft-start sequence.
Table 9.
Mode
Run
Standby
Shutdown
28/47
Operative modes
Conditions
SHDN is high,
EN1/EN2 pins are high
Description
Switching regulators are enabled; internal linear
regulators outputs are enabled.
Internal linear regulators active (LDO5 is always on). In
Both EN1/EN2 pins are low
Standby mode LGATE1/LGATE2 pins are forced high
and SHDN pin is high
while HGATE1/HGATE2 pins are forced low.
SHDN is low
All circuits off.
PM6681A
Monitoring and protections
8
Monitoring and protections
8.1
Power Good signals
The PM6681A provides three independent Power Good signals: one for each switching
section (PGOOD1/PGOOD2).
PGOOD1/PGOOD2 signals are low if the output voltage is out of ± 10 % of the designed set
point or during the soft-start, standby and shutdown mode.
8.2
Thermal protection
The PM6681A has a thermal protection to preserve the device from overheating. The
thermal shutdown occurs when the die temperature goes above +150 °C. In this case all
internal circuitry is turned off and the power sections are turned off after the discharge
mode.
A power on reset or a toggle on the SHDN pin is necessary to restart the device.
8.3
Overvoltage protection
When the switching output voltage goes over the OVP threshold (about 116 % of its nominal
value), the low side MOSFET turns on. The LS MOSFET is kept on until the output voltage
returns under the OVP threshold.
8.4
Undervoltage protection
When the switching output voltage is below 70 % of its nominal value, a latched
undervoltage protection occurs. In this case the switching section is immediately disabled
and both switches are open. The controller enters in soft-end mode and the output is
eventually kept to ground, turning low side MOSFET on. The undervoltage circuit protection
is enabled only at the end of the soft-start. Once an overvoltage protection has been
detected, a toggle on SHDN, EN1/EN2 pin or a power on reset is necessary to clear the
undervoltage fault and starts with a new soft-start phase.
Table 10.
Protections and operatives modes
Mode
Conditions
Description
LGATE1/LGATE2 pin is forced high until the output
voltage is over the OVP threshold, LDO5 remains
active.
Overvoltage
protection
OUT1/OUT2 > 115 % of
the nominal value
Undervoltage
protection
LGATE1/LGATE2 is forced high after the soft-end
OUT1/OUT2 < 70 % of the
mode, LDO5 remains active. Exit by a power on reset
nominal value
or toggling SHDN or EN1/EN2
Thermal
shutdown
TJ > +150 °C
All circuitry off. Exit by a POR on VIN or toggling
SHDN.
29/47
Design guidelines
9
PM6681A
Design guidelines
The design of a switching section starts from two parameters:
9.1
●
Input voltage range: in notebook applications it varies from the minimum battery
voltage, VINmin to the AC adapter voltage, VINmax.
●
Maximum load current: it is the maximum required output current, ILOAD(max).
Switching frequency
It's possible to set 3 different working frequency ranges for the two sections with FSEL pin
(table 1).
Switching frequency mainly influences two parameters:
9.2
●
Inductor size: for a given saturation current and RMS current, greater frequency allows
to use lower inductor values, which means smaller size.
●
Efficiency: switching losses are proportional to frequency. High frequency generally
involves low efficiency.
Inductor selection
Once that switching frequency is defined, inductor selection depends on the desired
inductor ripple current and load transient performance.
Low inductance means great ripple current and could generate great output noise. On the
other hand, low inductor values involve fast load transient response.
A good compromise between the transient response time, the efficiency, the cost and the
size is to choose the inductor value in order to maintain the inductor ripple current ∆IL
between 20 % and 50 % of the maximum output current ILOAD(max). The maximum ∆IL
occurs at the maximum input voltage. With this considerations, the inductor value can be
calculated with the following relationship:
Equation 13
L=
VIN − VOUT VOUT
×
fsw × ∆IL
VIN
where fsw is the switching frequency, VIN is the input voltage, VOUT is the output voltage and
∆IL is the selected inductor ripple current.
In order to prevent overtemperature working conditions, inductor must be able to provide an
RMS current greater than the maximum RMS inductor current ILRMS:
Equation 14
ILRMS = (ILOAD (max))2 +
Where ∆IL(max) is the maximum ripple current:
30/47
(∆IL (max))2
12
PM6681A
Design guidelines
Equation 15
∆IL (max) =
VIN max − VOUT
V
× OUT `
fsw × L
VIN max
If hard saturation inductors are used, the inductor saturation current should be much greater
than the maximum inductor peak current Ipeak:
Equation 16
Ipeak = ILOAD (max) +
∆IL (max)
2
Using soft saturation inductors it's possible to choose inductors with saturation current limit
nearly to Ipeak. Below there is a list of some inductor manufacturers.
Table 11.
9.3
Inductor manufacturer
Manufacturer
Series
Inductor value
(uH)
RMS current
(A)
Saturation current
(A)
Coilcraft
SER1360
1 to 8
6 to 9.5
7 to 31
Coilcraft
MLC
0.7 to 4.5
13.6 to 17.3
11.5 to 26
TDK
RLF12560
1 to 10
7.5 to 14.4
7.5 to 18.5
Output capacitor
The selection of the output capacitor is based on the ESR value Rout and the voltage rating
rather than on the capacitor value Cout.
The output capacitor has to satisfy the output voltage ripple requirements. Lower inductor
value can reduce the size of the choke but increases the inductor current ripple ∆IL.
Since the voltage ripple VRIPPLEout is given by:
Equation 17
VRIPPLEout = R out × ∆IL
A low ESR capacitor is required to reduce the output voltage ripple. Switching sections can
work correctly even with 20 mV output ripple.
However, to reduce jitter noise between the two switching sections it's preferable to work
with an output voltage ripple greater than 30 mV. If lower output ripple is required, a further
compensation network is needed (see Closing the integrator loop paragraph).
Finally the output capacitor choice deeply impacts on the load transient response (see Load
transient response paragraph). Below there is a list of some capacitor manufacturers.
31/47
Design guidelines
PM6681A
Table 12.
9.4
Output capacitor manufacturer
Manufacturer
Series
Capacitor value
(uF)
Rated voltage (V)
ESR max (mΩ)
SANYO
POSCAP TPB,TPD,
TPE
100 to 470
2.5 to 6.3
12 to 65
Panasonic
SPCAP UD, UE
100 to 470
2 to 6.3
7 to 18
Input capacitors selection
In a buck topology converter the current that flows into the input capacitor is a pulsed current
with zero average value. The input RMS current of the two switching sections can be roughly
estimated as follows:
Equation 18
ICinRMS = D1 × I12 × (1 − D1) + D 2 × I22 × (1 − D 2 )
Where D1, D2 are the duty cycles and I1, I2 are the maximum load currents of the two
sections.
Input capacitor should be chosen with an RMS rated current higher than the maximum RMS
current given by both sections.
Tantalum capacitors are good in term of low ESR and small size, but they occasionally can
burn out if subjected to very high current during the charge. Ceramic capacitors have
usually a higher RMS current rating with smaller size and they remain the best choice.
Below there is a list of some ceramic capacitor manufacturers.
Table 13.
9.5
Input capacitor manufacturer
Manufacturer
Series
Capacitor value (uF)
Rated voltage (V)
Tayio yuden
UMK432 X5506MM-T
10
50
TDK
C3225X5R1E106M
10
25
Power MOSFETs
Logic-level MOSFETs are recommended, since low side and high side gate drivers are
powered by LDO5. Their breakdown voltage VBRDSS must be higher than VINmax.
In notebook applications, power management efficiency is a high level requirement. The
power dissipation on the power switches becomes an important factor in switching
selections. Losses of high-side and low-side MOSFETs depend on their working conditions.
The power dissipation of the high-side MOSFET is given by:
Equation 19
PDHighSide = Pconduction + Pswitching
32/47
PM6681A
Design guidelines
Maximum conduction losses are approximately:
Equation 20
Pconduction = RDSon ×
VOUT
× ILOAD (max)2
VIN min
where RDS(on) is the drain-source on resistance of the high side MOSFET. Switching losses
are approximately:
Equation 21
Pswitching =
∆IL
∆I
) × t on × fsw VIN × (ILOAD (max) + L ) × t off × fsw
2
2
+
2
2
VIN × (ILOAD (max) −
where ton and toff are the switching times of the turn off and turn off phases of the MOSFET.
As general rule, high side MOSFETs with low gate charge are recommended, in order to
minimize driver losses.
Below there is a list of possible choices for the high side MOSFET.
Table 14.
High side MOSFET manufacturer
Manufacturer
Type
Gate charge (nC)
Rated reverse voltage (V)
ST
STS12NH3LL
10
30
ST
STS17NH3LL
18
30
The power dissipation of the low side MOSFET is given by:
Equation 22
PDLowSide = Pconduction
Maximum conduction losses occur at the maximum input voltage:
Equation 23
⎛
V
Pconduction = RDSon × ⎜⎜1 − OUT
⎝ VIN max
⎞
⎟ × ILOAD (max)2
⎟
⎠
Choose a synchronous rectifier with low RDS(on). When high side MOSFET turns on, the fast
variation of the phase node voltage can bring up even the low side gate through its gate
drain capacitance CRSS, causing cross-conduction problems. Choose a low side MOSFET
that minimizes the ratio CRSS/CGS (CGS = CISS - CRSS).
Below there is a list of some possible low side MOSFETs.
33/47
Design guidelines
PM6681A
Table 15.
Low side MOSFET manufacturer
Manufacturer
Type
RDS(on) (mΩ)
CRSS
CGS
Rated reverse voltage (V)
ST
STS17NF3LL
5.5
0.047
30
ST
STS25NH3LL
3.5
0.011
30
Dual N-channel MOSFETs can be used in applications with a maximum output current of
about 3 A. Below there is a list of some MOSFET manufacturers.
Table 16.
Dual MOSFET manufacturer
Manufacturer
Type
RDS(on) (mΩ)
Gate charge (nC) Rated reverse voltage (V)
ST
STS8DNH3LL
25
10
30
ST
STS4DNF60L
65
32
60
A rectifier across the low side MOSFET is recommended. The rectifier works as a voltage
clamp across the synchronous rectifier and reduces the negative inductor swing during the
dead time between turning the high-side MOSFET off and the synchronous rectifier on. It
can increase the efficiency of the switching section, since it reduces the low side switch
losses. A Schottky diode is suitable for its low forward voltage drop (0.3 V). The diode
reverse voltage must be greater than the maximum input voltage VINmax. A minimum
recovery reverse charge is preferable. Below there is a list of some Schottky diode
manufacturers.
Table 17.
9.6
Schottky diode manufacturer
Manufacturer
Series
Forward voltage
(V)
Rated reverse voltage
(V)
Reverse current
(uA)
ST
STPS1L30M
0.34
30
0.00039
ST
STPS1L20M
0.37
20
0.000075
Closing the integrator loop
The design of external feedback network depends on the output voltage ripple. If the ripple
is higher than approximately 30 mV, the feedback network (Figure 39) is usually enough to
keep the loop stable.
34/47
PM6681A
Design guidelines
Figure 39. Circuitry for output ripple compensation
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The stability of the system depends firstly on the output capacitor zero frequency. The
following condition should be satisfied:
Equation 24
fsw > k × fZout =
k
2π × C out × R out
where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It
determinates the minimum integrator capacitor value CINT:
Equation 25
CINT >
gm
⎛f
⎞
2π × ⎜ sw − fZout ⎟
k
⎝
⎠
×
Vr
VOUT
where gm = 50 µs is the integrator trans conductance.
In order to ensure stability it must be also verified that:
Equation 26
CINT >
gm
Vr
×
2π × fZout VOUT
In order to reduce ground noise due to load transient on the other section, it is
recommended to add a resistor RINT and a capacitor Cfilt that, together with CINT, realize a
low pass filter (see Figure 39). The cutoff frequency fCUT must be much greater (10 or more
times) than the switching frequency of the section:
35/47
Design guidelines
PM6681A
Equation 27
RINT =
1
C × C filt
2π × fCUT × INT
CINT + C filt
Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by:
Equation 28
VRIPPLEINT = VRIPPLEout ×
CINT
= VRIPPLEout × q
CINT + C filt
Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple.
If the ripple is very small (lower than approximately 30 mV), a further compensation network,
named virtual ESR network, is needed. This additional part generates a triangular ripple
that is added to the ESR output voltage ripple at the input of the integrator network. The
complete control schematic is represented in Figure 40.
Figure 40. Virtual ESR network
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The T node voltage is the sum of the output voltage and the triangular waveform generated
by the virtual ESR network. In fact the virtual ESR network behaves like a further equivalent
ESR RESR.
A good trade-off is to design the network in order to achieve an RESR given by:
Equation 29
RESR =
36/47
VRIPPLE
− R out
∆IL
PM6681A
Design guidelines
where ∆IL is the inductor current ripple and VRIPPLE is the overall ripple of the T node
voltage. It should be chosen higher than approximately 30 mV.
The new closed loop gain depends on CINT. In order to ensure stability it must be verified
that:
Equation 30
CINT >
gm
Vr
×
2π × fZ VOUT
Where:
Equation 31
fZ =
1
2π × C out × R TOT
where RTOT is the sum of the ESR of the output capacitor Rout and the equivalent ESR
given by the virtual ESR network RESR.
Moreover CINT must meet the following condition:
Equation 32
fsw > k × fZ =
k
2π × C out × R TOT
Where k is a free design parameter greater than 3 and determines the minimum integrator
capacitor value CINT:
Equation 33
CINT >
gm
Vr
×
⎛f
⎞ VOUT
2π × ⎜ sw − fZ ⎟
k
⎝
⎠
C must be selected as shown:
Equation 34
C > 5 × CINT
R must be chosen in order to have enough ripple voltage on integrator input:
Equation 35
R=
L
RESR × C
R1 can be selected as follows:
37/47
Design guidelines
PM6681A
Equation 36
⎛
⎞
1
⎟⎟
R × ⎜⎜
×
π
×
C
f
Z ⎠
⎝
R1 =
1
R−
C × π × fZ
Example:
OUT1 = 1.5 V, fSW = 290 kHz, L = 2.5 µH, Cout = 330 µF with Rout ≈ 12 mΩ. We design
RESR = 12 mΩ. We choose CINT = 1 nF by equations 31, 34 and Cfilt = 47 pF, RINT = 1 kΩ by
eq.28, 29. C = 5.6 nF by Eq.35. Then R = 36 kΩ (eq.36) and R1 = 3 kΩ (eq.37).
9.7
Other parts design
●
VIN filter. A VIN pin low pass filter is suggested to reduce switching noise. The low pass
filter is shown in the next figure:
Figure 41. VIN pin filter
Typical components values are: R = 3.9 Ω and C = 4.7 µF.
●
VCC filter. A VCC low pass filter helps to reject switching commutations noise:
Figure 42. Inductor current waveforms
LD O5
R
VC C
C
38/47
PM6681A
Design guidelines
Typical components values are: R = 47 Ω and C = 1 µF.
●
VREF capacitor. A 10 nF to 100 nF ceramic capacitor on VREF pin must be added to
ensure noise rejection.
●
LDO5 output capacitors. Bypass the output of each linear regulator with 1 µF ceramic
capacitor closer to the LDO pin and a 4.7 µF tantalum capacitor (ESR = 2 Ω). In most
applicative conditions a 4.7 µF ceramic output capacitor can be enough to ensure
stability.
●
Bootstrap circuit. The external bootstrap circuit is represented in the next figure:
Figure 43. Bootstrap circuit
D
D
R
RBOOT
OT
LDO
O55
B
BO
OO
OTT
CBOOT
L
P
PH
HASE
The bootstrap circuit capacitor value CBOOT must provide the total gate charge to the high
side MOSFET during turn on phase. A typical value is 100 nF.
The bootstrap diode D must charge the capacitor during the off time phases. The maximum
rated voltage must be higher than VINmax.
A resistor RBOOT on the BOOT pin could be added in order to reduce noise when the phase
node rises up, working like a gate resistor for the turn on phase of the high side MOSFET.
9.8
Design example
The following design example considers an input voltage from 7 V to 16 V. The two switching
outputs are OUT1 = 1.5 V and OUT2 = 1.05 V and must deliver a maximum current of 5 A.
The selected switching frequencies are about 290 kHz for OUT1 section and about 425 kHz
for OUT2 section (see Table 1).
9.8.1
Inductor selection
OUT1: ILOAD = 2.5 A, 45 % ripple current.
L=
3.3V ⋅ (20V − 3.3V)
≈ 8.2µH
290KHz ⋅ 24V ⋅ 0.45 ⋅ 2.5
We choose standard value L = 8.2 µH.
∆IL(max) = 1.16 A @ VIN = 24 V.
ILRMS = 2.53 A
39/47
Design guidelines
PM6681A
Ipeak = 2.5 A + 0.58 A = 3.08 A
OUT2 : ILOAD = 2.5 A, 35 % ripple current.
L=
1.8V ⋅ (24V − 1.8V)
≈ 4.76µH
425KHz ⋅ 24V ⋅ 0.35 ⋅ 2.5
We choose standard value L = 4.7 µH.
∆IL(max) = 0.89 A @ VIN = 24 V.
ILRMS = 2.513 A
Ipeak = 2.5 A + 0.443 A = 2.943 A
9.8.2
Output capacitor selection
We would like to have an output ripple smaller than 25 mV.
OUT1: POSCAP 4TPE150MI
OUT2: POSCAP 6TPE220M
9.8.3
Power MOSFETs
OUT1:High side: STS5NF60L
Low side: STS7NF60L
OUT2:High side: STS5NF60L
Low side: STS7NF60L
9.8.4
Current limit
OUT1:
ILvalley (min) = ILOAD(max) −
RCSENSE ≡
∆IL (min)
= 4.12A
2
4.12A
⋅ 16.25mΩ ≈ 670Ω
100µA
(Let's assume the maximum temperature Tmax = 75 °C in RDS(on) calculation)
OUT2:
ILvalley (min) = ILOAD (max) −
40/47
∆IL (min)
= 4 .2 A
2
PM6681A
Design guidelines
RCSENSE ≡
4 . 2A
⋅ 16.25mΩ ≈ 680Ω
100µA
(Let's assume Tmax = 75 °C in RDS(on) calculation)
9.8.5
Input capacitor
Maximum input capacitor RMS current is about 1.1 A. Then ICinRMS > 1.1 A
We can put two 10 µF ceramic capacitors with Irms = 1.5 A.
9.8.6
Synchronous rectifier
OUT1: Schottky diode STPS1L40M
OUT2: Schottky diode STPS1L40M
9.8.7
Integrator loop
(Refer to Figure 40)
OUT1: The ripple is smaller than 40mV, then the virtual ESR network is required.
CINT = 1 nF; Cfilt = 47 pF; RINT = 1 kΩ
C = 5.6 nF; R = 36 kΩ; R1 = 3 kΩ
OUT2: The ripple is smaller than 40mV, then the virtual ESR network is required.
CINT = 1 nF; Cfilt = 110 pF; RINT = 1 kΩ
C = 5.6 nF; R = 22 kΩ; R1 = 3.3 kΩ
9.8.8
Output feedback divider
(Refer to Figure 32)
OUT1: R1 = 10 kΩ; R2 = 6.8 kΩ
OUT2: R1 = 11 kΩ; R2 = 1.8 kΩ
41/47
Layout guidelines
10
PM6681A
Layout guidelines
The layout is very important in terms of efficiency, stability and noise of the system. It is
possible to refer to the PM6681A demonstration board for a complete layout example.
For good PC board layout follows these guidelines:
●
Place on the top side all the power components (inductors, input and output capacitors,
MOSFETs and diodes). Refer them to a power ground plan, PGND. If possible, reserve
a layer to PGND plan. The PGND plan is the same for both the switching sections.
●
AC current paths layout is very critical (see Figure 44). The first priority is to minimize
their length. Trace the LS MOSFET connection to PGND plan (with or without current
sense resistor RSENSE) as short as possible. Place the synchronous diode D near the
LS MOSFET. Connect the LS MOSFET drain to the switching node with a short trace.
●
Place input capacitors near HS MOSFET drain. It is recommended to use the same
input voltage plan for both the switching sections, in order to put together all input
capacitors.
●
Place all the sensitive analog signals (feedbacks, voltage reference and current sense
paths) on the bottom side of the board or in an inner layer. Isolate them from the power
top side with a signal ground layer, SGND. Connect the SGND and PGND plans only in
one point (a multiple via connection is preferable to a 0 ohm resistor connection) near
the PGND device pin. Place the device on the top or on the bottom size and connect
the exposed pad and the SGND pins to the SGND plan (see Figure 44).
Figure 44. Current paths, ground connection and driver traces layout
42/47
PM6681A
Layout guidelines
●
●
●
●
●
As general rule, make the high side and low side drivers traces wide and short. The
high side driver is powered by the bootstrap circuit. It's very important to place
capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin (for
example on the layer opposite to the device). Route HGATE and PHASE traces as near
as possible in order to minimize the area between them. The Low side gate driver is
powered by the 5 V linear regulator output. Placing PGND and LGATE pins near the
low side MOSFETs reduces the length of the traces and the crosstalk noise between
the two sections.
The linear regulator output LDO5 is referred to SGND as long as the reference voltage
Vref. Place their output filtering capacitors as near as possible to the device.
Place input filtering capacitors near VCC and VIN pins.
It would be better if the feedback networks connected to COMP, FB and OUT pins are
“referred” to SGND in the same point as reference voltage Vref. To avoid capacitive
coupling place these traces as far as possible from the gate drivers and phase
(switching) paths.
Place the current sense traces on the bottom side. If low side MOSFET RDS(on) sensing
is enabled, use a dedicated connection between the switching node and the current
limit resistor RCSENSE.
43/47
Package mechanical data
11
PM6681A
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Table 18.
VFQFPN32 5 x 5 x 1.0 mm pitch 0.50
Databook (mm)
Dim.
Min
Typ
Max
A
0.8
0.9
1
A1
0
0.02
0.05
A3
0.2
b
0.18
0.25
D
4.85
5
D2
0.3
5.15
See exposed pad variations
E
4.85
E2
(2)
5
5.15
See exposed pad variations
e
(2)
0.5
L
0.3
0.4
0.5
ddd
Table 19.
0.05
Exposed pad variations
(1)(2)D2
E2
Min
Typ
Max
Min
Typ
Max
2.90
3.10
3.20
2.90
3.10
3.20
1. VFQFPN stands for thermally enhanced very thin fine pitch quad flat package no lead. Very thin:
A = 1.00 mm Max.
2. Dimensions D2 and E2 are not in accordance with JEDEC.
44/47
PM6681A
Package mechanical data
Figure 45. Package dimensions
45/47
Revision history
12
PM6681A
Revision history
Table 20.
46/47
Document revision history
Date
Revision
Changes
02-Nov-2006
1
Initial release
03-Jun-2008
2
Document status promoted from Target specification to
Datasheet
26-Jun-2008
3
Updated: Figure 1 on page 4, Figure 27 on page 16, Figure 16
and Figure 17 on page 15
PM6681A
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