SPV1050
Datasheet
Ultralow power energy harvester and battery charger
Features
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Transformerless thermoelectric generators and PV modules energy harvester
High efficiency for any harvesting source
Up to 70 mA output current
Fully integrated MOSFETs for Boost or Buck-boost configurations
Selectable enable/disable MPPT functionality
Programmable MPPT by external resistors
2.6 V to 5.3 V trimmable output overvoltage level (± 1% accuracy)
2.2 V to 3.6 V trimmable output undervoltage level (± 1% accuracy)
Two fully independent LDOs (1.8 V and 3.3 V output)
Enable/disable LDO pins
Load disconnect function (by-pass transistor open) prior the first start-up (Cold
Start) to avoid battery lifetime shortening
Battery Connected and DC-DC switching open drain indication pins
Application
Product status link
SPV1050
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Internet of things
Remote control
Fleet and livestock tracking
Agriculture sensors
Toll-pay
Electronic labels
Smart watch and wearable.
Product label
Description
The SPV1050 is an ultra-low power and high-efficiency power manager embedding
four MOSFETs for boost or buck-boost DC-DC converter and an additional transistor
for the load connection/disconnection.
An internal high accuracy MPPT algorithm can be used to maximize the power
extracted from PV panel or TEG.
The internal logic works to guarantee tight monitoring of both the end-of-charge
voltage (VEOC) and the minimum battery voltage (VUVP) by opening the passtransistor at triggering of the VEOC threshold or at triggering of the VUVP threshold
to preserve the battery life. Both the VEOC and VUVP thresholds can be trimmed by
external resistors connected between the STORE rail and the EOC and UVP pins,
respectively.
In boost configuration (CONF pin connected to the supply source), the IC requires
550 mV and 30 μA to Cold start; while after the first start-up the input voltage can
range between 150 mV and VEOC. In buck-boost configuration (CONF pin connected
to ground), the IC requires 2.6 V and 5 μA at Cold start; while after the first start-up
input voltage can range between 150 mV up to 18 V.
The STORE pin is available as unregulated voltage output (e.g. to supply by external
LDO a micro-controller), while two fully independent LDOs (1.8 V and 3.3 V) are
embedded for powering other companion ICs like MCU, sensors or RF transceivers.
Both LDOs can be independently enabled through the related pins.
DS10044 - Rev 7 - January 2022
For further information contact your local STMicroelectronics sales office.
www.st.com
SPV1050
Block Diagram
1
Block Diagram
Figure 1. Block diagram
DS10044 - Rev 7
page 2/30
SPV1050
Pin configurations
2
DS10044 - Rev 7
Pin configurations
page 3/30
SPV1050
Pin description
3
Pin description
Pin no.
(VFQFPN
20)
1
2
MPP
MPP_SET
Type
Description
I
Input voltage sense pin: to be connected to the voltage source. The
connection can be direct or through a ladder resistor, depending on the
maximum voltage of the source despite the AMR and operating range
of the MPP pin. The switching of the DC-DC is disabled when VMPP <
VEN_TH.
I
MPPT enable/disable and setting voltage pin.
Connect this pin directly to STORE pin when MPPT function is not
required: this configuration (VMPP_SET > VSTORE-VEN_TH) inhibits the
periodic deactivation of the embedded DC-DC.
If MPPT function is required, then connect MPP_SET and MPP pins
through a ladder resistor: the MPPT algorithm periodically deactivates the
DC-DC for sampling of the open circuit voltage of the source. Typically, the
DC-DC is stopped for ~400 ms every ~16 s.
I
Voltage reference pin.
The switching of the DC-DC is controlled by internal logic purposing high
conversion efficiency, even with low power sources. The switching remains
active until VMPP > VMPP_REF. Connecting this pin to ground enables
continuous switching of the DC-DC converter, provided that enough power
can be supplied by the source.
When MPPT function is required, connect this pin to a 10 nF capacitor: at
every sampling period (~16 s) this capacitor stores the reference voltage
(% of the open circuit voltage of the source) VMPP_REF.
When MPPT function is not required, connect this pin to an external
voltage reference.
3
MPP_REF
4
GND
5
LDO1_EN
I
If high, enables LDO1 (1.8V).
6
LDO2_EN
I
If high, enables LDO2 (3.3V).
7
BATT_CHG
O
DC-DC operation output flag pin (open drain): if low, it indicates that the
DC-DC is switching; if high, it indicates that the DC-DC is not switching.
8
BATT_CONN
O
Embedded pass transistor connection status pin (open drain): if low, it
indicates that the pass transistor between the STORE and BATT pins
is closed (load connected); if high, it indicates that the pass transistor
between the STORE and BATT pins is open (load disconnected).
I
Load overvoltage/battery end of charge protection pin.
To be connected to the STORE pin through a resistor divider. Internal DCDC stops/restarts switching when the voltage at EOC pin is higher/lower
than the internal bandgap voltage (VBG = 1.23 V, typical value).
Also, at start-up (internal pass transistor between STORE and BATT is
still open) and while VSTORE is increasing, the triggering of the internal
bandgap voltage makes the internal pass transistor gets closed.
9
DS10044 - Rev 7
Name
EOC
GND
Signal ground pin.
10
UVP
I
Load/battery undervoltage protection pin.
To be connected to the STORE pin through a resistor divider. Internal pass
transistor between STORE and BATT pins opens when the voltage at UVP
pin goes below the internal bandgap voltage (VBG = 1.23 V, typical value).
11
LDO1
O
1.8 V regulated output voltage pin.
12
LOD2
O
3.3 V regulated output voltage pin.
13
CONF
I
DC-DC converter configuration pin.
Boost configuration: CONF pin connected to the input supply source.
Buck-boost configuration: CONF pin connected to ground.
14
BATT
I/O
Load/battery connection pin.
page 4/30
SPV1050
Pin description
Pin no.
(VFQFPN
20)
DS10044 - Rev 7
Name
Type
I/O
Description
15
STORE
16
IN_LV
I
Low voltage input source.
It has to be connected to the inductor for both boost and buck-boost
configuration.
17
NC
-
Not connected.
18
PGND
PGND
19
L_HV
I
Input pin for buck-boost configuration.
Boost configuration: to be connected to ground.
Buck-boost configuration: to be connected to the inductor.
20
IN_HV
I
High voltage input source.
Boost configuration: to be connected to ground.
Buck-boost configuration: to be connected to the input supply source.
EP
Exposed Pad
GND
Tank capacitor connection pin.
Power ground pin.
Connect to ground layer of the application board. It's warmly
recommended a direct connection (without any vias) between EP, GND,
PGND and the ground net of the tank capacitor on STORE pin.
page 5/30
SPV1050
Maximum ratings
4
Maximum ratings
Table 1. Absolute maximum ratings
Symbol
Parameter
Value
Unit
IN_LV
Analog input
VSTORE + 0.3
V
IN_HV
Analog input
20
V
L_HV
Analog input
IN_HV +0.3
V
CONF
Analog input
5.5
V
MPP
Analog input
5.5
V
MPP_SET
Analog input
5.5
V
MPP_REF
Analog input
5.5
V
BATT
Analog input/output
5.5
V
STORE
Analog input/output
5.5
V
UVP
Analog input
VSTORE + 0.3
V
EOC
Analog input
VSTORE + 0.3
V
BATT_CONN
Digital output
5.5
V
BATT_CHG
Digital output
5.5
V
LDO1_EN
Digital input
VSTORE + 0.3
V
LDO2_EN
Digital input
VSTORE + 0.3
V
LDO1
Analog output
VSTORE + 0.3
V
LDO2
Analog output
VSTORE + 0.3
V
PGND
Power ground
0
V
GND
Signal ground
-0.3 to 0.3
V
TJ
Junction temperature
-40 to 125
oC
TSTORAGE
Storage temperature
150
oC
Table 2. Thermal data
Symbol
Parameter
Value
Unit
Rth(JC)
Thermal resistance junction-case
7.5
°C/W
Rth(JA) (1)
Thermal resistance junction-ambient
49
°C/W
1. Measured on 2-layer application board FR4, Cu thickness = 17 um with total exposed pad area = 16 mm2
DS10044 - Rev 7
page 6/30
SPV1050
Electrical characteristics
5
Electrical characteristics
VSTORE = 4 V; -40 °C < TJ < 85 °C, unless otherwise specified. Voltage with respect to GND, unless otherwise
specified
Table 3. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
-
-
70
30
-
-
2.2
-
5.3
V
6
7
8
Ω
Internal reference voltage
-
1.23
-
V
Accuracy
-1
-
+1
%
2.2
-
3.6
V
-
5
-
%
2.6
-
5.3
V
-
-1
-
%
Load/battery operating range
IBATT
Output current to load/
battery
VBATT
BATT pin voltage range
RBATT
Pass transistor resistance
boost configuration
buck-boost configuration
BATT_CONN = low
mA
Bandgap
VBG
UVP
VSTORE(UVP)
VSTORE undervoltage
protection range
(VUVP + UVPHYS) < (VEOC - EOCHYS)
UVPHYS
UVP hysteresis
VSTORE rising
VSTORE(EOC)
VSTORE end-of-charge
voltage range
(VUVP + UVPHYS) < (VEOC - EOCHYS)
EOCHYS
EOC hysteresis
VSTORE falling
EOC
STORE
VSTORE
VSTORE(
STORE pin voltage
operating range
UVP)
-
VSTORE(
EOC)
V
Static current consumption
ISD
ISB
IOP
Shutdown current
Shutdown mode: before first start-up or
BATT_CONN high
TAMB < 60 °C
-
-
1
nA
Standby current
Standby mode:
BATT_CONN low, BATT_CHG high,
VSTORE = 5.3 V, VMPP < VEN_TH and
LDO1,2_EN low
TAMB = 25 °C
-
0.8
-
μA
LDO1_EN = 1
or
LDO2_EN = 1
-
1.7
-
Operating current in open
load
Operating mode (LDOs
in open load),
BATT_CONN low,
BATT_CHG high,
TAMB = 25 °C
LDO1_EN = 1
and
LDO2_EN = 1
-
2.6
-
Boost configuration, BATT_CONN high
or at first start-up
-
0.55
0.58
Buck-boost configuration BATT_CONN
high or at first start-up
-
μA
DC-DC converter
VIN-SU
DS10044 - Rev 7
Cold start minimum input
voltage
V
2.6
2.8
page 7/30
SPV1050
Electrical characteristics
Symbol
Parameter
ISU
Cold start minimum input
current
VEN_TH
DC-DC switching enable
threshold
VIN_LV
VIN_HV
Input voltage range
R-ONB
Low-side MOS resistance
SR-ONB
Synchronous rectifier MOS
resistance
R-ONBB
Low-side MOS resistance
Test conditions
Min.
Typ.
Max.
Boost configuration
-
30
-
Buck-boost configuration
-
5
-
0.1
0.15
Voltage checked during TSAMPLE
Boost configuration
VEN_TH
-
VEOC
Buck-boost configuration
VEN_TH
-
18
0.5
1.0
1.5
0.5
1.0
1.5
1
1.5
2
1
1.5
2
Boost configuration
Buck-boost configuration
Unit
μA
V
V
Ω
Ω
SR-ONBB
Synchronous rectifier MOS
resistance
fSW
Maximum allowed
switching frequency
Boost and buck-boost configurations
-
-
1
MHz
UVLOH
Undervoltage lockout
activation threshold
VSTORE increasing
-
2.6
2.8
V
UVLOL
Undervoltage lockout
deactivation threshold
VSTORE falling
2
2.1
-
V
IL(PEAK)
DC-DC input current high
peak threshold
DC-DC active and input current rising
(TAMB = 25oC)
85
190
mA
IL(ZC)
DC-DC output current low
threshold
DC-DC active and input current falling
(TAMB = 25oC)
0
82
mA
TON(MAX)
DC-DC ON Time
DC-DC maximum ON time
10
μs
TOFF(MIN)
DC-DC OFF Time
DC-DC- minimum OFF time
0.2
TTRACKING
MPPT tracking period
BATT_CHG low
12
20
s
TSAMPLE
MPPT sampling time
BATT_CHG high
0.3
0.5
s
VMPP
MPP pin voltage range
MPPT enabled, MPPTRATIO = 50%,
VMPP(MAX) = 150mV, DC-DC switching
(see Section 6.4 MPPT setting)
0.075
VUVP
-0.1
V
MPPACC
MPP tracking accuracy
Boost and buck-boost configurations
LDO1,2 adjusted output
voltage
LDO1_EN = 1
1.8
LDO2_EN = 1
3.3
μs
MPPT
95
%
LDO
VLDO1,2
LDO1 dropout
VUVP + 200 mV < VSTORE ≤ 5.3 V; ILDO1
= 100 mA
0.5
LDO2 dropout
3.3 V < VUVP + 200 mV < VSTORE ≤ 5.3
V; ILDO2 = 100 mA
0.5
LDO1,2 START-up time
BATT_CONN = low; CLDO1,2 = 100 nF
ΔVLDO1,2
tLDO
ILDO1,2(1)
V
IOUT max from LDO1
IOUT max from LDO2
BATT_CONN= low
%
-
-
1
ms
-
-
200
mA
-
-
200
mA
VLDO1,2_EN_H
LDO1,2 enable input HIGH
1
-
-
V
VLDO1,2_EN_L
LDO1,2 enable input LOW
-
-
0.5
V
Digital output
DS10044 - Rev 7
page 8/30
SPV1050
Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
VBATT_CONN_L
BATT_CONN voltage drop
1 mA sink current; BATT_CONN = low
40
70
150
mV
VBATT_CHG_L
BATT_CHG voltage drop
1 mA sink current; BATT_CHG = low
40
70
150
mV
1. Guaranteed by design, not tested in production.
DS10044 - Rev 7
page 9/30
SPV1050
Functional description
6
Functional description
The SPV1050 can be used as energy harvester or normal DC-DC converter, depending on the activation or
deactivation of the embedded MPPT algorithm (by MPP_SET pin setting). Also, the IC offers both load overvoltage and under-voltage control, which fit with the most typical requirements of battery charger applications. The
additional unregulated (STORE) and regulated (LDO1, LDO2) voltage rails makes the IC suitable to be used as
power manager.
Independently by the activation/deactivation of the MPPT function, the DC-DC converter stage can be configured
as boost or buck-boost by tying the CONF pin to the input source or to ground, respectively. See Figure 4. Boost
configuration example and Figure 12. Buck-boost configuration example.
If the embedded MPPT algorithm is enabled (MPP and MPP_SET pins connected to input source by a resistor
partitioning), the device periodically stops the switching of the DC-DC converter to do a sampling of the input
voltage and to store it on the capacitor connected at MPP_REF pin. When the sampling time elapses, the IC
restarts operating: if VMPP > VMPP_REF, then the DC-DC can switch according the internal driving sequence
purposing the optimization of the conversion efficiency. The selection of the resistor partitioning at the input
stage, according to the electrical characteristic of the harvested source, allows the IC to maximize the power
extracted: see further details in Section 6.2 Boost configuration,Section 6.3 Buck-boost configuration and
Figure 19. MPPT setup circuitry.
The MPPT algorithm can be disabled by shorting the MPP_SET pin to the STORE pin. In this application case
the MPP_REF pin is usually connected to a voltage reference. In case of low impedance source (e.g. USB), the
MPP_REF is normally connected to GND: the IC tries switching at highest duty cycle. In case of high impedance
source (limited current capability, i.e. the source in unable to sustain the continuous switching at maximum duty
cycle), the MPP_REF pin can be connected to a reference voltage (VEXT_REF) such that the IC stops switching
when VMPP < VEXT_REF. This voltage reference can be set through a resistor ladder connected to STORE rail or
to any other voltage reference available.
6.1
Battery voltage control
The IC integrates a pass transistor between the STORE and BATT pins to implement both the undervoltage and
the overvoltage protection thresholds. These thresholds are respectively controlled by the pins UVP and EOC,
normally connected to the STORE pin by a resistor partitioning. The respective voltages (VUVP and VEOC) are
compared with the IC internal voltage reference (VBG = 1.23 V, typical value).
Those protection thresholds guarantee the lifetime and the safety of the battery.
DS10044 - Rev 7
page 10/30
SPV1050
Battery voltage control
Figure 2. Battery management section
Before the first startup (cold start) the pass transistor is open, so that the leakage from the output is lower than
1 nA. The pass transistor is closed once the (rising) voltage on the STORE pin triggers the overvoltage threshold
VSTORE(EOC) (corresponding to VEOC > VBG). An internal hysteresis (EOCHYS) sets the restart voltage level for
DC-DC converter. The IC also offers the undervoltage protection threshold: the pass transistor is opened once the
(falling) voltage on the STORE pin decreases down to the undervoltage threshold VSTORE(UVP) (corresponding to
VUVP < VBG).
Referring to Figure 2. Battery management section, the design rules to set up the R4, R5 and R6 are the
following:
Equation 1:
set the total output resistance (ROUT(TOT) = R4 + R5 + R6) to minimize its leakage:
•
10 MΩ ≤ ROUT(TOT) ≤ 20 MΩ
Equation 2:
•
R6 = (VBG / VEOC) × ROUT(TOT)
Equation 3:
•
R5 = (VBG / VUVP) × ROUT(TOT) - R6
In addition, the IC provides two open drain digital outputs to an external microcontroller:
BATT_CONN
•
This pin is pulled down when the pass transistor is closed. It will be released once the pass transistor will be
opened. If used, this pin must be pulled up to the STORE rail by resistor (10 MΩ, typically) .
•
DS10044 - Rev 7
BATT_CHG
This pin is pulled down when the DC-DC converter is switching, while it's released when it is not switching,
i.e. it is high after STORE triggers VSTORE(EOC) and until it drops by EOCHYS , or when the UVLOL threshold
is triggered, or during the sampling period (TSAMPLE ) of the MPPT algorithm. If used, this pin must be
pulled-up to the STORE rail by a resistor (10 MΩ, typically).
page 11/30
SPV1050
Boost configuration
For some applications (typically with battery or super-cap connected to BATT pin) it could be necessary to
implement a reactivation hysteresis after undervoltage event (pass transistors status changes from closed to
open): it avoids the undesired continuous system reset loop due to full discharge of the CSTORE at every triggering
of the overvoltage threshold. The application solution is simply based on a diode (or p-channel MOSFET driven
by BATT_CONN) between STORE and BATT pins.
Figure 3. Implementations examples of larger UVP hysteresis
6.2
Boost configuration
Figure 4. Boost configuration example below shows an example of boost application circuit.
Figure 4. Boost configuration example
In case of boost configuration, once the source is connected, the SPV1050 will start boosting the voltage on the
STORE rail. In the range of 0 ≤ VSTORE < 2.6 V the voltage boost is carried on by an integrated high-efficiency
charge pump, while the DC-DC converter stage remains OFF.
Figure 5. Boost start-up shows the behavior of input voltage VIN (voltage supplied by the source) and VSTORE at
the start-up.
DS10044 - Rev 7
page 12/30
SPV1050
Boost configuration
Figure 5. Boost start-up
In the range 2.6 V ≤ VSTORE < VSTORE(EOC) the voltage on STORE rail is boosted by the DC-DC converter
that operates driven by internal logic until VMPP > VMPP_REF. Switching activity of the DC-DC is controlled by
internal logic: ON phase stops at triggering of IL(PEAK) (peak current through the inductor) and can't be longer than
TON(MAX) ; OFF phase can't be shorter than TOFF(MIN). Also, purposing highest efficiency with low power source,
the first ON phase after reactivation of the DC-DC is limited a triggering of IL(PEAK) / 2.
If the MPPT mode is active, then the IC stops switching for ~400 ms (TSAMPLE) every ~16 seconds (TTRACKING).
During the TSAMPLE, the IC goes in high impedance and the open circuit voltage VOC at input stage is sampled
and stored by charging the CREF (capacitor on the MPP_REF pin) through the MPP_SET pin.
Once the TSAMPLE is elapsed, the DC-DC converter will start switching back: the IC impedance is set featuring the
VIN stays as close as possible to the VMPP_REF. The periodic sampling of VOC guarantees the best MPPT in case
of source condition variations (e.g. irradiation/thermal gradient and/or temperature changes).
A resistor partitioning connected between the source and the pins MPP and MPP_SET has to be properly
selected, in order to match the source manufacturer's specs: refer to Section 6.4 MPPT setting for further details.
Figure 6. MPPT tracking shows the input voltage waveform of a PV panel supplying
VOC = 1.25 V and VMP = 1.05 V.
DS10044 - Rev 7
page 13/30
SPV1050
Boost configuration
Figure 6. MPPT tracking
Once the voltage at STORE pin triggers the VSTORE(EOC) the switching of the DC-DC converter stops until
VSTORE decreases below the threshold defined by the internal hysteresis.
Figure 7. Triggering of VEOC (BATT pin floating)
DS10044 - Rev 7
page 14/30
SPV1050
Boost configuration
The following plots (Figure 8. Efficiency vs. input current; VOC = 1.0 V, Figure 9. Efficiency vs. input current; VOC
= 1.5 V, Figure 10. Efficiency vs. input current; VOC = 2.0 V, Figure 11. Efficiency vs. input current; VOC = 2.5 V)
show the power efficiency of the DC-DC converter configured in boost mode at TAMB = 25 °C in some typical use
cases at different open circuit voltages (MPPTRATIO = 83%):
Figure 8. Efficiency vs. input current; VOC = 1.0 V
0.9
0.85
0.8
Efficiency
Pout/Pin [%]
0.75
0.7
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.65
0.6
0.55
0.5
0.45
0.4
0.01
0.1
1
10
100
Input current [mA]
AM03745
Figure 9. Efficiency vs. input current; VOC = 1.5 V
0.9
0.85
Efficiency
Pout/Pin [%]
0.8
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.75
0.7
0.65
0.6
0.01
0.1
1
10
100
Input current [mA]
AM03746
Figure 10. Efficiency vs. input current; VOC = 2.0 V
1
0.95
0.9
Efficiency
Pout/Pin [%]
0.85
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.8
0.75
0.7
0.65
0.6
0.01
0.1
1
10
100
Input current [mA]
AM03747
DS10044 - Rev 7
page 15/30
SPV1050
Buck-boost configuration
Figure 11. Efficiency vs. input current; VOC = 2.5 V
1
0.95
0.9
Efficiency
Pout/Pin [%]
0.85
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.8
0.75
0.7
0.65
0.6
0.01
0.1
1
10
100
Input current [mA]
AM03748
6.3
Buck-boost configuration
Figure 12. Buck-boost configuration example shows an example of buck-boost application circuit.
Figure 12. Buck-boost configuration example
BATT
STORE
IN_LV
Input source
CONTROL
DRIVERS
IN_HV
+
+
-
UVP
EOC
L_HV
CONTROL
LOGIC
STORE
1.8 V
MPP
LDO1
STORE
C STORE
Battery
TO LOAD1
MPP_SET
MPPT
3.3 V
MPP_REF
LDO1_EN
LDO2
TO LOAD2
_____ _____
BATT_CON
_____ _____
BATT_CHG
LDO2_EN
CONF
Cin
PGND
GND
AM03399
In case of buck-boost configuration, once the harvested source is connected, the IN_HV and STORE pins will be
internally shorted until VSTORE < 2.6 V. Figure 13. Buck-boost start-up (IIN = 5 μA) shows the behavior of the input
voltage VIN_HV and VSTORE at the start-up.
DS10044 - Rev 7
page 16/30
SPV1050
Buck-boost configuration
Figure 13. Buck-boost start-up (IIN = 5 μA)
In the range 2.6 V ≤ VSTORE < VSTORE(EOC) the integrated DC-DC switches until VMPP > VMPP_REF.
If the MPPT function is active, then the IC stops switching for ~400ms (TSAMPLE) every ~16 seconds (TTRACKING).
During the TSAMPLE, the open circuit voltage VOC of the input source is sampled and stored by charging the CREF
(capacitor on the MPP_REF pin) through the MPP_SET pin. Once the TSAMPLE is elapsed, the DC-DC converter
operates again driven by the internal logic and such that VIN (voltage supplied by the source) stays as close as
possible to the maximum power point of the source. The periodic sampling of VOC guarantees the best MPPT in
case of source condition variations (e.g. irradiation and/or temperature changes).
A resistor partitioning connected between the source and the pins MPP and MPP_SET has to be properly
selected in order to match the electrical characteristics of the source given by the manufacturer. Please refer to
Section 6.4 MPPT setting for further details.
Figure 14. MPPT tracking shows the MPPT tracking form in case of VOC = 9.9 V and voltage at maximum power
point VMP = 8.2 V.
DS10044 - Rev 7
page 17/30
SPV1050
Buck-boost configuration
Figure 14. MPPT tracking
The following plots (Figure 15. Efficiency vs. input current - VOC = 6V , Figure 16. Efficiency vs. input current VOC = 9V , Figure 17. Efficiency vs. input current - VOC = 12V , Figure 18. Efficiency vs. input current - VOC =
15V ) show the power efficiency of the DC-DC converter configured in buck-boost mode at TAMB = 25 °C in some
typical use cases (MPPTRATIO = 83%):
Figure 15. Efficiency vs. input current - VOC = 6V
0.85
Efficiency
Pout/Pin [%]
0.8
0.75
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.7
0.65
0.6
0.01
0.1
1
10
100
Input current [mA]
AM03750
DS10044 - Rev 7
page 18/30
SPV1050
Buck-boost configuration
Figure 16. Efficiency vs. input current - VOC = 9V
0.85
Efficiency
Pout/Pin [%]
0.8
0.75
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.7
0.65
0.6
0.01
0.1
1
10
100
Input current [mA]
AM03751
Figure 17. Efficiency vs. input current - VOC = 12V
0.85
Efficiency
Pout/Pin [%]
0.8
0.75
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.7
0.65
0.6
0.01
0.1
1
10
100
Input current [mA]
AM03752
Figure 18. Efficiency vs. input current - VOC = 15V
0.85
Efficiency
Pout/Pin [%]
0.8
0.75
Vbatt = 4.2 V
Vbatt = 3.7 V
Vbatt = 3.0 V
0.7
0.65
0.6
0.01
0.1
1
10
100
Input current [mA]
AM03753
DS10044 - Rev 7
page 19/30
SPV1050
MPPT setting
6.4
MPPT setting
When MPPT is enabled, the SPV1050 can regulate its impedance to extract the maximum power from the
harvesting source. Typically, the datasheet of an harvesting source reports the main electrical characteristics:
open circuit voltage (VOC) and voltage at maximum power (VMP); the MPPTRATIO is consequently calculated as
VMP/VOC. Referring to PV panels and TEGs, the VMP and VOC can change according to the external conditions
(light irradiation, temperature), but usually the effect on MPPTRATIO remains limited.
The highest MPPT accuracy of the SPV1050 can be achieved only by a proper selection of the resistors at the
input stage (R1, R2, R3).
Figure 19. MPPT setup circuitry
R1
MPP
R2
MPP_SET
Source
R3
MPPT
MPP_REF
Cin
C REF
PGND
GND
AM03400
To select R1, R2 and R3 it is necessary to set some application parameters and then apply the below equations
from 4 to 7.
•
Electrical characteristics of the harvesting source
–
VOC(MAX), intended as VOC at max operating condition of the source
–
•
Application constraints
–
ILEAKAGE, intended as the acceptable leakage through the resistors at the input stage
–
•
Usually, 0.1 μA ≤ ILEAKAGE ≤ 1 μA fits for most of the applications.
SPV1050 constraints
–
VEN_TH (MAX) ≤ VMPP(MAX) ≤ (VUVP(MIN) - 100 mV) ⇒
150 mV ≤ VMPP(MAX) ≤ 2.1 V
–
DS10044 - Rev 7
MPPTRATIO , intended as VMP/VOC at typical operating conditions of the source
VMPP(MAX) < VOC(MAX)
page 20/30
SPV1050
MPPT setting
Equation 4:
RIN(TOT) = R1 + R2 + R3 > (VOC(MAX) / ILEAKAGE ) × MPPTRATIO
Equation 5:
R1 = RIN(TOT) × [ 1 - (VMPP(MAX) / VOC(MAX) ) ]
Equation 6:
R2 = RIN(TOT) × (VMPP(MAX) / VOC(MAX) ) × (1 - MPPTRATIO)
Equation 7:
R3 = RIN(TOT) × (VMPP(MAX) / VOC(MAX) ) × MPPTRATIO
Example:
Harvesting source is a PV panel with VMP(TYP) = 1.5 V and VOC(TYP) = 2.0 V ( ⇒ MPPTRATIO = 75%). At
maximum light irradiation VOC(MAX) = 2.2 V.
VMPP(MAX) could be set between 0.15 V and 2.1 V: in this example we can assume that VMPP(MAX) = 0.50 V ( =
33% of VMP(TYP)).
In general, VMPP(MAX) depends on the power supplied by the PV panel at low light irradiation and on the minimum
acceptable conversion efficiency of the DC-DC.
Hence set
•
VOC(MAX) = 2.2 V
•
VMPP(MAX) = 0.5 V
•
ILEAKAGE = 0.1 μ A
RIN(TOT) = (2.2 V / 0.1 uA) × 0.75 = 16.5 MΩ
R1 =16.5 MΩ × [ 1 - (0.5 V / 2.2 V) ] = 12.75 MΩ
R2 =16.5 MΩ × (0.5 V/ 2.2 V) × (1- 0.75) = 0.94 MΩ
R3 =16.5 MΩ × (0.5 V/ 2.2 V) × 0.75 = 2.81 MΩ
Also, the MPPT accuracy can be strongly affected by an improper selection of the input capacitor. The input
capacitance CIN = 4.7 μF generally covers the most typical use cases.
The energy extracted from the source, and stored on CIN, is transferred to the load by the DC-DC converter
through the inductor. The energy extracted by the inductor depends by the sink current: the higher input currents
cause higher voltage drop on the input capacitance and this may result a problem for low voltage (< 1 V) and high
energy (> 20 mA) sources. In such application cases the input capacitance has to be increased or, alternatively
the L1 inductance has to be reduced.
During the TSAMPLE time frame the input capacitor CIN is charged up to VOC by the source with a time constant
(T1) resulting from the capacitance and the equivalent resistance REQ of the source.
In case of PV source, being IMP the minimum operating current for MPPT, the REQ can be calculated as following:
Equation 8:
•
REQ = (VOC - VMP) / IMP = VOC × (1 - MPPRATIO) / IMP
Thus CIN is calculated by the following formula:
Equation 9:
•
CIN ≤ T1 /REQ
The following plots (Figure 20. Energy harvester equivalent circuit, Figure 21. Voltage vs. time at different C
values and fixed current) show the effect of different CIN values on the time constant. If the capacitance is too
high, the capacitor may not be charged within the TSAMPLE = 400 ms time window, thus affecting the MPPT
accuracy.
DS10044 - Rev 7
page 21/30
SPV1050
Power manager
Figure 20. Energy harvester equivalent circuit
REQ
VE Q
I MPP
C1
VC1
AM03401V1
Figure 21. Voltage vs. time at different C values and fixed current
6.5
Power manager
The SPV1050 device works as a power manager by providing two regulated voltages on the LDO1 (1.8 V) and
LDO2 (3.3 V) pins.
Each LDO can be selectively enabled or disabled by driving the related enable/disable pins LDO1_EN and
LDO2_EN. The performances of the LDOs can be optimized by selecting a proper capacitor between the LDO
output pin and ground. A 100 nF for each LDO pin is suitable for the most typical use cases.
Figure 22. LDO1 turn on with 100 mA load and Figure 23. LDO2 turn on with 100 mA load show the behavior of
the LDOs when a 100 mA load is connected.
DS10044 - Rev 7
page 22/30
SPV1050
Power manager
Figure 22. LDO1 turn on with 100 mA load
Figure 23. LDO2 turn on with 100 mA load
Note that the internal logic inhibits both LDOs when the embedded pass transistor is open, that is when the
battery is not connected. Also, the LDOs are both supplied by the STORE rail: if the input source is unable to
sustain the current required by the load, then the missing energy will be supplied by the battery connected to the
BATT pin. In this case, the current from the battery causes a voltage drop between STORE and BATT pins due to
the resistance of the pass transistor:
VSTORE = VBATT - (RBATT * ILOAD).
If VSTORE drops and UVP pin triggers the undevoltage threshold, then the pass transistor gets open and the load
is no longer supplied until next end of charge condition is reached.
DS10044 - Rev 7
page 23/30
SPV1050
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
7.1
Package and packing information
Figure 24. VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 package outline
DS10044 - Rev 7
page 24/30
SPV1050
Package and packing
information
Table 4. VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4 package mechanical data
Symbol
Dimensions [mm](1)
Min.
Typ.
Max.
A
0.80
0.90
1.0
A1
-
0.02
0.05
A2
-
0.65
1.00
A3
-
0.20
-
b
0.15
0.20
0.25
D
2.85
3.00
3.15
D1
-
1.60
-
D2
1.50
1.60
1.70
E
2.85
3.00
3.15
E1
-
1.60
-
E2
1.50
1.60
1.70
e
0.35
0.40
0.45
L
0.30
0.40
0.50
ddd
-
-
0.07
1. “VFQFPN” stands for “Thermally Enhanced Very thin Fine pitch Quad Packages No lead”. Very thin: 0.80 < A ≤ 1.00 mm /
fine pitch: e < 1.00 mm.
Figure 25. Recommended footprint of VFQFPN20 3 x 3 x 1 mm - 20-lead pitch 0.4
DS10044 - Rev 7
page 25/30
SPV1050
Package and packing
information
Figure 26. Tape and reel design
DS10044 - Rev 7
page 26/30
SPV1050
Ordering information
8
DS10044 - Rev 7
Ordering information
Order code
Op. temp. range [oC]
Package
Packing
SPV1050TTR
-40 to 85
VFQFPN 3 x 3 x 1 20L
Tape and reel
page 27/30
SPV1050
Application tips
Appendix A Application tips
In the DC-DC converters the energy is transferred from the input to the output through the inductor. During the ON
phase of the duty cycle the inductor stores energy; during the OFF phase of the duty cycle the energy is released
toward the output stage.
Figure 27. Inductor current and input voltage waveforms
IL(PEAK)
LOW INPUT POWER
VIN - VSTORE
* TOFF
L
VIN
TON
L *
ILH
~
IL(MIN)
T
Internal
Driving Signal
TON
ON
TON(MAX)
TOFF
TOFF(MIN)
OFF
~
VIN
~
The SPV1050 activates the driving signal of the DC-DC when VMPP > VMPP_REF. During the ON phase of the
driving signal, the inductor is loaded for TON until one of the following events occurs:
•
VSTORE triggers the overvoltage threshold
•
The inductor current (IL) triggers the internal threshold IL(PEAK) (= 140 mA, typ.)
•
TON(MAX) = 10 μs elapses
In the OFF phase the energy stored in the inductor will be released to the output stage: during TOFF the IL
decreases to ILZC. According to the internal controls of the IC, TOFF(MIN) = 0.2 μs: in order to prevent IL goes
negative, the application must be designed such that the energy stored in the inductor during TON is always
greater than, or equal to, the energy released during TOFF. This goal can be achieved through the proper
selection of R2 + R3. Thus, in order to guarantee IL(MIN) > 0, it must be:
Equation 10:
•
IL(MIN) = IH - (VSTORE - VIN)×(TOFF(MIN)/L) > 0
Equation 11:
•
IL(MIN) = (VIN/L) × TON(MAX)- (VSTORE - VIN)×(TOFF(MIN)/L) > 0
leading
Equation 12:
•
VIN > VSTORE × (TOFF(MIN)/(TON(MAX) + TOFF(MIN)) = VSTORE / 51
As worst case for the above equation it can be considered VSTORE at the overvoltage level.
The resistor R1, part of the partitioning at the input stage, can be used purposing the DC-DC switch-off before
IL(MIN) ≤ 0.
VMPP = VIN *(R2+R3)/(R1+R2+R3) < VEN_TH
DS10044 - Rev 7
page 28/30
SPV1050
Revision history
Table 5. Document revision history
Date
Version
Changes
25-Nov-2013
1
Initial release.
28-Aug-2014
2
Document status promoted from preliminary data to production data, with
comprehensive update of electrical characteristic sand graphic content
throughout the document.
18-Dec-2014
3
Document status corrected to reflect current phase of product development.
06-Aug-2015
4
Minor text edits throughout the document. Added maximum values for Rth
and Rth j-a in Table 2: Thermal data, with associated footnote. Multiple
changes to parameters, test conditions and values in Table 4: Electrical
characteristics. Modified text in Section 6: Functional description and Section
6.4: MPPT setting. Removed order code SPV1050T from Table 7: Device
summary, and modified package and packing values for order code SPV1050WST. Added Appendix A: Application tips
17-May-2018
5
Added Figure 26 on page 32. Minor modifications throughout the document
12-Oct-2021
6
Changed datasheet formatting. Front page: rephrased Features list and
Description; extended Application list. Block diagram: added details of the
input stage with internal control thresholds. Pin Description: rephrased
descriptions of input and output stage pins. Electrical characteristics: minor
editing fixes; added VEN_TH, IL(PEAK), IL(ZC) , TON(MAX) and TOFF(MAX)
parameters. Chapter 6: minor editing; added application examples for the
management of larger UVP hysteresis. Chapter 6.4: reviewed calculation of
input resistor partitioning. Deleted Appendix A.
26-Jan-2022
7
Updated cover image in the front page, pin configuration, ordering information
and package information: deleted any reference to die form.
Corrected editing error in Equation 1.
j-c
DS10044 - Rev 7
page 29/30
SPV1050
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DS10044 - Rev 7
page 30/30
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