ST72344xx, ST72345xx
8-bit MCU with up to 16 Kbytes Flash memory, 10-bit ADC,
two 16-bit timers, two I2C, SPI, SCI
Datasheet −production data
Features
■
■
■
■
■
Memories
– up to 16 Kbytes Program memory: single
voltage extended Flash (XFlash) with readout and write protection, in-circuit and inapplication programming (ICP and IAP).
10,000 write/erase cycles guaranteed, data
retention: 20 years at 55 °C.
– up to 1 Kbyte RAM
– 256 bytes data EEPROM with readout
protection. 300,000 write/erase cycles
guaranteed, data retention: 20 years at
55 °C.
Clock, reset and supply management
– Power on / power off safe reset with
3 programmable threshold levels (LVD)
– Auxiliary voltage detector (AVD)
– Clock sources: crystal/ceramic resonator
oscillators, high-accuracy internal RC
oscillator or external clock
– PLL for 4x or 8x frequency multiplication
– 5 power-saving modes: Slow, Wait, Halt,
Auto-wakeup from Halt and Active-halt
– Clock output capability (fCPU)
Interrupt management
– Nested interrupt controller
– 10 interrupt vectors plus TRAP and RESET
– 9 external interrupt lines on 4 vectors
Up to 34 I/O ports
– up to 34 multifunctional bidirectional I/O
lines
– up to 12 high sink outputs (10 on 32-pin
devices)
4 timers
– Configurable window watchdog timer
– Real-time base
– 16-bit timer A with: 1 input capture, 1 output
compare, external clock input, PWM and
pulse generator modes
July 2012
This is information on a product in full production.
LQFP48
7 x 7 mm
LQFP32
7 × 7 mm
LQFP44
10 × 10 mm
– 16-bit timer B with: 2 input captures, 2
output compares, PWM and pulse
generator modes
■
3 communication interfaces
– I2C multimaster / slave
– I2C slave 3 addresses, no stretch, with
DMA access and byte pair coherency on
I²C read
– SCI asynchronous serial interface (LIN
compatible)
– SPI synchronous serial interface
■
1 analog peripheral
– 10-bit ADC with 12 input channels (8 on 32pin devices)
■
Instruction set
– 8-bit data manipulation
– 63 basic instructions with illegal opcode
detection
– 17 main addressing modes
– 8 x 8 unsigned multiply instruction
■
Development tools
– Full hardware/software development
package
– On-chip debug module
Table 1.
Device summary
References
Part numbers
ST72344xx
ST72344K2, ST72344K4,
ST72344S2, ST72344S4
ST72345xx
ST72345C4
Doc ID 12321 Rev 6
1/247
www.st.com
1
Contents
ST72344xx, ST2345xx
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Register and memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4
Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3
Programming modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.1
In-circuit programming (ICP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.2
In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.4
ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.5
Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.6
4.5.1
Readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.5.2
Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.6.1
5
Data EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3
Memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4
Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.1
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.2
Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.4.3
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.5
Access error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.6
Data EEPROM readout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.7.1
6
2/247
Flash control/status register (FCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
EEPROM control/status register (EECSR) . . . . . . . . . . . . . . . . . . . . . . 35
Central processing unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
7
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.1
Condition code register (CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.3.2
Stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Supply, reset and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.1
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7.2
Phase locked loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.3
Multioscillator (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.4
7.5
7.6
8
Contents
7.3.1
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.2
Crystal/ceramic oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7.3.3
Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.1
RC control register (RCCRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
7.4.2
RC control register (RCCRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Reset sequence manager (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.5.2
Asynchronous external RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.5.3
External power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.5.4
Internal low-voltage detector (LVD) reset . . . . . . . . . . . . . . . . . . . . . . . . 48
7.5.5
Internal watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
System integrity management (SI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.6.1
Low-voltage detector (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.6.2
Auxiliary-voltage detector (AVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.6.3
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6.4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
7.6.5
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.2
Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3
Interrupts and low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.4
Concurrent & nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
8.5
Interrupt register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
8.5.1
CPU CC register interrupt bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Doc ID 12321 Rev 6
3/247
Contents
ST72344xx, ST2345xx
8.5.2
8.6
External interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8.6.1
8.7
9
10
Power-saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.2
Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.3
Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.4
Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.5
Active-halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
9.6
Auto-wakeup from Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
9.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.7.1
AWUFH control/status register (AWUCSR) . . . . . . . . . . . . . . . . . . . . . . 72
9.7.2
AWUFH prescaler register (AWUPR) . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.1
Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.2.2
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.2.3
Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
10.3
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O port implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1
4/247
I/O port interrupt sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
External interrupt control register (EICR) . . . . . . . . . . . . . . . . . . . . . . . . . 61
10.5.1
11
Interrupt software priority registers (ISPRX) . . . . . . . . . . . . . . . . . . . . . 58
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.4
Using Halt mode with the WDG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1.5
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.1.6
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.1.7
Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Contents
11.1.8
Using Halt mode with the WDG (WDGHALT option) . . . . . . . . . . . . . . . 87
11.1.9
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.1.10 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.2
11.3
11.4
11.5
Main clock controller with real-time clock and beeper (MCC/RTC) . . . . . 88
11.2.1
Programmable CPU clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.2
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.3
Real-time clock timer (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.4
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.2.5
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.2.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
11.2.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.3.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.3.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.3.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.3.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
11.3.6
Summary of timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11.3.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
11.4.4
Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
11.4.5
Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
11.4.6
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
11.4.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.4.8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SCI serial communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.5.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.5.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11.5.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
11.5.5
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
11.5.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
11.5.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Doc ID 12321 Rev 6
5/247
Contents
ST72344xx, ST2345xx
11.6
11.7
11.8
12
I2C bus interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.6.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.6.5
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.6.6
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
11.6.7
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
I2C triple slave interface with DMA (I2C3S) . . . . . . . . . . . . . . . . . . . . . . 167
11.7.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.7.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
11.7.3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
11.7.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
11.7.5
Address handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
11.7.6
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
11.7.7
Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
11.7.8
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
10-bit A/D converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.8.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.8.2
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
11.8.3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
11.8.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
11.8.5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
11.8.6
Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.1
12.2
ST7 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
12.1.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
12.1.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.1.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.1.4
Indexed (No Offset, Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
12.1.5
Indirect (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12.1.6
Indirect Indexed (Short, Long) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
12.1.7
Relative Mode (direct, indirect) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Instruction groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
12.2.1
6/247
Illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
13
Contents
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
13.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
13.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
13.4
Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
13.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
13.6
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
13.6.1
Crystal and ceramic resonator oscillators . . . . . . . . . . . . . . . . . . . . . . 210
13.7
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
13.8
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
13.9
13.8.1
Functional EMS (electromagnetic susceptibility) . . . . . . . . . . . . . . . . . 213
13.8.2
EMI (electromagnetic interference) . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
13.8.3
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . 214
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
13.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
13.11 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 224
13.11.1 I2C and I²C3SNS interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
13.12 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
14
15
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.1
ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
14.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Device configuration and ordering information . . . . . . . . . . . . . . . . . 232
15.1
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
15.1.1
Option byte 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
15.1.2
Option byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
15.1.3
Option byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
15.1.4
Option byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Doc ID 12321 Rev 6
7/247
Contents
16
ST72344xx, ST2345xx
15.2
Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
15.3
Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
15.3.2
Development and debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3.3
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
15.3.4
Order codes for ST72F34x development tools . . . . . . . . . . . . . . . . . . 238
External interrupt missed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.1.1
Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.1.2
Unexpected reset fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
16.2
Clearing active interrupts outside interrupt routine . . . . . . . . . . . . . . . . . 241
16.3
16-bit timer PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.4
TIMD set simultaneously with OC interrupt . . . . . . . . . . . . . . . . . . . . . . 242
16.5
16.6
16.7
8/247
Starter kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
16.1
17
15.3.1
16.4.1
Impact on the application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.4.2
Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
SCI wrong break duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.5.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
16.5.2
Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.5.3
Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Random read operations not supported with the standard I²C . . . . . . . 243
16.6.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.6.2
Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.6.3
Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Programming of EEPROM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.7.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.7.2
Impact on application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.7.3
Workaround . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
ST72344xx and ST72345xx features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data EEPROM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PLL configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
ST7 clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
LVDRF and WDGRF description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
External interrupt sensitivity (ei2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
External interrupt sensitivity (ei3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
External interrupt sensitivity (ei0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
External interrupt sensitivity (ei1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Nested interrupts register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Power saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
AWUPR dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
AWU register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I/O Port mode options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
I/O port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Description of interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
I/O port register configurations (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O port register configurations (interrupt ports with pull-up). . . . . . . . . . . . . . . . . . . . . . . . 79
I/O port register configurations (interrupt ports without pull-up) . . . . . . . . . . . . . . . . . . . . . 79
I/O port register configurations (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I/O port register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Watchdog timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Interrupt event. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CPU clock prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Time base control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Beep control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Main clock controller register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
ICiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
OCiR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Low-power mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Doc ID 12321 Rev 6
9/247
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
10/247
ST72344xx, ST2345xx
Timer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Clock control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
16-bit timer register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI master mode SCK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
SCP[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SCT[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SCR[2:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
SCI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
FR[1:0] configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
PL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
I2C3S register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Addressing mode groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
ST7 addressing mode overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Inherent instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Immediate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Instructions supporting direct, indexed, indirect and indirect indexed addressing modes 194
Short instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Relative direct/indirect instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Main instruction groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Illegal opcode detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
LVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
AVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Internal RC oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Internal RC oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
General timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
External clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Auto-wakeup from Halt oscillator (AWU) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 210
Crystal/ceramic resonator oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Recommended load capacitance vs. equivalent serial resistance of ceramic
resonator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Table 100.
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
List of tables
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
EEPROM data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
EMS test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
EMI emissions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
General characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Output driving current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Asynchronous RESET pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
I2C and I²C3SNS interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
SCL frequency table (multimaster I2C interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
32-pin low profile quad flat package (7 x 7 mm) mechanical data . . . . . . . . . . . . . . . . . . 228
40-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . 229
44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
LVD threshold configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Size of sector 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
Selection of the resonator oscillator range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
List of valid option combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Package selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Option byte default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Development tool order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Doc ID 12321 Rev 6
11/247
List of figures
ST72344xx, ST2345xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
12/247
General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
LQFP44 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
LQFP48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Typical ICC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
EEPROM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Data EEPROM programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Data EEPROM write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Data EEPROM programming cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Clock, reset and supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PLL output frequency timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
reset sequence phases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Reset sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Low voltage detector vs. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Using the AVD to monitor VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Interrupt processing flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Priority decision process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Concurrent interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Nested interrupt management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
External interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Power saving mode transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Slow mode clock transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Wait mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Active-halt timing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Active-halt mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
AWUFH mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
AWUF Halt timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
AWUFH mode flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
I/O port general block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Interrupt I/O port state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Approximate timeout duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Exact timeout duration (tmin and tmax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Main clock controller (MCC/RTC) block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
16-bit read sequence (from either the counter register or the alternate
counter register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Counter timing diagram, internal clock divided by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Input capture block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
List of figures
Input capture timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Output compare block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Output compare timing diagram, fTIMER = fCPU/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Output compare timing diagram, fTIMER = fCPU/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
One-pulse mode cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
One-pulse mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Pulse width modulation mode timing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Pulse width modulation cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Serial peripheral interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Generic SS timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Clearing the WCOL bit (write collision flag) software sequence . . . . . . . . . . . . . . . . . . . . 123
Single master / multiple slave configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
SCI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SCI baud rate and extended prescaler block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Bit sampling in reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
I2C interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
I2C3S interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
16-bit word write operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
16-bit word read operation flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Transfer sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Random read (dummy write + restart + current address read). . . . . . . . . . . . . . . . . . . . . 175
Random read (dummy write + stop + start + current address read) . . . . . . . . . . . . . . . . . 176
Sequential read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Combined format for read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
fCPU maximum operating frequency versus VDD supply voltage . . . . . . . . . . . . . . . . . . . 202
Typical RC frequency vs. RCCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Typical IDD in Run vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Typical IDD in Run at fCPU = 8 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Typical IDD in Slow vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Typical IDD in Wait vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Typical IDD in Wait at fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Typical IDD in Slow-wait vs. fCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Typical IDD vs. temp. at VDD = 5 V and fCPU = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Typical application with an external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Typical application with a crystal or ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Two typical applications with unused I/O pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Typical VOL at VDD = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Doc ID 12321 Rev 6
13/247
List of figures
Figure 100.
Figure 101.
Figure 102.
Figure 103.
Figure 104.
Figure 105.
Figure 106.
Figure 107.
Figure 108.
Figure 109.
Figure 110.
Figure 111.
Figure 112.
Figure 113.
Figure 114.
Figure 115.
Figure 116.
Figure 117.
Figure 118.
Figure 119.
Figure 120.
Figure 121.
Figure 122.
Figure 123.
14/247
ST72344xx, ST2345xx
Typical VOL at VDD = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Typical VOL at VDD = 5 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Typical VOL at VDD = 2.4 V (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Typical VOL at VDD = 3 V (high-sink I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Typical VOL at VDD = 5 V (high-sink I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Typical VOL vs. VDD (std I/Os, 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Typical VOL vs. VDD (std I/Os, 6 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Typical VOL vs. VDD (HS I/Os, IIO = 8 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Typical VOL vs. VDD (HS I/Os, IIO = 2 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Typical VOL vs. VDD (HS I/Os, IIO = 12 mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Typical VDD – vOH at VDD = 2.4 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Typical VDD – VOH at VDD = 3 V (std I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Typical VDD – VOH at VDD = 4 V (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Typical VDD – VOH at VDD = 5 V (std) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Typical VDD – VOH vs. VDD (high sink) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
RESET pin protection when LVD is enabled(1)(2)(3)(4). . . . . . . . . . . . . . . . . . . . . . . . . . 223
RESET pin protection when LVD is disabled (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Typical A/D converter application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
32-pin low profile quad flat package (7 x 7 mm) outline . . . . . . . . . . . . . . . . . . . . . . . . . . 227
40-lead very thin fine pitch quad flat no-lead package outline . . . . . . . . . . . . . . . . . . . . . 228
44-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
48-pin low profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
ST7234x ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
1
Description
Description
The ST7234x devices are members of the ST7 microcontroller family. Table 2 gives the
available part numbers and details on the devices. All devices are based on a common
industry-standard 8-bit core, featuring an enhanced instruction set.
They feature single-voltage Flash memory with byte-by-byte in-circuit programming (ICP)
and in-application programming (IAP) capabilities.
Under software control, all devices can be placed in Wait, Slow, Auto-wakeup from Halt,
Active-halt or Halt mode, reducing the power consumption when the application is in idle or
stand-by state.
The enhanced instruction set and addressing modes of the ST7 offer both power and
flexibility to software developers, enabling the design of highly efficient and compact
application code. In addition to standard 8-bit data management, all ST7 microcontrollers
feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes.
The devices feature an on-chip debug module (DM) to support in-circuit debugging (ICD).
For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual.
Figure 1.
General block diagram
8-BIT CORE
ALU
RESET
VSS
VDD
OSC1
OSC2
PROGRAM
MEMORY
(16 K - 32 KBytes)
CONTROL
RAM
(512- 1024 Bytes)
LVD
AVD
WATCHDOG
CLOCK CONTROL
I2CMMS
MCC/RTC/BEEP
PORT F
PF
(6-bits)
TIMER A
ADDRESS AND DATA BUS
INTERNAL RC
PA
(5-bits)
PORT A
PORT B
PB
(5-bits)
PWM ART
PORT C
BEEP
TIMER B
PC
(8-bits)
I2C3SNS
SPI
PD
(6-bits)
PORT D
10-BIT ADC
VAREF
VSSA
PORT E
PE
(2-bits)
SCI
Doc ID 12321 Rev 6
15/247
Description
ST72344xx, ST2345xx
Table 2.
ST72344xx and ST72345xx features
Features
Program memory - bytes
ST72344K2, ST72344K4, ST72344S2,
ST72344S4
8,000
16,000
16,000
512 bytes (256 bytes)
1 Kbyte (256 bytes)
1 Kbyte (256 bytes)
EEPROM data - bytes
256
256
256
Common peripherals
Window watchdog, 2 16-bit timers, SCI, SPI, I2CMMS
RAM (stack) - bytes
Other peripherals
CPU frequency
10-bit ADC
Package
I2C3SNS, 10-bit ADC
8 MHz @ 3.3 V to 5.5 V, 4 MHz @ 2.7 V to 5.5 V
Temperature range
16/247
ST72345C4
-40 °C to +85 °C
LQFP32 7x7, LQFP44 10x10
Doc ID 12321 Rev 6
LQFP48 7x7
ST72344xx, ST2345xx
Pin description
LQFP32 package pinout
PD1 / AIN1
PD0 / AIN0
PB4 (HS)
PB3
PB0
PE1 / RDI
PE0 / TDO
VDD_2
Figure 2.
32 31 30 29 28 27 26 25
VDDA
VSSA
AIN8 / PF0
(HS) PF1
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
AIN12 / OCMP2_B / PC0
1
ei3
ei2
ei0
24
2
23
3
22
4 ei1
21
5
20
6
19
ei0 18
17
8
9 10 11 12 13 14 15 16
7
OSC1
OSC2
VSS_2
RESET
ICCSEL
PA7 (HS) / SCL
PA6 (HS) / SDA
PA4 (HS)
AIN13 / OCMP1_B / PC1
ICAP2_B / (HS) PC2
ICAP1_B / (HS) PC3
ICCDATA / MISO / PC4
AIN14 / MOSI / PC5
ICCCLK / SCK / PC6
AIN15 / SS / PC7
(HS) PA3
2
Pin description
(HS) 20mA high sink capability
eix associated external interrupt vector
Doc ID 12321 Rev 6
17/247
Pin description
LQFP44 package pinout
PE0 / TDO
VDD_2
OSC1
OSC2
VSS_2
RESET
ICCSEL
PA7 (HS) / SCL
PA6 (HS) / SDA
PA5 (HS)
PA4 (HS)
Figure 3.
ST72344xx, ST2345xx
44 43 42 41 40 39 38 37 36 35 34
ei0
1
33
2
32
3
31
ei0
ei2
4
30
5
29
ei3
6
28
7
27
8
26
9
25
10
24
ei1
11
23
12 13 14 15 16 17 18 19 20 21 22
AIN5 / PD5
VDDA
VSSA
MCO / AIN8 / PF0
BEEP / (HS)
(HS) PF2
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
VDD_0
VSS_0
RDI / PE1
PB0
PB1
PB2
PB3
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
18/247
Doc ID 12321 Rev 6
VSS_1
VDD_1
PA3 (HS)
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
PC0 / OCMP2_B / AIN12
ST72344xx, ST2345xx
LQFP48 package pinout
VDD_2
OSC1
OSC2
VSS_2
RESET
ICCSEL
PA7 (HS)/SCL
PA6 (HS)/SDA
PA5 (HS)
PA4 (HS)
PD6/SDA3SNS
PD7/SCL3SNS
Figure 4.
Pin description
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2 ei0
35
ei0
34
3
33
4
ei2
32
5
31
6
30
7 ei3
29
8
28
9
27
10
26
11
ei1
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VSS_1
VDD_1
PA3 (HS)
PC7 / SS / AIN15
PC6 / SCK / ICCCLK
PC5 / MOSI / AIN14
PC4 / MISO / ICCDATA
PC3 (HS) / ICAP1_B
PC2 (HS) / ICAP2_B
PC1 / OCMP1_B / AIN13
NC
NC
AIN5 / PD5
VDDA
VSSA
MCO / AIN8 / PF0
BEEP / (HS) PF1
(HS) PF2
OCMP1_A / AIN10 / PF4
ICAP1_A / (HS) PF6
EXTCLK_A / (HS) PF7
VDD_0
VSS_0
PC0 / OCMP2_B / AIN12
PE0/TD0
RDI / PE1
PB0
PB1
PB2
PB3
(HS) PB4
AIN0 / PD0
AIN1 / PD1
AIN2 / PD2
AIN3 / PD3
AIN4 / PD4
Note:
For external pin connection guidelines, refer to Section 13: Electrical characteristics.
Doc ID 12321 Rev 6
19/247
Pin description
ST72344xx, ST2345xx
Legend / Abbreviations for Table 3:
Type:
I = input, O = output, S = supply
Input level:
A = Dedicated analog input
In/Output level: CT= CMOS 0.3VDD/0.7VDD with input trigger
Output level:
HS = 20 mA high sink (on N-buffer only)
Port and control configuration:
●
Input:
float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog
●
Output:
OD = open drain 2), PP = push-pull
The reset configuration of each pin is shown in bold. This configuration is valid as long as
the device is in reset state.
On the chip, each I/O port may have up to 8 pads. Pads that are not bonded to external pins
are set in input pull-up configuration after reset through the option byte Package selection.
The configuration of these pads must be kept at reset state to avoid added current
consumption.
Device pin description
Main
function
Output
(after
reset)
Alternate function
PP
int
wpu
Input (1)
OD
Port
float
Output
Input
Pin name
Type
Level
LQFP48
LQFP44
LQFP32
Pin n°
ana
Table 3.
1 13 14 VDDA (2)
S
Analog supply voltage
(2)
S
Analog ground voltage
2 14 15 VSSA
X
X Port F0
Main clock ADC
analog
out
input 8
(fOSC/2)
X
X Port F1
Beep signal output
X
X Port F2
X
X Port F4
Timer A
ADC
output
analog
compare 1 input 10
X
X
X Port F6
Timer A Input
Capture 1
X
X
X Port F7
Timer A external
clock source
3 15 16 PF0/MCO/AIN8
I/O CT
X
ei1
4 16 17 PF1 (HS)/BEEP
I/O CT HS
X
ei1
I/O CT HS
X
5 18 19 PF4/OCMP1_A/AIN10
I/O CT
X
X
6 19 20 PF6 (HS)/ICAP1_A
I/O CT HS
X
7 20 21 PF7 (HS)/EXTCLK_A
I/O CT HS
X
-
17 18 PF2 (HS)
(3)
X
ei1
X
-
21 22 VDD_0 (2)
S
Digital main supply voltage
-
22 23 VSS_0 (2)
S
Digital ground voltage
8 23 24 PC0/OCMP2_B/AIN12
I/O CT
X
X
X
X
X Port C0
Timer B
ADC
output
analog
compare 2 input 12
9 24 27 PC1/OCMP1_B/AIN13
I/O CT
X
X
X
X
X Port C1
Timer B
ADC
output
analog
compare 1 input 13
20/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Table 3.
Pin description
Device pin description (continued)
Port
I/O CT HS
X
X
X
X Port C2
Timer B input capture
2
11 26 29 PC3 (HS)/ICAP1_B
I/O CT HS
X
X
X
X Port C3
Timer B input capture
1
12 27 30 PC4/MISO/ICCDATA
I/O CT
X
X
X
X Port C4
SPI Master
ICC data
In / Slave
input
Out data
13 28 31 PC5/MOSI/AIN14
I/O CT
X
X
X
X Port C5
SPI Master ADC
Out / Slave analog
In data
input 14
14 29 32 PC6/SCK/ICCCLK
I/O CT
X
X
X
X Port C6
SPI serial
clock
ICC
clock
output
X
X Port C7
SPI slave
select
(active
low)
ADC
analog
input 15
X
X Port A3
15 30 33 PC7/SS/AIN15
I/O CT
X
16 31 34 PA3 (HS)
I/O CT HS
X
-
ana
10 25 28 PC2 (HS)/ICAP2_B
int
PP
Alternate function
OD
Main
function
Output
(after
reset)
wpu
Input
(1)
float
Output
Input
Pin name
Type
Level
LQFP48
LQFP44
LQFP32
Pin n°
X
X
X
ei0
32 35 VDD_1
(2)
S
Digital main supply voltage
33 36 VSS_1
(2)
S
Digital ground voltage
T
-
-
37 PD7 (3)/ SCL3SNS
I/O CT HS
X
(4)
Port D7
I2C3SNS serial clock
-
-
38 PD6 (3)/ SDA3SNS
I/O CT HS
X
T
Port D6
I2C3SNS serial data
I/O CT HS
X
X
X
X Port A4
I/O CT HS
X
X
X
X Port A5
18 36 41 PA6 (HS)/SDA
I/O CT HS
X
T
Port A6
I2C serial data
19 37 42 PA7 (HS)/SCL
I/O CT HS
X
T
Port A7
I2C serial clock
17 34 39 PA4 (HS)
-
35 40 PA5 (HS)
(3)
20 38 43 ICCSEL (5)
21 39 44 RESET
I
ICC mode selection
Top priority non maskable
interrupt.
I/O CT
22 40 45 VSS_2 (2)
S
Digital ground voltage
23 41 46 OSC2
O
Resonator oscillator inverter
output
24 42 47 OSC1
I
External clock input or resonator
oscillator inverter input
25 43 48 VDD_2 (2)
S
Digital main supply voltage
26 44
1
PE0/TDO
I/O CT
X
X
Doc ID 12321 Rev 6
X
X Port E0
SCI transmit data out
21/247
Pin description
Device pin description (continued)
2
PE1/RDI
I/O CT
X
28
2
3
PB0
int
wpu
float
Input
(1)
ei0
Main
function
Output
(after
reset)
PP
LQFP48
1
Output
LQFP44
27
Pin name
Input
LQFP32
Port
OD
Level
Type
Pin n°
ana
Table 3.
ST72344xx, ST2345xx
X
X Port E1
I/O CT
X
ei2
X
X Port B0
(3)
I/O CT
X
ei2
X
X Port B1
ei2
X
X Port B2
X
X Port B3
X
X Port B4
Alternate function
SCI receive data in
-
3
4
PB1
-
4
5
PB2 (3)
I/O CT
X
29
5
6
PB3
I/O CT
X
30
6
7
PB4 (HS)
I/O CT HS
X
31
7
8
PD0/AIN0
I/O CT
X
X
X
X
X Port D0
ADC analog input 0
32
8
9
PD1/AIN1
I/O CT
X
X
X
X
X Port D1
ADC analog input 1
-
9
10 PD2/AIN2
I/O CT
X
X
X
X
X Port D2
ADC analog input 2
-
10 11 PD3/AIN3
I/O CT
X
X
X
X
X Port D3
ADC analog input 3
-
11 12 PD4/AIN4
I/O CT
X
X
X
X
X Port D4
ADC analog input 4
-
12 13 PD5/AIN5
I/O CT
X
X
X
X
X Port D5
ADC analog input 5
ei2
ei3
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is
merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating
interrupt input.
2. It is mandatory to connect all available VDD and VDDA pins to the supply voltage and all VSS and VSSA pins to ground.
3. Pulled-up by hardware when not present on the package.
4. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not
implemented).
5. Internal weak pull-down.
22/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
3
Register and memory map
Register and memory map
As shown in Figure 5, the MCU is capable of addressing 64 Kbytes of memories and I/O
registers.
The available memory locations consist of 128 bytes of register locations, up to 1 Kbyte of
RAM, 256 bytes of Data EEPROM and up to 16 Kbytes of user program memory. The RAM
space includes up to 256 bytes for the stack from 0100h to 01FFh.
The highest address bytes contain the user reset and interrupt vectors.
Figure 5.
0000h
007Fh
0080h
047Fh
0480h
Memory map
HW registers
RAM
(512 or 1K Bytes)
Reserved
0BFFh
0C00h
0CFFh
0D00h
0080h
Short addressing
RAM (zero page)
See Table 4
Data EEPROM
(256 Bytes)
Reserved
00FFh
0100h
256 Bytes stack
01FFh
0200h
16-bit addressing
RAM
047Fh
SECTOR 2
16 Kbytes
Program memory
(8 or 16 KBytes)
FFDFh
FFE0h
FFFFh
C000h
C000h
BFFFh
C000h
E000h
E000h
8 Kbytes
Interrupt & Reset Vectors
See Table 17
F000h (4k)
or FB00h (2k)
or FC00h (1k)
or FE00h (0.5k)
SECTOR 1
SECTOR 0
FFFFh
Doc ID 12321 Rev 6
FFFFh
23/247
Register and memory map
Table 4.
Address
ST72344xx, ST2345xx
Hardware register map
Block
Register
label
Register name
Reset status
Remarks
(1)
(2)
PADR
Port A (3) PADDR
PAOR
Port A Data Register
Port A Data Direction Register
Port A Option Register
00h (4)
00h
00h
R/W
R/W
R/W
Port B
(3)
PBDR
PBDDR
PBOR
Port B Data Register
Port B Data Direction Register
Port B Option Register
00h (4)
00h
00h
R/W
R/W
R/W
Port C
(3)
PCDR
PCDDR
PCOR
Port C Data Register
Port C Data Direction Register
Port C Option Register
00h (4)
00h
00h
R/W
R/W
R/W
0009h
000Ah
000Bh
Port D
(3)
PDADR
PDDDR
PDOR
Port D Data Register
Port D Data Direction Register
Port D Option Register
00h (4)
00h
00h
R/W
R/W
R/W
000Ch
000Dh
000Eh
PEDR
Port E (3) PEDDR
PEOR
Port E Data Register
Port E Data Direction Register
Port E Option Register
00h (4)
00h
00h
R/W
R/W
R/W
PFDR
PFDDR
PFOR
Port F Data Register
Port F Data Direction Register
Port F Option Register
00h (4)
00h
00h
R/W
R/W
R/W
FFh
03h
R/W
R/W
Data EEPROM Control/Status Register
00h
R/W
SPIDR
SPICR
SPICSR
SPI Data I/O Register
SPI Control Register
SPI Control Status Register
xxh
0xh
00h
R/W
R/W
R/W
ISPR0
ISPR1
ISPR2
ISPR3
Interrupt Software Priority Register 0
Interrupt Software Priority Register 1
Interrupt Software Priority Register 2
Interrupt Software Priority Register 3
FFh
FFh
FFh
FFh
R/W
R/W
R/W
R/W
EICR
External Interrupt Control Register
00h
R/W
FCSR
Flash Control/Status Register
00h
R/W
WDGCR
Watchdog Control Register
7Fh
R/W
SICSR
System Integrity Control/Status Register
000x 000xb
R/W
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
000Fh
0010h
0011h
Port F
(3)
0012h to
0016h
0017h
0018h
Reserved area (5 bytes)
RC
RCCRH
RCCRL
0019h
001Ah to
001Fh
00020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
RC oscillator Control Register High
RC oscillator Control Register Low
Reserved area (1 byte)
DM (5)
Reserved area (6 bytes)
EEPROM EECSR
SPI
ITC
0028h
00029h
Flash
002Ah
WWDG
002Bh
SI
002Ch
002Dh
MCC
MCCSR
MCCBCR
Main Clock Control/Status Register
MCC Beep Control Register
00h
00h
R/W
R/W
002Eh
002Fh
AWU
AWUCSR
AWUPR
AWU Control/Status Register
AWU Prescaler Register
00h
FFh
R/W
R/W
0030h
WWDG
WDGWR
Window Watchdog Control Register
7Fh
R/W
24/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Table 4.
Address
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Register and memory map
Hardware register map (continued)
Block
Register
label
TACR2
TACR1
TACSR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TIMER A TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h
0058h
0059h
005Ah
005Bh
005Ch
005Dh
005Eh
005Fh
Timer A Control Register 2
Timer A Control Register 1
Timer A Control/Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register
Reset status
Remarks
(1)
(2)
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
Timer B Control Register 2
Timer B Control Register 1
Timer B Control/Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register
00h
00h
xxh
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
C0h
xxh
00h
x000 0000b
00h
-00h
00h
Read Only
R/W
R/W
R/W
R/W
SCIERPR
SCIETPR
SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
Reserved area
SCI Extended Receive Prescaler Register
SCI Extended Transmit Prescaler Register
I2CCR
I2CSR1
I2CSR2
I2CCCR
I2COAR1
I2COAR2
I2CDR
I2C Control Register
I2C Status Register 1
I2C Status Register 2
I2C Clock Control Register
I2C Own Address Register 1
I2C Own Address Register2
I2C Data Register
00h
00h
00h
00h
00h
40h
00h
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h
004Ah
004Bh
004Ch
004Dh
004Eh
004Fh
Register name
Reserved area (1 Byte)
TBCR2
TBCR1
TBCSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TIMER B TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR
SCI
I2C
SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
R/W
R/W
Reserved area (1 byte)
Doc ID 12321 Rev 6
25/247
Register and memory map
Table 4.
Address
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
ST72344xx, ST2345xx
Hardware register map (continued)
Block
Register
label
I2C3SCR1
I2C3SCR2
I2C3SSR
I2C3SBCR
I2C3SSAR1
I2C3SNS
I2C3SCAR1
I2C3SSAR2
I2C3SCAR2
I2C3SSAR3
I2C3SCAR3
0070h
0071h
0072h
ADC
0073h to
007Fh
ADCCSR
ADCDRH
ADCDRL
Register name
I2C3SNS Control Register 1
I2C3SNS Control Register 2
I2C3SNS Status Register
I2C3SNS Byte Count Register
I2C3SNS Slave Address 1 Register
I2C3SNS Current Address 1 Register
I2C3SNS Slave Address 2 Register
I2C3SNS Current Address 2 Register
I2C3SNS Slave Address 3 Register
I2C3SNS Current Address 3 Register
A/D Control Status Register
A/D Data Register High
A/D Data Low Register
Reset status
Remarks
(1)
(2)
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
R/W
R/W
Read Only
Read Only
R/W
R/W
R/W
R/W
R/W
R/W
00h
xxh
0000 00xxb
R/W
Read Only
Read Only
Reserved area (13 bytes)
1. x = undefined.
2. R/W = read/write.
3. The bits associated with unavailable pins must always keep their reset value.
4. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the
I/O pins are returned instead of the DR register contents.
5. For a description of the Debug Module registers, see ST7 ICC protocol reference manual.
26/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Flash program memory
4
Flash program memory
4.1
Introduction
The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be
electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in
parallel.
The XFlash devices can be programmed off-board (plugged in a programming tool) or onboard using In-Circuit Programming or In-Application Programming.
The array matrix organization allows each sector to be erased and reprogrammed without
affecting other sectors.
4.2
4.3
Main features
●
ICP (in-circuit programming)
●
IAP (in-application programming)
●
ICT (in-circuit testing) for downloading and executing user application test patterns in
RAM
●
Sector 0 size configurable by option byte
●
Read-out and write protection
Programming modes
The ST7 can be programmed in three different ways:
●
Insertion in a programming tool
In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can
be programmed or erased.
●
In-circuit programming
In this mode, Flash sectors 0 and 1, option byte row and data EEPROM (if present) can
be programmed or erased without removing the device from the application board.
●
In-application programming
In this mode, sector 1 and data EEPROM (if present) can be programmed or erased
without removing the device from the application board and while the application is
running.
Doc ID 12321 Rev 6
27/247
Flash program memory
4.3.1
ST72344xx, ST2345xx
In-circuit programming (ICP)
ICP uses a protocol called ICC (in-circuit communication) which allows an ST7 plugged on a
printed circuit board (PCB) to communicate with an external programming device connected
via cable. ICP is performed in three steps:
Switch the ST7 to ICC mode (in-circuit communications). This is done by driving a specific
signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the
ST7 enters ICC mode, it fetches a specific reset vector which points to the ST7 System
Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes
from the ICC interface.
●
Download ICP Driver code in RAM from the ICCDATA pin
●
Execute ICP Driver code in RAM to program the Flash memory
Depending on the ICP Driver code downloaded in RAM, Flash memory programming can
be fully customized (number of bytes to program, program locations, or selection of the
serial communication interface for downloading).
4.3.2
In-application programming (IAP)
This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in
ICP mode).
This mode is fully controlled by user software. This allows it to be adapted to the user
application (user-defined strategy for entering programming mode, choice of
communications protocol used to fetch the data to be stored etc.)
IAP mode can be used to program any memory areas except Sector 0, which is write/erase
protected to allow recovery in case errors occur during the programming operation.
4.4
ICC interface
ICP needs a minimum of 4 and up to 7 pins to be connected to the programming tool. These
pins are:
Note:
28/247
●
RESET: device reset
●
VSS: device power supply ground
●
ICCCLK: ICC output serial clock pin
●
ICCDATA: ICC input serial data pin
●
ICCSEL: ICC selection
●
OSC1: main clock input for external source (not required on devices without
OSC1/OSC2 pins)
●
VDD: application board power supply (optional, see Note 3)
1
If the ICCCLK or ICCDATA pins are only used as outputs in the application, no signal
isolation is necessary. As soon as the Programming Tool is plugged to the board, even if an
ICC session is not in progress, the ICCCLK and ICCDATA pins are not available for the
application. If they are used as inputs by the application, isolation such as a serial resistor
has to be implemented in case another device forces the signal. Refer to the Programming
Tool documentation for recommended resistor values.
2
During the ICP session, the programming tool must control the RESET pin. This can lead to
conflicts between the programming tool and the application reset circuit if it drives more than
5 mA at high level (push pull output or pull-up resistor1,000 or a reset management IC with open drain output and pull-up resistor>1,000, no
additional components are needed. In all cases the user must ensure that no external reset
is generated by the application during the ICC session.
3
The use of Pin 7 of the ICC connector depends on the Programming Tool architecture. This
pin must be connected when using most ST Programming Tools (it is used to monitor the
application power supply). Please refer to the Programming Tool manual.
4
Pin 9 has to be connected to the OSC1 pin of the ST7 when the clock is not available in the
application or if the selected clock option is not programmed in the option byte. ST7 devices
with multi-oscillator capability need to have OSC2 grounded in this case.
5
In “enabled option byte” mode (38-pulse ICC mode), the internal RC oscillator is forced as a
clock source, regardless of the selection in the option byte.
Caution:
During normal operation, the ICCCLK pin must be internally or externally pulled- up
(external pull-up of 10 kΩ mandatory in noisy environment) to avoid entering ICC mode
unexpectedly during a reset. In the application, even if the pin is configured as an output,
any reset will put it back in input pull-up.
Figure 6.
Typical ICC interface
PROGRAMMING TOOL
ICC CONNECTOR
ICC Cable
ICC CONNECTOR
HE10 CONNECTOR TYPE
(See Note 3)
OPTIONAL
(See Note 4)
9
7
5
3
1
10
8
6
4
2
APPLICATION BOARD
APPLICATION
RESET SOURCE
See Note 2
10kΩ
4.5
ICCCLK
APPLICATION
I/O
ICCDATA
ST7
RESET
See Note 1
ICCSEL
OSC1
CL1
OSC2
VDD
CL2
VSS
APPLICATION
POWER SUPPLY
Memory protection
There are two different types of memory protection: Read Out Protection and Write/Erase
Protection which can be applied individually.
4.5.1
Readout protection
Readout protection, when selected, provides a protection against program memory content
extraction and against write access to Flash memory. Even if no protection can be
considered as totally unbreakable, the feature provides a very high level of protection for a
general purpose microcontroller. Both program and data E2 memory are protected.
Doc ID 12321 Rev 6
29/247
Flash program memory
ST72344xx, ST2345xx
In Flash devices, this protection is removed by reprogramming the option. In this case, both
program and data E2 memory are automatically erased, and the device can be
reprogrammed.
Read-out protection selection depends on the device type:
4.5.2
●
In Flash devices, it is enabled and removed through the FMP_R bit in the option byte.
●
In ROM devices, it is enabled by mask option specified in the Option List.
Flash write/erase protection
Write/erase protection, when set, makes it impossible to both overwrite and erase program
memory. It does not apply to E2 data. Its purpose is to provide advanced security to
applications and prevent any change being made to the memory content.
Warning:
Once set, Write/erase protection can never be removed. A
write-protected Flash device is no longer reprogrammable.
Write/erase protection is enabled through the FMP_W bit in the option byte.
4.6
Register description
4.6.1
Flash control/status register (FCSR)
Reset value: 0000 0000 (00h)
1st RASS Key: 0101 0110 (56h)
2nd RASS Key: 1010 1110 (AEh)
7
0
0
0
0
0
0
OPT
LAT
PGM
Read/Write
Note:
This register is reserved for programming using ICP, IAP or other programming methods. It
controls the XFlash programming and erasing operations. For details on XFlash
programming, refer to the ST7 Flash Programming Reference Manual.
When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys
are sent automatically.
30/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Data EEPROM
5
Data EEPROM
5.1
Introduction
The electrically erasable programmable read only memory can be used as a non-volatile
backup for storing data. Using the EEPROM requires a basic access protocol described in
this chapter.
5.2
Main features
●
Up to 32 bytes programmed in the same cycle
●
EEPROM mono-voltage (charge pump)
●
Chained erase and programming cycles
●
Internal control of the global programming cycle duration
●
Wait mode management
●
Readout protection
Figure 7.
EEPROM block diagram
HIGH VOLTAGE
PUMP
EECSR
0
0
0
ADDRESS
DECODER
0
0
4
0
E2LAT E2PGM
EEPROM
ROW
MEMORY MATRIX
DECODER
(1 ROW = 32 x 8 BITS)
128
4
128
DATA
32 x 8 BITS
MULTIPLEXER
DATA LATCHES
4
ADDRESS BUS
5.3
DATA BUS
Memory access
The Data EEPROM memory read/write access modes are controlled by the E2LAT bit of the
EEPROM Control/Status register (EECSR). The flowchart in Figure 8 describes these
different memory access modes.
Doc ID 12321 Rev 6
31/247
Data EEPROM
ST72344xx, ST2345xx
Read operation (E2LAT = 0)
The EEPROM can be read as a normal ROM location when the E2LAT bit of the EECSR
register is cleared.
On this device, Data EEPROM can also be used to execute machine code. Take care not to
write to the Data EEPROM while executing from it. This would result in an unexpected code
being executed.
Write operation (E2LAT = 1)
To access the write mode, the E2LAT bit has to be set by software (the E2PGM bit remains
cleared). When a write access to the EEPROM area occurs, the value is latched inside the
32 data latches according to its address.
When E2PGM bit is set by the software, all the previous bytes written in the data latches (up
to 32) are programmed in the EEPROM cells. The effective high address (row) is
determined by the last EEPROM write sequence. To avoid wrong programming, the user
must take care that all the bytes written between two programming sequences have the
same high address: only the five Least Significant Bits of the address can change.
The programming cycle is fully completed when the E2PGM bit is cleared.
Note:
Care should be taken during the programming cycle. Writing to the same memory location
will over-program the memory (logical AND between the two write access data results)
because the data latches are only cleared at the end of the programming cycle and by the
falling edge of the E2LAT bit.
It is not possible to read the latched data.
This note is illustrated by the Figure 10.
Figure 8.
Data EEPROM programming flowchart
READ MODE
E2LAT = 0
E2PGM = 0
READ BYTES
IN EEPROM AREA
WRITE MODE
E2LAT = 1
E2PGM = 0
WRITE UP TO 32 BYTES
IN EEPROM AREA
(with the same 11 MSB of the address)
START PROGRAMMING CYCLE
E2LAT=1
E2PGM=1 (set by software)
0
CLEARED BY HARDWARE
32/247
Doc ID 12321 Rev 6
E2PGM
1
ST72344xx, ST2345xx
Figure 9.
Data EEPROM
Data EEPROM write operation
⇓ Row / Byte ⇒ 0
Row
definition
1
2
3
...
30 31
Physical address
0
00h...1Fh
1
20h...3Fh
...
N
Nx20h...Nx20h+1Fh
Read operation impossible
Byte 1 Byte 2
Byte 32
PHASE 1
Writing data latches
Read operation possible
Programming cycle
PHASE 2
Waiting E2PGM and E2LAT to fall
E2LAT bit
Set by USER application
Cleared by hardware
E2PGM bit
Note:
If a programming cycle is interrupted (by reset action), the integrity of the data in memory
will not be guaranteed.
5.4
Power saving modes
5.4.1
Wait mode
The data EEPROM can enter Wait mode on execution of the WFI instruction of the
microcontroller or when the microcontroller enters Active Halt mode.The data EEPROM will
immediately enter this mode if there is no programming in progress, otherwise the data
EEPROM will finish the cycle and then enter Wait mode.
5.4.2
Active-halt mode
Refer to Wait mode.
5.4.3
Halt mode
The data EEPROM immediately enters Halt mode if the microcontroller executes the Halt
instruction. Therefore the EEPROM will stop the function in progress, and data may be
corrupted.
5.5
Access error handling
If a read access occurs while E2LAT = 1, then the data bus will not be driven.
If a write access occurs while E2LAT = 0, then the data on the bus will not be latched.
If a programming cycle is interrupted (by reset action), the integrity of the data in memory
will not be guaranteed.
Doc ID 12321 Rev 6
33/247
Data EEPROM
5.6
ST72344xx, ST2345xx
Data EEPROM readout protection
The readout protection is enabled through an option bit (see Section 15.1: Option bytes).
When this option is selected, the programs and data stored in the EEPROM memory are
protected against read-out (including a rewrite protection). In Flash devices, when this
protection is removed by reprogramming the option byte, the entire Program memory and
EEPROM is first automatically erased.
Note:
Both program memory and data EEPROM are protected using the same option bit.
Figure 10. Data EEPROM programming cycle
READ OPERATION NOT POSSIBLE
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
ERASE CYCLE
WRITE OF
DATA
LATCHES
WRITE CYCLE
tPROG
E2LAT
E2PGM
All interrupts must be masked 1)
Note 1: refer to Programming of EEPROM data
34/247
Doc ID 12321 Rev 6
I bit in CC register
ST72344xx, ST2345xx
Data EEPROM
5.7
Register description
5.7.1
EEPROM control/status register (EECSR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
E2LAT
E2PGM
Read/Write
Bits 7:2 = Reserved, forced by hardware to 0.
Bit 1 = E2LAT Latch Access Transfer
This bit is set by software. It is cleared by hardware at the end of the programming
cycle. It can only be cleared by software if the E2PGM bit is cleared.
0: Read mode
1: Write mode
Bit 0 = E2PGM Programming control and status
This bit is set by software to begin the programming cycle. At the end of the
programming cycle, this bit is cleared by hardware.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note:
If the E2PGM bit is cleared during the programming cycle, the memory data is not
guaranteed.
Table 5.
Data EEPROM register map and reset values
Address
(Hex.)
Register
label
0020h
EECSR
Reset value
7
6
5
4
3
2
0
0
0
0
0
0
Doc ID 12321 Rev 6
1
0
E2LAT E2PGM
0
0
35/247
Central processing unit
ST72344xx, ST2345xx
6
Central processing unit
6.1
Introduction
This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8bit data manipulation.
6.2
6.3
Main features
●
Enable executing 63 basic instructions
●
Fast 8-bit by 8-bit multiply
●
17 main addressing modes (with indirect addressing mode)
●
Two 8-bit index registers
●
16-bit stack pointer
●
Low power Halt and Wait modes
●
Priority maskable hardware interrupts
●
Non-maskable software/hardware interrupts
CPU registers
The six CPU registers shown in Figure 11 are not present in the memory mapping and are
accessed by specific instructions.
Accumulator (A)
The Accumulator is an 8-bit general purpose register used to hold operands and the results
of the arithmetic and logic calculations and to manipulate data.
Index Registers (X and Y)
These 8-bit registers are used to create effective addresses or as temporary storage areas
for data manipulation. (The Cross-Assembler generates a precede instruction (PRE) to
indicate that the following instruction refers to the Y register.)
The Y register is not affected by the interrupt automatic procedures.
Program Counter (PC)
The program counter is a 16-bit register containing the address of the next instruction to be
executed by the CPU. It is made of two 8-bit registers PCL (Program Counter Low which is
the LSB) and PCH (Program Counter High which is the MSB).
36/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Central processing unit
Figure 11. CPU registers
7
0
ACCUMULATOR
RESET VALUE = XXh
7
0
X INDEX REGISTER
RESET VALUE = XXh
7
0
Y INDEX REGISTER
RESET VALUE = XXh
PCH
15
PCL
8 7
0
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ FFFEh-FFFFh
7
0
1 1 I1 H I0 N Z C
CONDITION CODE REGISTER
RESET VALUE = 1 1 1 X 1 X X X
15
8 7
0
STACK POINTER
RESET VALUE = STACK HIGHER ADDRESS
X = Undefined Value
6.3.1
Condition code register (CC)
Reset value: 111x1xxx
7
1
0
1
I1
H
I0
N
Z
C
Read/Write
The 8-bit Condition Code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
Arithmetic management bits
Bit 4 = H Half carry.
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during
an ADD or ADC instructions. It is reset by hardware during the same instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
Doc ID 12321 Rev 6
37/247
Central processing unit
ST72344xx, ST2345xx
Bit 2 = N Negative.
This bit is set and cleared by hardware. It is representative of the result sign of the last
arithmetic, logical or data manipulation. It’s a copy of the result 7th bit.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative
(that is, the most significant bit is a logic 1).
This bit is accessed by the JRMI and JRPL instructions.
Bit 1 = Z Zero.
This bit is set and cleared by hardware. This bit indicates that the result of the last
arithmetic, logical or data manipulation is zero.
0: The result of the last operation is different from zero.
1: The result of the last operation is zero.
This bit is accessed by the JREQ and JRNE test instructions.
Bit 0 = C Carry/borrow.
This bit is set and cleared by hardware and software. It indicates an overflow or an
underflow has occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.
This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC
instructions. It is also affected by the “bit test and branch”, shift and rotate instructions.
Interrupt management bits
Bits 5,3 = I1, I0 Interrupt
The combination of the I1 and I0 bits gives the current interrupt software priority.
Table 6.
Interrupt software priority
Priority
I1
I0
Level 0 (main)
1
0
Level 1
0
1
Level 2
0
0
Level 3 (= interrupt disable)
1
1
These two bits are set/cleared by hardware when entering in interrupt. The loaded value is
given by the corresponding bits in the interrupt software priority registers (IxSPR). They can
be also set/cleared by software with the RIM, SIM, IRET, HALT, WFI and PUSH/POP
instructions.
See the interrupt management chapter for more details.
38/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
6.3.2
Central processing unit
Stack pointer (SP)
Reset value: 01 FFh
15
0
8
0
0
0
0
0
0
1
Read/Write
7
SP7
0
SP6
SP5
SP4
SP3
SP2
SP1
SP0
Read/Write
The Stack pointer is a 16-bit register which is always pointing to the next free location in the
stack. It is then decremented after data has been pushed onto the stack and incremented
before data is popped from the stack (see Figure 12).
Since the stack is 256 bytes deep, the 8 most significant bits are forced by hardware.
Following an MCU Reset, or after a Reset Stack Pointer instruction (RSP), the Stack pointer
contains its reset value (the SP7 to SP0 bits are set) which is the stack higher address.
The least significant byte of the Stack pointer (called S) can be directly accessed by an LD
instruction.
Note:
When the lower limit is exceeded, the Stack pointer wraps around to the stack upper limit,
without indicating the stack overflow. The previously stored information is then overwritten
and therefore lost. The stack also wraps in case of an underflow.
The stack is used to save the return address during a subroutine call and the CPU context
during an interrupt. The user may also directly manipulate the stack by means of the PUSH
and POP instructions. In the case of an interrupt, the PCL is stored at the first location
pointed to by the SP. Then the other registers are stored in the next locations as shown in
Figure 12.
●
When an interrupt is received, the SP is decremented and the context is pushed on the
stack.
●
On return from interrupt, the SP is incremented and the context is popped from the
stack.
A subroutine call occupies two locations and an interrupt five locations in the stack area.
Doc ID 12321 Rev 6
39/247
Central processing unit
ST72344xx, ST2345xx
Figure 12. Stack manipulation example
CALL
Subroutine
PUSH Y
Interrupt
Event
POP Y
RET
or RSP
IRET
@ 0100h
SP
SP
Y
CC
A
CC
A
X
X
X
PCH
PCH
PCL
PCL
PCL
PCH
PCH
PCH
PCH
PCH
PCL
PCL
PCL
PCL
PCL
Stack Higher Address = 01FFh
Stack Lower Address = 0100h
40/247
CC
A
PCH
SP
@ 01FFh
SP
Doc ID 12321 Rev 6
SP
SP
ST72344xx, ST2345xx
7
Supply, reset and clock management
Supply, reset and clock management
The device includes a range of utility features for securing the application in critical
situations (for example in case of a power brown-out), and reducing the number of external
components.
7.1
Main features
●
Clock management
–
1 MHz high-accuracy internal RC oscillator (enabled by option byte)
–
1 to 16 MHz External crystal/ceramic resonator (enabled by option byte)
–
External Clock Input (enabled by option byte)
–
PLL for multiplying the frequency by 8 or 4 (enabled by option byte)
●
Reset sequence manager (RSM)
●
System integrity management (SI)
–
Main supply low voltage detection (LVD) with reset generation (enabled by option
byte)
–
Auxiliary voltage detector (AVD) with interrupt capability for monitoring the main
supply (enabled by option byte)
Figure 13. Clock, reset and supply block diagram
RCCRH/RCCRL Register
MAIN CLOCK
CONTROLLER
WITH REAL-TIME
CLOCK(MCC/RTC)
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
fCPU
Tunable
External Clock (0.5-8 MHz)
RC Oscillator
RC Clock (1 MHz)
1 MHz
PLL 1 MHz --> 8 MHz
/2
DIVIDER
PLL 1 MHz --> 4 MHz 4 MHz
OSC Option bit
OSC1
OSC
1-16 MHz
OSC2
fOSC2
8 MHz
PLLx4x8
Option bit
/2
DIVIDER
/2
DIVIDER*
PLL Clock 8/4 MHz
DIV2EN
Option bit*
OSC, PLLOFF
OSCRANGE[2:0]
Option bits
Crystal OSC (0.5-8 MHz)
*not available if PLLx4 is enabled
Doc ID 12321 Rev 6
41/247
Supply, reset and clock management
7.2
ST72344xx, ST2345xx
Phase locked loop
The PLL can be used to multiply a 1 MHz frequency from the RC oscillator or the external
clock by 4 or 8 to obtain fOSC of 4 or 8 MHz. The PLL is enabled and the multiplication factor
of 4 or 8 is selected by 3 option bits. Refer to Table 7 for the PLL configuration depending on
the required frequency and the application voltage. Refer to Section 15.1 for the option byte
description.
Table 7.
PLL configurations
Target ratio
VDD
PLL ratio
DIV2
x4(1)
2.7 V - 3.65 V
x4
OFF
x8
ON
x8
OFF
x4
3.3 V - 5.5 V
x8
1. For a target ratio of x4 between 3.3 V - 3.65 V, this is the recommended configuration.
Figure 14. PLL output frequency timing diagram
LOCKED bit set
4/8 x
input
freq.
Output freq.
tSTAB
tLOCK
tSTARTUP
t
When the PLL is started, after reset or wakeup from Halt mode or AWUFH mode, it outputs
the clock after a delay of tSTARTUP.
When the PLL output signal reaches the operating frequency, the LOCKED bit in the
SICSCR register is set. Full PLL accuracy (ACCPLL) is reached after a stabilization time of
tSTAB (see Figure 14).
Refer to Section 7.6.5: Register description for a description of the LOCKED bit in the
SICSR register.
Caution:
The PLL is not recommended for applications where timing accuracy is required.
Caution:
When the RC oscillator and the PLL are enabled, it is recommended to calibrate this clock
through the RCCRH and RCCRL registers.
42/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
7.3
Supply, reset and clock management
Multioscillator (MO)
The main clock of the ST7 can be generated by three different source types coming from the
multioscillator block:
●
an external source
●
4 crystal or ceramic resonator oscillators
●
an internal high-accuracy RC oscillator
Each oscillator is optimized for a given frequency range in terms of consumption and is
selectable through the option byte. The associated hardware configurations are shown in
Table 8. Refer to Section 13: Electrical characteristics for more details.
Caution:
The OSC1 and/or OSC2 pins must not be left unconnected. For the purposes of Failure
Mode and Effect Analysis, it should be noted that if the OSC1 and/or OSC2 pins are left
unconnected, the ST7 main oscillator may start and, in this configuration, could generate an
fOSC clock frequency in excess of the allowed maximum (>16 MHz), putting the ST7 in an
unsafe/undefined state. The product behavior must therefore be considered undefined when
the OSC pins are left unconnected.
7.3.1
External clock source
In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle
has to drive the OSC1 pin while the OSC2 pin is tied to ground.
7.3.2
Crystal/ceramic oscillators
This family of oscillators has the advantage of producing a very accurate rate on the main
clock of the ST7. The selection within a list of 4 oscillators with different frequency ranges
has to be done by option byte in order to reduce consumption (refer to Section 15.1: Option
bytes for more details on the frequency ranges). In this mode of the multi-oscillator, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. The loading
capacitance values must be adjusted according to the selected oscillator.
These oscillators are not stopped during the reset phase to avoid losing time in the oscillator
startup phase.
Doc ID 12321 Rev 6
43/247
Supply, reset and clock management
Table 8.
ST72344xx, ST2345xx
ST7 clock sources
Internal RC oscillator Crystal/ceramic resonators
External clock
Hardware configuration
44/247
ST7
OSC1
OSC2
EXTERNAL
SOURCE
ST7
OSC1
CL1
OSC2
LOAD
CAPACITORS
ST7
OSC1
Doc ID 12321 Rev 6
OSC2
CL2
ST72344xx, ST2345xx
7.3.3
Supply, reset and clock management
Internal RC oscillator
The device contains a high-precision internal RC oscillator. It must be calibrated to obtain
the frequency required in the application. This is done by software writing a calibration value
in the RCCRH and RCCRL Registers.
Whenever the microcontroller is reset, the RCCR returns to its default value (FF 03h), i.e.
each time the device is reset, the calibration value must be loaded in the RCCRH and
RCCRL registers. Predefined calibration values are stored in XFlash for 3 and 5V VDD
supply voltages at 25 °C, as shown in the following table:
Table 9.
Note:
Calibration values
RCCR
Conditions
Address
RCCR0
VDD = 5 V
TA = 25 °C
fRC = 1 MHz
BEE0, BEE1
RCCR1
VDD = 3 V
TA = 25 °C
fRC = 1 MHz
BEE4, BEE5
To improve clock stability, it is recommended to place a decoupling capacitor between the
VDD and VSS pins.
These two 10-bit values are systematically programmed by ST.
RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset
after it has been set. See Section 4.5: Memory protection.
Caution:
If the voltage or temperature conditions change in the application, the frequency may need
to be recalibrated.
Refer to application note AN1324 for information on how to calibrate the RC frequency using
an external reference signal.
7.4
Register description
7.4.1
RC control register (RCCRH)
Reset value: 1111 1111 (FFh)
7
CR9
0
CR8
CR7
CR6
CR5
CR4
CR3
CR2
Read/Write
Bits 7:0 = CR[9:2] RC oscillator frequency adjustment bits
Doc ID 12321 Rev 6
45/247
Supply, reset and clock management
7.4.2
ST72344xx, ST2345xx
RC control register (RCCRL)
Reset value: 0000 0011 (03h)
7
0
0
0
0
0
0
0
CR1
CR0
Read/Write
Bits 7:2 = Reserved, must be kept cleared.
Bits 1:0 = CR[1:0] RC Oscillator Frequency Adjustment Bits
This 10-bit value must be written immediately after reset to adjust the RC oscillator
frequency in order to obtain the specified accuracy. The application can store the
correct value for each voltage range in EEPROM and write it to this register at startup.
0000h = maximum available frequency
03FFh = lowest available frequency
Note:
To tune the oscillator, write a series of different values in the register until the correct
frequency is reached. The fastest method is to use a dichotomy starting with 200h.
7.5
Reset sequence manager (RSM)
7.5.1
Introduction
The reset sequence manager includes three reset sources as shown in Figure 16:
Note:
●
External RESET source pulse
●
Internal LVD reset (low voltage detection)
●
Internal watchdog reset
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to Section 12.2.1: Illegal opcode reset on page 196 for further details.
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of 3 phases as shown in Figure 15:
Caution:
●
Active phase depending on the reset source
●
256 or 4096 CPU clock cycle delay (selected by option byte)
●
reset vector fetch
When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the Reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application (see Section 15.1: Option bytes).
The reset vector fetch phase duration is 2 clock cycles.
46/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Supply, reset and clock management
Figure 15. reset sequence phases
RESET
Active phase
7.5.2
Internal Reset
256 or 4096 clock cycles
Fetch
vector
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated RON weak pull-up
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See Section 13: Electrical
characteristics for more details.
A reset signal originating from an external source must have a duration of at least th(RSTL)in
in order to be recognized (see Figure 17). This detection is asynchronous and therefore the
MCU can enter reset state even in Halt mode.
Figure 16. Reset block diagram
VDD
RON
INTERNAL
RESET
Filter
RESET
PULSE
GENERATOR
WATCHDOG RESET
ILLEGAL OPCODE RESET (1)
LVD RESET
1. See Section 12.2.1: Illegal opcode reset for more details on illegal opcode reset conditions.
The RESET pin is an asynchronous signal which plays a major role in EMS performance. In
a noisy environment, it is recommended to follow the guidelines mentioned in Section 13:
Electrical characteristics.
If the external RESET pulse is shorter than tw(RSTL)out (see short ext. Reset in Figure 17),
the signal on the RESET pin may be stretched. Otherwise the delay will not be applied (see
long ext. Reset in Figure 17). Starting from the external RESET pulse recognition, the
device RESET pin acts as an output that is pulled low during at least tw(RSTL)out.
7.5.3
External power-on reset
If the LVD is disabled by option byte, to start up the microcontroller correctly, the user must
ensure by means of an external reset circuit that the reset signal is held low until VDD is over
the minimum level specified for the selected fOSC frequency (see Section 13.3: Operating
conditions).
A proper reset signal for a slow rising VDD supply can generally be provided by an external
RC network connected to the RESET pin.
Doc ID 12321 Rev 6
47/247
Supply, reset and clock management
7.5.4
ST72344xx, ST2345xx
Internal low-voltage detector (LVD) reset
Two different reset sequences caused by the internal LVD circuitry can be distinguished:
●
Power-on reset
●
Voltage-drop reset
The device RESET pin acts as an output that is pulled low when VDD W6:0 CMP
Write WDGCR
WATCHDOG CONTROL REGISTER (WDGCR)
WDGA
T6
T5
T3
T2
T1
T0
6-BIT DOWNCOUNTER (CNT)
MCC/RTC
fOSC2
T4
DIV 64
WDG PRESCALER
DIV 4
12-BIT MCC
RTC COUNTER
MSB
11
LSB
6 5
0
TB[1:0] bits
(MCCSR
Register)
The application program must write in the WDGCR register at regular intervals during
normal operation to prevent an MCU reset. This operation must occur only when the counter
value is lower than the window register value. The value to be stored in the WDGCR register
must be between FFh and C0h (see Figure 38: Approximate timeout duration):
●
Enabling the watchdog:
When Software Watchdog is selected (by option byte), the watchdog is disabled after a
reset. It is enabled by setting the WDGA bit in the WDGCR register, then it cannot be
disabled again except by a reset.
When Hardware Watchdog is selected (by option byte), the watchdog is always active
and the WDGA bit is not used.
●
Controlling the downcounter:
This downcounter is free-running: It counts down even if the watchdog is disabled.
When the watchdog is enabled, the T6 bit must be set to prevent generating an
immediate reset.
The T[5:0] bits contain the number of increments which represents the time delay
before the watchdog produces a reset (see Figure 38). The timing varies between a
minimum and a maximum value due to the unknown status of the prescaler when
writing to the WDGCR register (see Figure 39: Exact timeout duration (tmin and tmax)).
The window register (WDGWR) contains the high limit of the window: To prevent a
reset, the downcounter must be reloaded when its value is lower than the window
register value and greater than 3Fh. Figure 40: Window watchdog timing diagram
describes the window watchdog process.
Doc ID 12321 Rev 6
83/247
On-chip peripherals
Note:
ST72344xx, ST2345xx
The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is
cleared).
●
Watchdog reset on Halt option
If the watchdog is activated and the watchdog reset on halt option is selected, then the
HALT instruction will generate a Reset.
11.1.4
Using Halt mode with the WDG
If Halt mode with Watchdog is enabled by option byte (no watchdog reset on HALT
instruction), it is recommended before executing the HALT instruction to refresh the WDG
counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller.
11.1.5
How to program the watchdog timeout
Figure 38 shows the linear relationship between the 6-bit value to be loaded in the watchdog
counter (CNT) and the resulting timeout duration in milliseconds. This can be used for a
quick calculation without taking the timing variations into account. If more precision is
needed, use the formulae in Figure 39.
Caution:
When writing to the WDGCR register, always write 1 in the T6 bit to avoid generating an
immediate reset.
Figure 38. Approximate timeout duration
3F
38
CNT Value (hex.)
30
28
20
18
10
08
00
1.5
18
34
50
65
82
Watchdog timeout (ms) @ 8 MHz fOSC2
84/247
Doc ID 12321 Rev 6
98
114
128
ST72344xx, ST2345xx
On-chip peripherals
Figure 39. Exact timeout duration (tmin and tmax)
Where:
tmin0 = (LSB + 128) x 64 x tOSC2
tmax0 = 16384 x tOSC2
tOSC2 = 125 ns if fOSC2 = 8 MHz
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0]
bits in the MCCSR register
TB1 bit
(MCCSR Reg.)
TB0 bit
(MCCSR Reg.)
Selected MCCSR
time base
MSB
LSB
0
0
2 ms
4
59
0
1
4 ms
8
53
1
0
10 ms
20
35
1
1
25 ms
49
54
To calculate the minimum watchdog timeout (tmin):
If
MSB
CNT < ------------4
then
else
t min = t min0
+ 16384 ×
CNT
×
t osc2
4CNT
t min = t min0 + 16384 × ⎛ CNT – ----------------- ⎞
⎝
MSB ⎠
+ ( 192 + LSB ) ×
4CNT
64 × ----------------MSB
×
t osc2
To calculate the maximum Watchdog Timeout (tmax):
If
CNT
------------≤ MSB
4
Note:
CNT × t osc2
⎛
----------------- ⎞
else tmax = t max0 + 16384 × ⎝ CNT – 4CNT
MSB ⎠
then
t max = t max0
+ 16384 ×
+ ( 192 + LSB ) ×
4CNT
64 × ----------------MSB
×
t osc2
In the above formulae, division results must be rounded down to the next integer
value.
Example:
With 2 ms timeout selected in MCCSR register
Value of T[5:0] Bits in
WDGCR Register (Hex.)
Min. watchdog timeout (ms)
tmin
Max. watchdog timeout (ms)
tmax
00
1.496
2.048
3F
128
128.552
Doc ID 12321 Rev 6
85/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 40. Window watchdog timing diagram
T[5:0] CNT downcounter
WDGWR
3Fh
Refresh not allowed Refresh Window
time
(step = 16384/fOSC2)
T6 bit
Reset
11.1.6
Low-power modes
Table 37.
Descriptions
Mode
Description
Slow
No effect on Watchdog: the downcounter continues to decrement at normal speed.
Wait
No effect on Watchdog: the downcounter continues to decrement.
OIE bit in
MCCSR
register
WDGHALT
bit in
Option Byte
0
0
No Watchdog reset is generated. The MCU enters Halt
mode. The Watchdog counter is decremented once and
then stops counting and is no longer able to generate a
watchdog reset until the MCU receives an external
interrupt or a reset.
If an interrupt is received (refer to interrupt table mapping
to see interrupts which can occur in halt mode), the
Watchdog restarts counting after 256 or 4096 CPU clocks.
If a reset is generated, the Watchdog is disabled (reset
state) unless Hardware Watchdog is selected by option
byte. For application recommendations see Section 11.1.8
below.
0
1
A reset is generated instead of entering halt mode.
x
No reset is generated. The MCU enters Active Halt mode.
The Watchdog counter is not decremented. It stop
counting. When the MCU receives an oscillator interrupt or
external interrupt, the Watchdog restarts counting
immediately. When the MCU receives a reset, the
Watchdog restarts counting after 256 or 4096 CPU clocks.
Halt
Active-halt
86/247
1
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
11.1.7
On-chip peripherals
Hardware watchdog option
If hardware watchdog is selected by option byte, the watchdog is always active and the
WDGA bit in the WDGCR is not used. Refer to the Option Byte description.
11.1.8
Using Halt mode with the WDG (WDGHALT option)
The following recommendation applies if Halt mode is used when the watchdog is enabled.
●
11.1.9
Before executing the HALT instruction, refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking up the microcontroller.
Interrupts
None.
11.1.10
Register description
Control register (WDGCR)
Reset value: 0111 1111 (7Fh)
7
WDGA
0
T6
T5
T4
T3
T2
T1
T0
Read/Write
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1,
the watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note:
This bit is not used if the hardware watchdog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit counter (MSB to LSB).
These bits contain the value of the watchdog counter. It is decremented every
16384 fOSC2 cycles (approx.). A reset is produced when it rolls over from 40h to 3Fh
(T6 becomes cleared).
Window register (WDGWR)
Reset value: 0111 1111 (7Fh)
7
-
0
W6
W5
W4
W3
W2
W1
W0
Read/Write
Bit 7 = Reserved
Bits 6:0 = W[6:0] 7-bit window value
These bits contain the window value to be compared to the downcounter.
Doc ID 12321 Rev 6
87/247
On-chip peripherals
Table 38.
11.2
ST72344xx, ST2345xx
Watchdog timer register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
2A
WDGCR
Reset value
WDGA
0
T6
1
T5
1
T4
1
T3
1
T2
1
T1
1
T0
1
30
WDGWR
Reset value
0
W6
1
W5
1
W4
1
W3
1
W2
1
W1
1
W0
1
Main clock controller with real-time clock and beeper
(MCC/RTC)
The main clock controller consists of three different functions:
●
a programmable CPU clock prescaler
●
a clock-out signal to supply external devices
●
a real-time clock timer with interrupt capability
Each function can be used independently and simultaneously.
11.2.1
Programmable CPU clock prescaler
The programmable CPU clock prescaler supplies the clock for the ST7 CPU and its internal
peripherals. It manages Slow power-saving mode (See Section 9.2: Slow mode for more
details).
The prescaler selects the fCPU main clock frequency and is controlled by three bits in the
MCCSR register: CP[1:0] and SMS.
11.2.2
Clock-out capability
The clock-out capability is an alternate function of an I/O port pin that outputs a fOSC2 clock
to drive external devices. It is controlled by the MCO bit in the MCCSR register.
Caution:
When selected, the clock out pin suspends the clock during Active-halt mode.
11.2.3
Real-time clock timer (RTC)
The counter of the real-time clock timer allows an interrupt to be generated based on an
accurate real-time clock. Four different time bases depending directly on fOSC2 are available.
The whole functionality is controlled by four bits of the MCCSR register: TB[1:0], OIE and
OIF.
When the RTC interrupt is enabled (OIE bit set), the ST7 enters Active-halt mode when the
HALT instruction is executed. See Section 9.5: Active-halt mode for more details.
11.2.4
Beeper
The beep function is controlled by the MCCBCR register. It can output three selectable
frequencies on the BEEP pin (I/O port alternate function).
88/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 41. Main clock controller (MCC/RTC) block diagram
BC1 BC0
MCCBCR
BEEP
BEEP SIGNAL
SELECTION
MCO
12-BIT MCC RTC
COUNTER
DIV 64
MCO CP1 CP0 SMS TB1 TB0 OIE
MCCSR
fOSC2
TO
WATCHDOG
TIMER
OIF
MCC/RTC INTERRUPT
1
DIV 2, 4, 8, 16
CPU CLOCK
TO CPU AND
PERIPHERALS
fCPU
0
11.2.5
Low-power modes
Table 39.
Mode description
Mode
11.2.6
Description
Wait
No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit from Wait mode.
Active-halt
No effect on MCC/RTC counter (OIE bit is set), the registers are frozen.
MCC/RTC interrupt cause the device to exit from Active-halt mode.
Halt
MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the MCU is woken up by an interrupt with “exit
from Halt” capability.
Interrupts
The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is
set and the interrupt mask in the CC register is not active (RIM instruction).
Table 40.
Interrupt event
Interrupt event
Time base overflow event
Event flag
Enable
Control bit
Exit from
Wait
Exit from
Halt
OIF
OIE
Yes
No (1)
1. The MCC/RTC interrupt wakes up the MCU from Active-halt mode, not from Halt mode.
Doc ID 12321 Rev 6
89/247
On-chip peripherals
11.2.7
ST72344xx, ST2345xx
Register description
MCC control/status register (MCCSR)
Reset value: 0000 0000 (00h)
7
MCO
0
CP1
CP0
SMS
TB1
TB0
OIE
OIF
Read/Write
Bit 7 = MCO Main clock out selection
This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared by
software.
0: MCO alternate function disabled (I/O pin free for general-purpose I/O)
1: MCO alternate function enabled (fCPU on I/O port)
Note:
To reduce power consumption, the MCO function is not active in Active-halt mode.
Bits 6:5 = CP[1:0] CPU clock prescaler
These bits select the CPU clock prescaler which is applied in the different slow modes.
Their action is conditioned by the setting of the SMS bit. These two bits are set and
cleared by software.
Table 41.
CPU clock prescaler selection
fCPU in Slow mode
CP1
CP0
fOSC2 / 2
0
0
fOSC2 / 4
0
1
fOSC2 / 8
1
0
fOSC2 / 16
1
1
Bit 4 = SMS Slow mode select
This bit is set and cleared by software.
0: Normal mode. fCPU = fOSC2
1: Slow mode. fCPU is given by CP1, CP0
See Section 9.2: Slow mode and Section 11.1: Window watchdog (WWDG) for more
details.
Bits 3:2 = TB[1:0] Time base control
These bits select the programmable divider time base. They are set and cleared by
software.
90/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Table 42.
On-chip peripherals
Time base control
Time base
Counter
prescaler
TB1
TB0
2 ms
0
0
8 ms
4 ms
0
1
80000
20 ms
10 ms
1
0
200000
50 ms
25 ms
1
1
fOSC2 = 4 MHz
fOSC2 = 8 MHz
16000
4 ms
32000
A modification of the time base is taken into account at the end of the current period
(previously set) to avoid an unwanted time shift. This allows to use this time base as a realtime clock.
Bit 1 = OIE Oscillator interrupt enable
This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt can be used to exit from Active-halt mode.
When this bit is set, calling the ST7 software HALT instruction enters the Active-halt
power-saving mode
.
Bit 0 = OIF Oscillator interrupt flag
This bit is set by hardware and cleared by software reading the MCCSR register. It
indicates when set that the main oscillator has reached the selected elapsed time
(TB1:0).
0: Timeout not reached
1: Timeout reached
Caution:
The BRES and BSET instructions must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.
MCC beep control register (MCCBCR)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
0
BC1
BC0
Read/Write
Bits 7:2 = Reserved, must be kept cleared.
Bits 1:0 = BC[1:0] Beep control
These 2 bits select the PF1 pin beep capability.
Doc ID 12321 Rev 6
91/247
On-chip peripherals
Table 43.
ST72344xx, ST2345xx
Beep control
BC1
BC0
Beep mode with fOSC2 = 8 MHz
0
0
Off
0
1
~2-kHz
1
0
~1-kHz
1
1
~500-Hz
Output
beep signal
~50% duty cycle
The beep output signal is available in Active-halt mode but has to be disabled to reduce the
consumption.
Table 44.
92/247
Main clock controller register map and reset values
Address
(Hex.)
Register
label
002Bh
7
6
5
4
3
2
1
0
SICSR
Reset value
0
AVDIE
0
AVDF
0
LVDRF
x
LOCKED
0
0
0
WDGRF
x
002Ch
MCCSR
Reset value
MCO
0
CP1
0
CP0
0
SMS
0
TB1
0
TB0
0
OIE
0
OIF
0
002Dh
MCCBCR
Reset value
0
0
0
0
0
0
BC1
0
BC0
0
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
11.3
16-bit timer
11.3.1
Introduction
On-chip peripherals
The timer consists of a 16-bit free-running counter driven by a programmable prescaler.
It may be used for a variety of purposes, including pulse length measurement of up to two
input signals (input capture) or generation of up to two output waveforms (output compare
and PWM).
Pulse lengths and waveform periods can be modulated from a few microseconds to several
milliseconds using the timer prescaler and the CPU clock prescaler.
Some devices of the ST7 family have two on-chip 16-bit timers. They are completely
independent, and do not share any resources. They are synchronized after a Device reset
as long as the timer clock frequencies are not modified.
This description covers one or two 16-bit timers. In the devices with two timers, register
names are prefixed with TA (Timer A) or TB (Timer B).
11.3.2
Main features
●
Programmable prescaler: fCPU divided by 2, 4 or 8.
●
Overflow status flag and maskable interrupt
●
External clock input (must be at least 4 times slower than the CPU clock speed) with
the choice of active edge
●
Output compare functions with
●
–
2 dedicated 16-bit registers
–
2 dedicated programmable signals
–
2 dedicated status flags
–
1 dedicated maskable interrupt
Input capture functions with
–
2 dedicated 16-bit registers
–
2 dedicated active edge selection signals
–
2 dedicated status flags
–
1 dedicated maskable interrupt
●
Pulse width modulation mode (PWM)
●
One-pulse mode
●
Reduced-power mode
●
5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK). See the
note below.
The block diagram is shown in Figure 42.
Note:
Some timer pins may not be available (not bonded) in some devices. Refer to the device pin
out description. When reading an input signal on a non-bonded pin, the value will always
be ‘1’.
Doc ID 12321 Rev 6
93/247
On-chip peripherals
11.3.3
ST72344xx, ST2345xx
Functional description
Counter
The main block of the programmable timer is a 16-bit free running upcounter and its
associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called
high & low.
Counter Register (CR):
●
Counter High Register (CHR) is the most significant byte (MS Byte).
●
Counter Low Register (CLR) is the least significant byte (LS Byte).
Alternate Counter Register (ACR)
●
Alternate Counter High Register (ACHR) is the most significant byte (MS Byte).
●
Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte).
These two read-only 16-bit registers contain the same value but with the difference that
reading the ACLR register does not clear the TOF bit (Timer overflow flag) located in the
Status register (SR). (See the following Note:).
Writing in the CLR register or ACLR register resets the free running counter to the FFFCh
value.
Both counters have a reset value of FFFCh (this is the only value which is reloaded in the
16-bit timer). The reset value of both counters is also FFFCh in One-pulse mode and PWM
mode.
The timer clock depends on the clock control bits of the CR2 register, as illustrated in
Table 50: Clock control bits. The value in the counter register repeats every 131 072, 262
144 or 524 288 CPU clock cycles, depending on the CC[1:0] bits.
The timer frequency can be fCPU/2, fCPU/4, fCPU/8 or an external frequency.
94/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 42. Timer block diagram
INTERNAL BUS
fCPU
16-BIT TIMER PERIPHERAL INTERFACE
8 low
8
8
8
low
8
high
8
low
8
high
EXEDG
8
low
high
8
high
8-bit
buffer
low
8 high
16
1/2
1/4
1/8
OUTPUT
COMPARE
REGISTER
2
OUTPUT
COMPARE
REGISTER
1
COUNTER
REGISTER
ALTERNATE
COUNTER
REGISTER
EXTCLK
pin
INPUT
CAPTURE
REGISTER
1
INPUT
CAPTURE
REGISTER
2
16
16
16
CC[1:0]
TIMER INTERNAL BUS
16 16
OVERFLOW
DETECT
CIRCUIT
OUTPUT COMPARE
CIRCUIT
6
ICF1 OCF1 TOF ICF2 OCF2 TIMD
0
EDGE DETECT
CIRCUIT1
ICAP1
pin
EDGE DETECT
CIRCUIT2
ICAP2
pin
LATCH1
OCMP1
pin
LATCH2
OCMP2
pin
0
(Control/Status Register)
CSR
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
OC1E OC2E OPM PWM
(Control Register 1) CR1
CC1
CC0 IEDG2 EXEDG
(Control Register 2) CR2
(See note 1)
TIMER INTERRUPT
1. If IC, OC and TO interrupt requests have separate vectors, then the last OR is not present (See Device
Interrupt Vector Table).
Doc ID 12321 Rev 6
95/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 43. 16-bit read sequence (from either the counter register or the alternate
counter register)
Beginning of the sequence
At t0
Read
MS Byte
LS Byte
is buffered
Other
instructions
Read
At t0 +Δt LS Byte
Returns the buffered
LS Byte value at t0
Sequence completed
The user must read the MS Byte first, then the LS Byte value is buffered automatically.
This buffered value remains unchanged until the 16-bit read sequence is completed, even if
the user reads the MS Byte several times.
After a complete reading sequence, if only the CLR register or ACLR register are read, they
return the LS Byte of the count value at the time of the read.
Whatever the timer mode used (input capture, output compare, one-pulse mode or PWM
mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then:
●
The TOF bit of the SR register is set.
●
A timer interrupt is generated if:
–
TOIE bit of the CR1 register is set and
–
I bit of the CC register is cleared.
If one of these conditions is false, the interrupt remains pending to be issued as soon as
they are both true.
Clearing the overflow interrupt request is done in two steps:
Note:
1.
Reading the SR register while the TOF bit is set.
2.
An access (read or write) to the CLR register.
The TOF bit is not cleared by accesses to ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that it allows simultaneous use of the overflow
function and reading the free running counter at random times (for example, to measure
elapsed time) without the risk of clearing the TOF bit erroneously.
The timer is not affected by Wait mode.
In Halt mode, the counter stops counting until the mode is exited. Counting then resumes
from the previous count (Device awakened by an interrupt) or from the reset count (Device
awakened by a Reset).
External clock
The external clock (where available) is selected if CC0=1 and CC1=1 in CR2 register.
The status of the EXEDG bit in the CR2 register determines the type of level transition on
the external clock pin EXTCLK that will trigger the free running counter.
The counter is synchronized with the falling edge of the internal CPU clock.
96/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
A minimum of four falling edges of the CPU clock must occur between two consecutive
active edges of the external clock; thus, the external clock frequency must be less than a
quarter of the CPU clock frequency.
Figure 44. Counter timing diagram, internal clock divided by 2
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFD FFFE FFFF 0000
0001
0002
0003
TIMER OVERFLOW FLAG (TOF)
Figure 45. Counter timing diagram, internal clock divided by 4
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
0001
TIMER OVERFLOW FLAG (TOF)
Figure 46. Counter timing diagram, internal clock divided by 8
CPU CLOCK
INTERNAL RESET
TIMER CLOCK
COUNTER REGISTER
FFFC
FFFD
0000
TIMER OVERFLOW FLAG (TOF)
Note:
The device is in reset state when the internal reset signal is high. When it is low, the Device
is running.
Doc ID 12321 Rev 6
97/247
On-chip peripherals
ST72344xx, ST2345xx
Input capture
In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the
16-bit timer.
The two input-capture 16-bit registers (IC1R and IC2R) are used to latch the value of the
free-running counter after a transition detected by the ICAPi pin.
Table 45.
ICiR register
ICiR
MS Byte
LS Byte
ICiHR
ICiLR
ICiR register is a read-only register. The active transition is software-programmable through
the IEDGi bit of Control Registers (CRi). The timing resolution is one count of the freerunning counter: (fCPU/CC[1:0]).
Procedure:
To use the input capture function, select the following in the CR2 register:
●
Select the timer clock (CC[1:0]) (see Table 50: Clock control bits).
●
Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2
pin must be configured as floating input).
And select the following in the CR1 register:
●
Set the ICIE bit to generate an interrupt after an input capture coming from either the
ICAP1 pin or the ICAP2 pin
●
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1pin must be configured as floating input).
When an input capture occurs:
●
ICFi bit is set.
●
The ICiR register contains the value of the free running counter on the active transition
on the ICAPi pin (see Figure 48).
●
A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC
register. Otherwise, the interrupt remains pending until both conditions become true.
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
Note:
98/247
1.
Reading the SR register while the ICFi bit is set.
2.
An access (read or write) to the ICiLR register.
1
After reading the ICiHR register, transfer of input capture data is inhibited and ICFi will never
be set until the ICiLR register is also read.
2
The ICiR register contains the free running counter value which corresponds to the most
recent input capture.
3
The 2 input capture functions can be used together even if the timer also uses the 2 output
compare functions.
4
In One-pulse Mode and PWM mode only the input capture 2 can be used.
5
The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any
transitions on these pins activate the input capture function.
Moreover, if one of the ICAPi pins is configured as an input and the second one as an
output, an interrupt can be generated provided that the user toggles the output pin and that
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading
the ICiHR (see note 1).
6
The TOF bit can be used with interrupt in order to measure events that go beyond the timer
range (FFFFh).
Figure 47. Input capture block diagram
ICAP1
pin
ICAP2
pin
(Control Register 1) CR1
EDGE DETECT
CIRCUIT2
EDGE DETECT
CIRCUIT1
ICIE
IEDG1
(Status Register) SR
IC2R Register
IC1R Register
ICF1
ICF2
0
0
0
(Control Register 2) CR2
16-BIT
16-BIT FREE RUNNING
CC1
CC0 IEDG2
COUNTER
Figure 48. Input capture timing diagram
TIMER CLOCK
COUNTER REGISTER
FF01
FF02
FF03
ICAPi PIN
ICAPi FLAG
FF03
ICAPi REGISTER
1. The active edge is the rising edge.
2. The time between an event on the ICAPi pin and the appearance of the corresponding flag is from 2 to 3
CPU clock cycles. This depends on the moment when the ICAP event happens relative to the timer clock.
Output compare
In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in
the 16-bit timer.
This function can be used to control an output waveform or indicate when a period of time
has elapsed.
Doc ID 12321 Rev 6
99/247
On-chip peripherals
ST72344xx, ST2345xx
When a match is found between the Output Compare register and the free running counter,
the output compare function:
●
Assigns pins with a programmable value if the OCIE bit is set
●
Sets a flag in the status register
●
Generates an interrupt if enabled
Two 16-bit registers, Output Compare Register 1 (OC1R) and Output Compare Register 2
(OC2R), contain the value to be compared to the counter register each timer clock cycle.
Table 46.
OCiR register
OCiR
MS Byte
LS Byte
OCiHR
OCiLR
These registers are readable and writable and are not affected by the timer hardware. A
reset event changes the OCiR value to 8000h.
The timing resolution is one count of the free running counter: (fCPU/CC[1:0]).
Procedure:
To use the output compare function, select the following in the CR2 register:
●
Set the OCiE bit if an output is needed then the OCMPi pin is dedicated to the output
compare i signal.
●
Select the timer clock (CC[1:0]) (see Table 50: Clock control bits).
And select the following in the CR1 register:
●
Select the OLVLi bit to applied to the OCMPi pins after the match occurs.
●
Set the OCIE bit to generate an interrupt if it is needed.
When a match is found between OCRi register and CR register:
●
OCFi bit is set.
●
The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset).
●
A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is
cleared in the CC register (CC).
The OCiR register value required for a specific timing application can be calculated using
the following formula:
Δ OCiR =
Δt * fCPU
PRESC
Where:
●
Δt = Output compare period (in seconds)
●
fCPU = CPU clock frequency (in Hertz)
●
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 50)
If the timer clock is an external clock, the formula is:
Δ OCiR = Δt * fEXT
Where:
100/247
●
Δt = Output compare period (in seconds)
●
fEXT = External timer clock frequency (in Hertz)
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by:
1.
Reading the SR register while the OCFi bit is set.
2.
An access (read or write) to the OCiLR register.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OCiR register:
Note:
●
Write to the OCiHR register (further compares are inhibited).
●
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
●
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
1
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
2
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
3
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see Figure 50 and Figure 51). This behavior is the same in
OPM or PWM mode.
4
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
5
The value in the 16-bit OCiR register and the OLVi bit should be changed after each
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
Forced compare output capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
FOLVLi bits have no effect in both one-pulse mode and PWM mode.
Figure 49. Output compare block diagram
16 BIT FREE RUNNING
COUNTER
OC1E OC2E
CC1
CC0
(Control Register 2) CR2
16-bit
(Control Register 1) CR1
OUTPUT COMPARE
CIRCUIT
16-bit
OCIE
FOLV2 FOLV1 OLVL2
OLVL1
16-bit
Latch
1
Latch
2
OC1R Register
OCF1
OCF2
0
0
OCMP1
Pin
OCMP2
Pin
0
OC2R Register
(Status Register) SR
Doc ID 12321 Rev 6
101/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 50. Output compare timing diagram, fTIMER = fCPU/2
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0
OUTPUT COMPARE REGISTER i (OCRi)
2ED1 2ED2 2ED3 2ED4
2ED3
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
Figure 51. Output compare timing diagram, fTIMER = fCPU/4
INTERNAL CPU CLOCK
TIMER CLOCK
COUNTER REGISTER
2ECF 2ED0
OUTPUT COMPARE REGISTER i (OCRi)
COMPARE REGISTER i LATCH
OUTPUT COMPARE FLAG i (OCFi)
OCMPi PIN (OLVLi=1)
102/247
Doc ID 12321 Rev 6
2ED1 2ED2 2ED3 2ED4
2ED3
ST72344xx, ST2345xx
On-chip peripherals
One-pulse mode
One-pulse mode enables the generation of a pulse when an external event occurs. This
mode is selected via the OPM bit in the CR2 register.
The one-pulse mode uses the Input Capture1 function and the Output Compare1 function.
Procedure:
To use one-pulse mode:
1.
Load the OC1R register with the value corresponding to the length of the pulse (see the
formula in the opposite column).
2.
Select the following in the CR1 register:
3.
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after the
pulse.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin during the
pulse.
–
Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the
ICAP1 pin must be configured as floating input).
Select the following in the CR2 register:
–
Set the OC1E bit, the OCMP1 pin is then dedicated to the Output Compare 1
function.
–
Set the OPM bit.
–
Select the timer clock CC[1:0] (see Table 50: Clock control bits).
Figure 52. One-pulse mode cycle
One-pulse mode cycle
When
event occurs
on ICAP1
ICR1 = Counter
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
When
Counter
= OC1R
OCMP1 = OLVL1
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1
register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin
and the ICF1 bit is set.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the Input Capture interrupt request (i.e. clearing the ICFi bit) is done in two steps:
1.
Reading the SR register while the ICFi bit is set.
2.
An access (read or write) to the ICiLR register.
Doc ID 12321 Rev 6
103/247
On-chip peripherals
ST72344xx, ST2345xx
The OC1R register value required for a specific timing application can be calculated using
the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
●
t = Pulse period (in seconds)
●
fCPU = CPU clock frequency (in Hertz)
●
PRESC = Timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see Table 50:
Clock control bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
●
t = Pulse period (in seconds)
●
fEXT = External timer clock frequency (in Hertz)
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin (See Figure 53).
Note:
1
The OCF1 bit cannot be set by hardware in One-pulse mode but the OCF2 bit can generate
an Output Compare interrupt.
2
When the Pulse Width Modulation (PWM) and One-pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
3
If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
4
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
5
When One-pulse mode is used, OC1R is dedicated to this mode. Nevertheless, OC2R and
OCF2 can be used to indicate that a period of time has been elapsed but cannot generate
an output waveform, because the OLVL2 level is dedicated to the One-pulse mode.
Figure 53. One-pulse mode timing example
COUNTER
2ED3
01F8
IC1R
01F8
FFFC FFFD FFFE
2ED0 2ED1 2ED2
FFFC FFFD
2ED3
ICAP1
OCMP1
OLVL2
OLVL1
compare1
1. IEDG1=1, OC1R=2ED0h, OLVL1=0, OLVL2=1.
104/247
Doc ID 12321 Rev 6
OLVL2
ST72344xx, ST2345xx
On-chip peripherals
Figure 54. Pulse width modulation mode timing example
COUNTER 34E2 FFFC FFFD FFFE
2ED0 2ED1 2ED2
OLVL2
OCMP1
compare2
34E2
OLVL1
compare1
FFFC
OLVL2
compare2
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Pulse-width modulation mode
Pulse-width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse-width modulation mode uses the complete Output Compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are loaded in their respective shadow
registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the
PWM output pin (OCMP1). The shadow registers contain the reference values for
comparison in PWM “double buffering” mode.
Note:
There is a locking mechanism for transferring the OCiR value to the buffer. After a write to
the OCiHR register, the transfer of the new compare value to the buffer is inhibited until
OCiLR is also written.
Unlike in Output Compare mode, the compare function is always enabled in PWM mode.
Procedure:
To use pulse-width modulation mode:
1.
Load the OC2R register with the value corresponding to the period of the signal using
the formula in the opposite column.
2.
Load the OC1R register with the value corresponding to the period of the pulse if
(OLVL1=0 and OLVL2=1) using the formula in the opposite column.
3.
Select the following in the CR1 register:
4.
–
Using the OLVL1 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with OC1R register.
–
Using the OLVL2 bit, select the level to be applied to the OCMP1 pin after a
successful comparison with OC2R register.
Select the following in the CR2 register:
–
Set OC1E bit: the OCMP1 pin is then dedicated to the output compare 1 function.
–
Set the PWM bit.
–
Select the timer clock (CC[1:0]) (see Table 50: Clock control bits).
Doc ID 12321 Rev 6
105/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 55. Pulse width modulation cycle
Pulse-width modulation cycle
When
Counter
= OC1R
When
Counter
= OC2R
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
to FFFCh
ICF1 bit is set
If OLVL1=1 and OLVL2=0 the length of the positive pulse is the difference between the
OC2R and OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin.
The OCiR register value required for a specific timing application can be calculated using
the following formula:
OCiR Value =
t * fCPU
-5
PRESC
Where:
●
t = Signal or pulse period (in seconds)
●
fCPU = CPU clock frequency (in Hertz)
●
PRESC = Timer prescaler factor (2, 4 or 8 depending on CC[1:0] bits, see Table 50:
Clock control bits)
If the timer clock is an external clock the formula is:
OCiR = t * fEXT -5
Where:
●
t = Signal or pulse period (in seconds)
●
fEXT = External timer clock frequency (in Hertz)
The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 54)
Note:
106/247
1
The OCF1 and OCF2 bits cannot be set by hardware in PWM mode; therefore, the Output
Compare interrupt is inhibited.
2
The ICF1 bit is set by hardware when the counter reaches the OC2R value; it can produce a
timer interrupt if the ICIE bit is set and the I bit is cleared.
3
In PWM mode, the ICAP1 pin cannot be used to perform an input capture because it is
disconnected to the timer. The ICAP2 pin can be used to perform an input capture (ICF2 can
be set and IC2R can be loaded) but the user must take care that the counter is reset each
period, and ICF1 can also generate an interrupt if ICIE is set.
4
When the pulse-width modulation (PWM) and One-pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
11.3.4
On-chip peripherals
Low-power modes
Table 47.
Low-power mode description
Mode
11.3.5
Description
Wait
No effect on 16-bit timer.
Timer interrupts cause the Device to exit from Wait mode.
Halt
16-bit timer registers are frozen.
In Halt mode, the counter stops counting until Halt mode is exited. Counting resumes from
the previous count when the Device is woken up by an interrupt with “exit from Halt mode”
capability or from the counter reset value when the Device is woken up by a reset.
If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is
armed. Consequently, when the Device is woken up by an interrupt with “exit from Halt
mode” capability, the ICFi bit is set, and the counter value present when exiting from Halt
mode is captured into the ICiR register.
Interrupts
Table 48.
Interrupt events
Interrupt event
Input Capture 1 event/Counter reset in PWM mode
Event
flag
Enable Exit from Exit from
control bit
Wait
Halt
ICF1
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
ICIE
Input Capture 2 event
ICF2
Output Compare 1 event (not available in PWM mode)
OCF1
OCIE
Output Compare 2 event (not available in PWM mode)
Timer overflow event
Note:
OCF2
TOF
TOIE
The 16-bit timer interrupt events are connected to the same interrupt vector (see Section 8:
Interrupts). These events generate an interrupt if the corresponding Enable Control Bit is set
and the interrupt mask in the CC register is reset (RIM instruction).
Doc ID 12321 Rev 6
107/247
On-chip peripherals
ST72344xx, ST2345xx
11.3.6
Summary of timer modes
Table 49.
Timer modes
Available resources
Modes
Input Capture 1
Input Capture 2
Output Compare 1 Output Compare 2
Input Capture (1 and/or 2)
Yes
Yes
Yes
Yes
Output Compare (1 and/or 2)
Yes
Yes
Yes
Yes
One-pulse mode
No
Not recommended (1)
No
Partially (2)
PWM mode
No
Not recommended (3)
No
No
1. See note 4 in One-pulse mode.
2. See note 5 in One-pulse mode.
3. See note 4 in Pulse-width modulation mode.
11.3.7
Register description
Each timer is associated with three control and status registers, and with six pairs of data
registers (16-bit values) related to the two input captures, the two output compares, the
counter and the alternate counter.
Control register 1 (CR1)
Read/Write
Reset value: 0000 0000 (00h)
7
0
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
Read/Write
Bit 7 = ICIE Input Capture Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set.
Bit 6 = OCIE Output Compare Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is
set.
Bit 5 = TOIE Timer Overflow Interrupt Enable.
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF bit of the SR register is set.
Bit 4 = FOLV2 Forced Output Compare 2.
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even
if there is no successful comparison.
108/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Bit 3 = FOLV1 Forced Output Compare 1.
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there
is no successful comparison.
Bit 2 = OLVL2 Output Level 2.
This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the
OC2R register and OCxE is set in the CR2 register. This value is copied to the OCMP1
pin in One-pulse mode and Pulse-width modulation mode.
Bit 1 = IEDG1 Input Edge 1.
This bit determines which type of level transition on the ICAP1 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = OLVL1 Output Level 1.
The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs
with the OC1R register and the OC1E bit is set in the CR2 register.
Control register 2 (CR2)
Reset value: 0000 0000 (00h)
7
OC1E
OC2E
0
OPM
PWM
CC1
CC0
IEDG2
EXEDG
Read/Write
Bit 7 = OC1E Output Compare 1 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP1 pin (OLV1 in
Output Compare mode, both OLV1 and OLV2 in PWM and one-pulse mode). Whatever
the value of the OC1E bit, the Output Compare 1 function of the timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP1 pin alternate function enabled.
Bit 6 = OC2E Output Compare 2 Pin Enable.
This bit is used only to output the signal from the timer on the OCMP2 pin (OLV2 in
Output Compare mode). Whatever the value of the OC2E bit, the Output Compare 2
function of the timer remains active.
0: OCMP2 pin alternate function disabled (I/O pin free for general-purpose I/O).
1: OCMP2 pin alternate function enabled.
Bit 5 = OPM One-pulse Mode.
0: One-pulse Mode is not active.
1: One-pulse Mode is active, the ICAP1 pin can be used to trigger one pulse on the
OCMP1 pin; the active transition is given by the IEDG1 bit. The length of the generated
pulse depends on the contents of the OC1R register.
Bit 4 = PWM Pulse-Width Modulation.
0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a programmable cyclic signal; the
Doc ID 12321 Rev 6
109/247
On-chip peripherals
ST72344xx, ST2345xx
length of the pulse depends on the value of OC1R register; the period depends on the
value of OC2R register.
Bits 3:2 = CC[1:0] Clock Control.
The timer clock mode depends on these bits:
Table 50.
Note:
Clock control bits
Timer clock
CC1
CC0
fCPU / 4
0
0
fCPU / 2
0
1
fCPU / 8
1
0
External clock (where available)
1
1
If the external clock pin is not available, programming the external clock configuration stops
the counter.
Bit 1 = IEDG2 Input Edge 2.
This bit determines which type of level transition on the ICAP2 pin will trigger the
capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 = EXEDG External Clock Edge.
This bit determines which type of level transition on the external clock pin EXTCLK will
trigger the counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.
Control/status register (CSR)
Reset value: 0000 0000 (00h)
The three least significant bits are not used.
7
ICF1
0
OCF1
TOF
ICF2
OCF2
TIMD
0
0
Read-only
Bit 7 = ICF1 Input Capture Flag 1.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
Bit 6 = OCF1 Output Compare Flag 1.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte of the
OC1R (OC1LR) register.
110/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Bit 5 = TOF Timer Overflow Flag.
0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read
the SR register, then read or write the low byte of the CR (CLR) register.
Note:
Reading or writing the ACLR register does not clear TOF.
Bit 4 = ICF2 Input Capture Flag 2.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR
register, then read or write the low byte of the IC2R (IC2LR) register.
Bit 3 = OCF2 Output Compare Flag 2.
0: No match (reset value).
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte of the
OC2R (OC2LR) register.
Bit 2 = TIMD Timer disable.
This bit is set and cleared by software. When set, it freezes the timer prescaler and
counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce power
consumption. Access to the timer registers is still available, allowing the timer
configuration to be changed while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
Bits 1:0 = Reserved, must be kept cleared.
Input capture 1 high register (IC1HR)
Reset value: Undefined
This is an 8-bit read-only register that contains the high part of the counter value (transferred
by the input capture 1 event).
7
0
MSB
LSB
Read Only
Input capture 1 low register (IC1LR)
Reset value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the input capture 1 event).
7
0
MSB
LSB
Read Only
Doc ID 12321 Rev 6
111/247
On-chip peripherals
ST72344xx, ST2345xx
Output compare 1 high register (OC1HR)
Read/Write
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
7
0
MSB
LSB
Read/Write
Output compare 1 low register (OC1LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
7
0
MSB
LSB
Read/Write
Output compare 2 high register (OC2HR)
Reset value: 1000 0000 (80h)
This is an 8-bit register that contains the high part of the value to be compared to the CHR
register.
7
0
MSB
LSB
Read/Write
Output compare 2 low register (OC2LR)
Reset value: 0000 0000 (00h)
This is an 8-bit register that contains the low part of the value to be compared to the CLR
register.
7
0
MSB
LSB
Read/Write
Counter high register (CHR)
Reset value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part of the counter value.
7
0
MSB
LSB
Read-only
112/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Counter low register (CLR)
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register, after accessing the CSR register, clears the
TOF bit.
7
0
MSB
LSB
Read-only
Alternate counter high register (ACHR)
Reset value: 1111 1111 (FFh)
This is an 8-bit register that contains the high part of the counter value.
7
0
MSB
LSB
Read-only
Alternate counter low register (ACLR)
Reset value: 1111 1100 (FCh)
This is an 8-bit register that contains the low part of the counter value. A write to this register
resets the counter. An access to this register after an access to CSR register does not clear
the TOF bit in the CSR register.
7
0
MSB
LSB
Read-only
Input capture 2 high register (IC2HR)
Reset value: Undefined
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the Input Capture 2 event).
7
0
MSB
LSB
Read-only
Input capture 2 low register (IC2LR)
Reset value: Undefined
This is an 8-bit read only register that contains the low part of the counter value (transferred
by the Input Capture 2 event).
7
0
MSB
LSB
Read-only
Doc ID 12321 Rev 6
113/247
On-chip peripherals
Table 51.
Address
(Hex.)
114/247
ST72344xx, ST2345xx
16-bit timer register map and reset values
Register
label
7
6
5
4
3
2
1
0
IEDG1
0
OLVL1
0
Timer A: 32 CR1
ICIE
Timer B: 42 Reset value 0
OCIE
0
TOIE
0
FOLV2
0
FOLV1
0
OLVL2
0
Timer A: 31 CR2
OC1E
Timer B: 41 Reset value 0
OC2E
0
OPM
0
PWM
0
CC1
0
CC0
0
Timer A: 33 CSR
ICF1
Timer B: 43 Reset value x
OCF1
x
TOF
x
ICF2
x
OCF2
x
TIMD
0
x
x
Timer A: 34 IC1HR
MSB
Timer B: 44 Reset value x
x
x
x
x
x
x
LSB
x
Timer A: 35 IC1LR
MSB
Timer B: 45 Reset value x
x
x
x
x
x
x
LSB
x
Timer A: 36 OC1HR
MSB
Timer B: 46 Reset value 1
0
0
0
0
0
0
LSB
0
Timer A: 37 OC1LR
MSB
Timer B: 47 Reset value 0
0
0
0
0
0
0
LSB
0
MSB
Timer A: 3E OC2HR
Timer B: 4E Reset value 1
0
0
0
0
0
0
LSB
0
Timer A: 3F OC2LR
MSB
Timer B: 4F Reset value 0
0
0
0
0
0
0
LSB
0
Timer A: 38 CHR
MSB
Timer B: 48 Reset value 1
1
1
1
1
1
1
LSB
1
Timer A: 39 CLR
MSB
Timer B: 49 Reset value 1
1
1
1
1
1
0
LSB
0
Timer A: 3A ACHR
MSB
Timer B: 4A Reset value 1
1
1
1
1
1
Timer A: 3B ACLR
MSB
Timer B: 4B Reset value 1
1
1
1
1
1
Timer A: 3C IC2HR
MSB
Timer B: 4C Reset value x
x
x
x
x
Timer A: 3D IC2LR
MSB
Timer B: 4D Reset value x
x
x
x
x
Doc ID 12321 Rev 6
IEDG2 EXEDG
0
0
LSB
1
1
0
LSB
0
x
x
LSB
x
x
x
LSB
x
ST72344xx, ST2345xx
On-chip peripherals
11.4
Serial peripheral interface (SPI)
11.4.1
Introduction
The serial peripheral interface (SPI) allows full-duplex, synchronous, serial communication
with external devices. An SPI system may consist of a master and one or more slaves, or a
system in which devices may be either masters or slaves.
11.4.2
Main features
●
Full-duplex synchronous transfers (on three lines)
●
Simplex synchronous transfers (on two lines)
●
Master or slave operation
●
6 master mode frequencies (fCPU/4 max.)
●
fCPU/2 max. slave mode frequency (see the note)
●
SS Management by software or hardware
●
Programmable clock polarity and phase
●
End-of-transfer interrupt flag
●
Write collision, master mode fault and Overrun flags
Note:
In slave mode, continuous transmission is not possible at maximum frequency due to the
software overhead for clearing status flags and to initiate the next transmission sequence.
11.4.3
General description
Figure 56 on page 116 shows the serial peripheral interface (SPI) block diagram. There are
three registers:
●
SPI Control Register (SPICR)
●
SPI Control/Status Register (SPICSR)
●
SPI Data Register (SPIDR)
The SPI is connected to external devices through four pins:
●
MISO: Master In / Slave Out data
●
MOSI: Master Out / Slave In data
●
SCK: Serial Clock out by SPI masters and input by SPI slaves
●
SS: Slave select:
This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves
individually and to avoid contention on the data lines. Slave SS inputs can be driven by
standard I/O ports on the master Device.
Doc ID 12321 Rev 6
115/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 56. Serial peripheral interface block diagram
Data/Address Bus
Read
SPIDR
Interrupt
request
Read Buffer
MOSI
MISO
8-bit Shift Register
SPICSR
7
SPIF WCOL OVR MODF
SOD
bit
0
SOD SSM
0
SSI
Write
SS
SPI
STATE
CONTROL
SCK
7
SPIE
1
0
SPICR
0
SPE SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER
CONTROL
SERIAL CLOCK
GENERATOR
SS
Functional description
A basic example of interconnections between a single master and a single slave is
illustrated in Figure 57.
The MOSI pins are connected together and the MISO pins are connected together. In this
way data is transferred serially between master and slave (most significant bit first).
The communication is always initiated by the master. When the master device transmits
data to a slave device via MOSI pin, the slave device responds by sending data to the
master device via the MISO pin. This implies full duplex communication with both data out
and data in, synchronized with the same clock signal (which is provided by the master
device via the SCK pin).
To use a single data line, the MISO and MOSI pins must be connected at each node (in this
case only simplex communication is possible).
Four possible data/clock timing relationships may be chosen (see Figure 60) but master and
slave must be programmed with the same timing mode.
116/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 57. Single master/ single slave application
SLAVE
MASTER
MSBit
LSBit
MSBit
8-bit SHIFT REGISTER
SPI
CLOCK
GENERATOR
MISO
MISO
MOSI
MOSI
SCK
SS
LSBit
8-bit SHIFT REGISTER
SCK
+5V
SS
Not used if SS is managed
by software
Slave select management
As an alternative to using the SS pin to control the Slave Select signal, the application can
choose to manage the Slave Select signal by software. This is configured by the SSM bit in
the SPICSR register (see Figure 59).
In software management, the external SS pin is free for other application uses and the
internal SS signal level is driven by writing to the SSI bit in the SPICSR register.
●
In Master mode:
–
●
SS internal must be held high continuously
In Slave Mode:
There are two cases depending on the data/clock timing relationship (see Figure 58):
If CPHA = 1 (data latched on second clock edge):
–
SS internal must be held low during the entire transmission. This implies that in
single slave applications the SS pin either can be tied to VSS, or made free for
standard I/O by managing the SS function by software (SSM = 1 and SSI = 0 in
the in the SPICSR register)
If CPHA = 0 (data latched on first clock edge):
–
SS internal must be held low during byte transmission and pulled high between
each byte to allow the slave to write to the shift register. If SS is not pulled high, a
Write Collision error will occur when the slave writes to the shift register (see Write
collision error (WCOL)).
Doc ID 12321 Rev 6
117/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 58. Generic SS timing diagram
MOSI/MISO
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(if CPHA = 0)
Figure 59. Hardware/software slave select management
SSM bit
SSI bit
1
SS external pin
0
SS internal
Master mode operation
In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and
phase are configured by software (refer to the description of the SPICSR register).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
How to operate the SPI in master mode
To operate the SPI in master mode, perform the following steps in order:
1.
2.
Write to the SPICR register:
–
Select the clock frequency by configuring the SPR[2:0] bits.
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits.
Figure 60 shows the four possible configurations.
Note that the slave must have the same CPOL and CPHA settings as the master.
Write to the SPICSR register:
–
3.
Write to the SPICR register:
–
Note:
Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin
high for the complete byte transmit sequence.
Set the MSTR and SPE bits
Note that the MSTR and SPE bits remain set only if SS is high).
Important: if the SPICSR register is not written first, the SPICR register setting (MSTR bit)
may be not taken into account.
The transmit sequence begins when the software writes a byte in the SPIDR register.
118/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Master mode transmit sequence
When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MOSI pin most significant bit first.
When data transfer is complete:
●
The SPIF bit is set by hardware.
●
An interrupt request is generated if the SPIE bit is set and the interrupt mask in the
CCR register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
Note:
1.
An access to the SPICSR register while the SPIF bit is set
2.
A read to the SPIDR register
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Slave mode operation
In slave mode, the serial clock is received on the SCK pin from the master device.
To operate the SPI in slave mode:
1.
2.
Write to the SPICSR register to perform the following actions:
–
Select the clock polarity and clock phase by configuring the CPOL and CPHA bits
(see Figure 60).
Note that the slave must have the same CPOL and CPHA settings as the master.
–
Manage the SS pin as described in Slave select management and Figure 58.
If CPHA = 1, SS must be held low continuously.
If CPHA = 0, SS must be held low during byte transmission and pulled up between
each byte to let the slave write in the shift register.
Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI
I/O functions.
Slave mode transmit sequence
When the software writes to the SPIDR register, the data byte is loaded into the 8-bit shift
register and then shifted out serially to the MISO pin most significant bit first.
The transmit sequence begins when the slave device receives the clock signal and the most
significant bit of the data on its MOSI pin.
When data transfer is complete:
●
The SPIF bit is set by hardware.
●
An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR
register is cleared.
Clearing the SPIF bit is performed by the following software sequence:
1.
An access to the SPICSR register while the SPIF bit is set
2.
A write or a read to the SPIDR register
Doc ID 12321 Rev 6
119/247
On-chip peripherals
Note:
ST72344xx, ST2345xx
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
The SPIF bit can be cleared during a second transmission; however, it must be cleared
before the second SPIF bit in order to prevent an Overrun condition (see Overrun condition
(OVR)).
11.4.4
Clock phase and clock polarity
Four possible timing relationships may be chosen by software, using the CPOL and CPHA
bits (See Figure 60).
Note:
The idle state of SCK must correspond to the polarity selected in the SPICSR register (by
pulling up SCK if CPOL = 1 or pulling down SCK if CPOL = 0).
The combination of the CPOL clock polarity and CPHA (clock phase) bits selects the data
capture clock edge.
Figure 60 shows an SPI transfer with the four combinations of the CPHA and CPOL bits.
The diagram may be interpreted as a master or slave timing diagram where the SCK pin, the
MISO pin and the MOSI pin are directly connected between the master and the slave
device.
Note:
120/247
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 60. Data clock timing diagram
CPHA = 1
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
CPHA = 0
SCK
(CPOL = 1)
SCK
(CPOL = 0)
MISO
(from master)
MOSI
(from slave)
MSBit
MSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
Bit 6
Bit 5
Bit 4
Bit3
Bit 2
Bit 1
LSBit
SS
(to slave)
CAPTURE STROBE
1. This figure should not be used as a replacement for parametric information. Refer to Section 13: Electrical
characteristics.
11.4.5
Error flags
Master mode fault (MODF)
Master mode fault occurs when the master device’s SS pin is pulled low.
When a Master mode fault occurs:
●
The MODF bit is set and an SPI interrupt request is generated if the SPIE bit is set.
●
The SPE bit is reset. This blocks all output from the device and disables the SPI
peripheral.
●
The MSTR bit is reset, thus forcing the device into slave mode.
Doc ID 12321 Rev 6
121/247
On-chip peripherals
ST72344xx, ST2345xx
Clearing the MODF bit is done through a software sequence:
Note:
1.
A read access to the SPICSR register while the MODF bit is set.
2.
A write ac cess to the SPICR register.
To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high
during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their
original state during or after this clearing sequence.
The hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is
set, except in the MODF bit clearing sequence.
In a slave device, the MODF bit can not be set, but in a multimaster configuration the device
can be in slave mode with the MODF bit set.
The MODF bit indicates that there might have been a multimaster conflict and allows
software to handle this using an interrupt routine and either perform a reset or return to an
application default state.
Overrun condition (OVR)
An overrun condition occurs when the master device has sent a data byte and the slave
device has not cleared the SPIF bit issued from the previously transmitted byte.
When an Overrun occurs:
●
The OVR bit is set, and an interrupt request is generated if the SPIE bit is set.
In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A
read to the SPIDR register returns this byte. All other bytes are lost.
The OVR bit is cleared by reading the SPICSR register.
Write collision error (WCOL)
A write collision occurs when the software tries to write to the SPIDR register while a data
transfer is taking place with an external device. When this happens, the transfer continues
uninterrupted and the software write will be unsuccessful.
Write collisions can occur both in master and slave mode. See also Slave select
management.
Note:
A “read collision” will never occur since the received data byte is placed in a buffer in which
access is always synchronous with the CPU operation.
The WCOL bit in the SPICSR register is set if a write collision occurs.
No SPI interrupt is generated when the WCOL bit is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software sequence (see Figure 61).
122/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 61. Clearing the WCOL bit (write collision flag) software sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SPICSR
2nd Step
Read SPIDR
RESULT
SPIF = 0
WCOL = 0
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
Read SPICSR
RESULT
2nd Step
Read SPIDR
WCOL = 0
1. Writing to the SPIDR register instead of reading it does not reset the WCOL bit.
Single master and multimaster configurations
There are two types of SPI systems: Single master system and Multimaster system.
●
Single master system
A typical single master system may be configured using a device as the master and
four devices as slaves (see Figure 62).
The master device selects the individual slave devices by using four pins of a parallel
port to control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports will be forced to
be inputs at that time, thus disabling the slave devices.
Note: To prevent a bus conflict on the MISO line, the master allows only one active
slave device during a transmission.
For more security, the slave device may respond to the master with the received data
byte. Then the master will receive the previous byte back from the slave device if all
MISO and MOSI pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes
with command fields.
●
Multimaster system
A multimaster system may also be configured by the user. Transfer of master control
could be implemented using a handshake method through the I/O ports or by an
exchange of code messages through the serial peripheral interface system.
The multimaster system is principally handled by the MSTR bit in the SPICR register,
and the MODF bit in the SPICSR register.
Doc ID 12321 Rev 6
123/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 62. Single master / multiple slave configuration
SS
SCK
SS
SS
SCK
Slave
Device
Slave
Device
MOSI MISO
MOSI
MISO
SS
SCK
Slave
Device
SCK
Slave
Device
MOSI
MOSI
MISO
MISO
SCK
Master
Device
5V
11.4.6
Ports
MOSI MISO
SS
Low-power modes
Table 52.
Mode
Description
Description
Wait
No effect on SPI.
SPI interrupt events cause the device to exit from Wait mode.
Halt
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI operation resumes when the device is woken up by
an interrupt with “exit from Halt mode” capability. The data received is subsequently read
from the SPIDR register when the software is running (interrupt vector fetching). If several
data are received before the wake-up event, then an overrun error is generated. This error
can be detected after the fetch of the interrupt routine that woke up the Device.
Using the SPI to wake up the device from Halt mode
In slave configuration, the SPI is able to wake up the device from Halt mode through a SPIF
interrupt. The data received is subsequently read from the SPIDR register when the
software is running (interrupt vector fetch). If multiple data transfers have been performed
before software clears the SPIF bit, then the OVR bit is set by hardware.
Note:
When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to
perform an extra communications cycle to bring the SPI from Halt mode state to normal
state. If the SPI exits from Slave mode, it returns to normal state immediately.
Caution:
The SPI can wake up the device from Halt mode only if the Slave Select signal (external SS
pin or the SSI bit in the SPICSR register) is low when the device enters Halt mode. So, if
Slave selection is configured as external (see Slave select management), make sure the
master drives a low level on the SS pin when the slave enters Halt mode.
124/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
11.4.7
On-chip peripherals
Interrupts
Table 53.
Interrupt events
Interrupt event
Enable control
bit
Event flag
SPI end of transfer event
SPIF
Master mode fault event
MODF
Exit from Wait
Exit from Halt
Yes
SPIE
Yes
No
Overrun error
OVR
Note:
The SPI interrupt events are connected to the same interrupt vector (see Section 8:
Interrupts).
They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).
11.4.8
Register description
SPI control register (SPICR)
Reset value: 0000 xxxx (0xh)
7
SPIE
SPE
0
SPR2
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
Bit 7 = SPIE Serial Peripheral Interrupt Enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault
or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)
Bit 6 = SPE Serial Peripheral Output Enable
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see Master mode fault (MODF)). The SPE bit is cleared by reset, so the
SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
Bit 5 = SPR2 Divider Enable
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to Table 54: SPI master mode SCK frequency.
0: Divider by 2 enabled
1: Divider by 2 disabled
Note:
This bit has no effect in slave mode.
Doc ID 12321 Rev 6
125/247
On-chip peripherals
ST72344xx, ST2345xx
Bit 4 = MSTR Master Mode
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see Master mode fault (MODF)).
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
Bit 3 = CPOL Clock Polarity
This bit is set and cleared by software. This bit determines the idle state of the serial
Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
Note:
If CPOL is changed at the communication byte boundaries, the SPI must be disabled by
resetting the SPE bit.
Bit 2 = CPHA Clock Phase
This bit is set and cleared by software.
0: The first clock transition is the first data capture edge.
1: The second clock transition is the first capture edge.
Note:
The slave must have the same CPOL and CPHA settings as the master.
Bits 1:0 = SPR[1:0] Serial clock frequency
These bits are set and cleared by software. Used with the SPR2 bit, they select the
baud rate of the SPI serial clock SCK output by the SPI in master mode.
Note:
These 2 bits have no effect in slave mode.
Table 54.
SPI master mode SCK frequency
Serial clock
SPR2
fCPU/4
1
SPR1
SPR0
0
fCPU/8
0
0
fCPU/16
1
fCPU/32
1
0
fCPU/64
1
0
fCPU/128
1
SPI control/status register (SPICSR)
Reset value: 0000 0000 (00h)
7
SPIF
WCOL
OVR
Read-only
126/247
0
MODF
Reserved
Doc ID 12321 Rev 6
SOD
SSM
Read/Write
SSI
ST72344xx, ST2345xx
On-chip peripherals
Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read-only)
This bit is set by hardware when a transfer has been completed. An interrupt is
generated if SPIE = 1 in the SPICR register. It is cleared by a software sequence (an
access to the SPICSR register followed by a write or a read to the SPIDR register).
0: Data transfer is in progress or the flag has been cleared.
1: Data transfer between the device and an external device has been completed.
Note:
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Bit 6 = WCOL Write collision status (Read-only)
This bit is set by hardware when a write to the SPIDR register is done during a transmit
sequence. It is cleared by a software sequence (see Figure 61).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = OVR SPI overrun error (Read-only)
This bit is set by hardware when the byte currently being received in the shift register is
ready to be transferred into the SPIDR register while SPIF = 1 (See Overrun condition
(OVR)). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is
cleared by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 = MODF Mode fault flag (Read-only)
This bit is set by hardware when the SS pin is pulled low in master mode (see Master
mode fault (MODF)). An SPI interrupt can be generated if SPIE = 1 in the SPICR
register. This bit is cleared by a software sequence (An access to the SPICSR register
while MODF = 1 followed by a write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bit 3 = Reserved, must be kept cleared.
Bit 2 = SOD SPI Output disable
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI output (MOSI in master mode / MISO in slave mode)
0: SPI output enabled (if SPE = 1)
1: SPI output disabled
Bit 1 = SSM SS management
This bit is set and cleared by software. When set, it disables the alternate function of
the SPI SS pin and uses the SSI bit value instead. See Slave select management.
0: Hardware management (SS managed by external pin)
1: Software management (internal SS signal controlled by SSI bit. External SS pin free
for general-purpose I/O)
Bit 0 = SSI SS internal mode
This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of
the SS slave select signal when the SSM bit is set.
0: Slave selected
1: Slave deselected
Doc ID 12321 Rev 6
127/247
On-chip peripherals
ST72344xx, ST2345xx
SPI data I/O register (SPIDR)
Reset value: Undefined
7
D7
D6
0
D5
D4
D3
D2
D1
D0
Read/Write
The SPIDR register is used to transmit and receive data on the serial bus. In a master
device, a write to this register will initiate transmission/reception of another byte.
Note:
During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read.
While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR
register is read.
Warning:
A write to the SPIDR register places data directly into the
shift register for transmission.
A read to the SPIDR register returns the value located in the buffer and not the content of
the shift register (see Figure 56).
Table 55.
Address
(Hex.)
128/247
SPI register map and reset values
Register
label
7
6
5
4
3
2
1
0
x
x
x
x
LSB
x
0021h
MSB
SPIDR
Reset value x
x
x
0022h
SPICR
SPIE
Reset value 0
SPE
0
SPR2
0
MSTR
0
CPOL
x
CPHA
x
SPR1
x
SPR0
x
0023h
SPICSR
SPIF
Reset value 0
WCOL
0
OR
0
MODF
0
0
SOD
0
SSM
0
SSI
0
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
11.5
SCI serial communication interface
11.5.1
Introduction
The serial communications interface (SCI) offers a flexible means of full-duplex data
exchange with external equipment requiring an industry standard NRZ asynchronous serial
data format. The SCI offers a very wide range of baud rates using two baud rate generator
systems.
11.5.2
Main features
●
Full-duplex, asynchronous communications
●
NRZ standard format (Mark/Space)
●
Dual baud rate generator systems
●
Independently programmable transmit and receive baud rates up to 500,000 baud
●
Programmable data word length (8 or 9 bits)
●
Receive buffer full, Transmit buffer empty and End of Transmission flags
●
2 receiver wake-up modes:
Address bit (MSB)
–
Idle line
●
Muting function for multiprocessor configurations
●
Separate enable bits for Transmitter and Receiver
●
4 error detection flags:
●
●
●
11.5.3
–
–
Overrun error
–
Noise error
–
Frame error
–
Parity error
5 interrupt sources with flags:
–
Transmit data register empty
–
Transmission complete
–
Receive data register full
–
Idle line received
–
Overrun error detected
Parity control:
–
Transmits parity bit
–
Checks parity of received data byte
Reduced power consumption mode
General description
The interface is externally connected to another device by three pins (see Figure 63). Any
SCI bidirectional communication requires a minimum of two pins: Receive Data In (RDI) and
Transmit Data Out (TDO):
●
SCLK: Transmitter clock output. This pin outputs the transmitter data clock for
synchronous transmission (no clock pulses on start bit and stop bit, and a software
option to send a clock pulse on the last data bit). This can be used to control
Doc ID 12321 Rev 6
129/247
On-chip peripherals
ST72344xx, ST2345xx
peripherals that have shift registers (e.g. LCD drivers). The clock phase and polarity
are software programmable.
●
TDO: Transmit Data Output. When the transmitter is disabled, the output pin returns to
its I/O port configuration. When the transmitter is enabled and nothing is to be
transmitted, the TDO pin is at high level.
●
RDI: Receive Data Input is the serial data input. Oversampling techniques are used for
data recovery by discriminating between valid incoming data and noise.
Through these pins, serial data is transmitted and received as frames comprising:
●
An Idle Line prior to transmission or reception
●
A start bit
●
A data word (8 or 9 bits) least significant bit first
●
A Stop bit indicating that the frame is complete.
This interface uses two types of baud rate generator:
130/247
●
A conventional type for commonly-used baud rates,
●
An extended type with a prescaler offering a very wide range of baud rates, even with
non-standard oscillator frequencies.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 63. SCI block diagram
Write
Read
(DATA REGISTER) SCIDR
Receive Data Register (RDR)
Transmit Data Register (TDR)
TDO
Receive Shift Register
Transmit Shift Register
RDI
R8
TRANSMIT
WAKE
UP
CONTROL
UNIT
T8
SCID
M
WAKE PCE
PS
SCICR1
PIE
RECEIVER
CLOCK
RECEIVER
CONTROL
SCISR
SCICR2
TIE TCIE RIE
ILIE
TE
TDRE TC RDRF IDLE OR
RE RWU SBK
NF
FE
PE
SCI
INTERRUPT
CONTROL
TRANSMITTER
CLOCK
TRANSMITTER RATE
fCPU
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
Doc ID 12321 Rev 6
131/247
On-chip peripherals
11.5.4
ST72344xx, ST2345xx
Functional description
The block diagram of the Serial Control Interface, is shown in Figure 63. It contains six
dedicated registers:
●
2 control registers (SCICR1 and SCICR2)
●
A status register (SCISR)
●
A baud rate register (SCIBRR)
●
An extended prescaler receiver register
(SCIERPR)
●
An extended prescaler transmitter register
(SCIETPR)
Refer to the register descriptions in Section 11.5.7 for the definitions of each bit.
Serial data format
Word length may be selected as being either 8 or 9 bits by programming the M bit in the
SCICR1 register (see Figure 64).
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame of “1”s followed by the start bit of the next
frame which contains data.
A Break character is interpreted on receiving “0”s for some multiple of the frame period. At
the end of the last break frame the transmitter inserts an extra “1” bit to acknowledge the
start bit.
Transmission and reception are driven by their own baud rate generator.
132/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 64. Word length programming
9-bit (M bit is set)
Possible
Parity
Bit
Data Frame
Start
Bit
Bit0
Bit2
Bit1
Bit3
Bit4
Bit5
Bit6
Bit7
Bit8
CLOCK
Next Data Frame
Next
Stop Start
Bit
Bit
(1)
Idle Frame
Start
Bit
Break Frame
Extra
’1’
Start
Bit
8-bit (M bit is reset)
Possible
Parity
Bit
Data Frame
Start
Bit
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
CLOCK
Bit6
Bit7
Next Data Frame
Stop
Bit
Next
Start
Bit
****
(1)
Idle Frame
Start
Bit
Break Frame
Extra Start
Bit
’1’
1. LBCL bit controls last data clock pulse.
Transmitter
The transmitter can send data words of either 8 or 9 bits depending on the M bit status.
When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the
T8 bit in the SCICR1 register.
When the transmit enable bit (TE) is set, the data in the transmit shift register is output on
the TDO pin.
Doc ID 12321 Rev 6
133/247
On-chip peripherals
ST72344xx, ST2345xx
Character transmission
During an SCI transmission, data shifts out least significant bit first on the TDO pin. In
this mode, the SCIDR register consists of a buffer (TDR) between the internal bus and
the transmit shift register (see Figure 64).
Procedure:
–
Select the M bit to define the word length.
–
Select the desired baud rate using the SCIBRR and the SCIETPR registers.
–
Set the TE bit to send an idle frame as first transmission.
–
Access the SCISR register and write the data to send in the SCIDR register (this
sequence clears the TDRE bit). Repeat this sequence for each data to be
transmitted.
Clearing the TDRE bit is always performed by the following software sequence:
a)
An access to the SCISR register
b)
A write to the SCIDR register
The TDRE bit is set by hardware and it indicates:
–
The TDR register is empty.
–
The data transfer is beginning.
–
The next data can be written in the SCIDR register without overwriting the
previous data.
This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR
register.
When a transmission is taking place, a write instruction to the SCIDR register stores
the data in the TDR register and which is copied in the shift register at the end of the
current transmission.
When no transmission is taking place, a write instruction to the SCIDR register places
the data directly in the shift register; the data transmission starts, and the TDRE bit is
immediately set.
When a frame transmission is complete (after the stop bit or after the break frame) the
TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the
CCR register.
Clearing the TC bit is performed by the following software sequence:
Note:
a)
An access to the SCISR register
b)
A write to the SCIDR register
The TDRE and TC bits are cleared by the same software sequence.
Break characters
Setting the SBK bit loads the shift register with a break character. The break frame
length depends on the M bit (see Figure 64).
As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing
this bit by software the SCI insert a logic 1 bit at the end of the last break frame to
guarantee the recognition of the start bit of the next frame.
Idle characters
Setting the TE bit drives the SCI to send an idle frame before the first data frame.
Clearing and then setting the TE bit during a transmission sends an idle frame after the
current word.
134/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Note:
On-chip peripherals
Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore,
the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next
byte in the SCIDR.
Receiver
The SCI can receive data words of either 8 or 9 bits. When the M bit is set, the word length
is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.
Character reception
During a SCI reception, data shifts in least significant bit first through the RDI pin. In
this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and
the received shift register (see Figure 63).
Procedure:
–
Select the M bit to define the word length.
–
Select the desired baud rate using the SCIBRR and the SCIERPR registers.
–
Set the RE bit, this enables the receiver which begins searching for a start bit.
When a character is received:
–
The RDRF bit is set. It indicates that the content of the shift register is transferred
to the RDR.
–
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR
register.
–
The error flags can be set if a frame error, noise or an overrun error has been
detected during reception.
Clearing the RDRF bit is performed by the following software sequence done by:
a)
An access to the SCISR register
b)
A read to the SCIDR register.
The RDRF bit must be cleared before the end of the reception of the next character to
avoid an overrun error.
Break character
When a break character is received, the SCI handles it as a framing error.
Idle character
When an idle frame is detected, there is the same procedure as a data received
character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR
register.
Doc ID 12321 Rev 6
135/247
On-chip peripherals
ST72344xx, ST2345xx
Overrun error
An overrun error occurs when a character is received and RDRF has not been reset.
Data cannot be transferred from the shift register to the RDR register until the RDRF bit
is cleared.
When a overrun error occurs:
–
The OR bit is set.
–
The RDR content is not lost.
–
The shift register is overwritten.
–
An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR
register.
The OR bit is reset by an access to the SCISR register followed by a SCIDR register
read operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise.
Normal data bits are considered valid if three consecutive samples (8th, 9th, 10th) have
the same bit value, otherwise the NF flag is set. In the case of start bit detection, the NF
flag is set on the basis of an algorithm combining both valid edge detection and three
samples (8th, 9th, 10th). Therefore, to prevent the NF flag getting set during start bit
reception, there should be a valid edge detection as well as three valid samples.
When noise is detected in a frame:
–
The NF flag is set at the rising edge of the RDRF bit.
–
Data is transferred from the Shift register to the SCIDR register.
–
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The NF flag is reset by a SCISR register read operation followed by a SCIDR register
read operation.
During reception, if a false start bit is detected (e.g. 8th, 9th, 10th samples are
011,101,110), the frame is discarded and the receiving sequence is not started for this
frame. There is no RDRF bit set for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible along with the RDRF bit when a next
valid frame is received.
Note:
If the application Start Bit is not long enough to match the above requirements, then the NF
flag may get set due to the short Start Bit. In this case, the NF flag may be ignored by the
application software when the first valid byte is received.
See also Noise error causes.
136/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Framing error
A framing error is detected when:
–
The stop bit is not recognized on reception at the expected time, following either a
de-synchronization or excessive noise.
–
A break is received.
When the framing error is detected:
–
the FE bit is set by hardware
–
Data is transferred from the Shift register to the SCIDR register.
–
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
The FE bit is reset by a SCISR register read operation followed by an SCIDR register
read operation.
Figure 65. SCI baud rate and extended prescaler block diagram
EXTENDED PRESCALER TRANSMITTER RATE CONTROL
TRANSMITTER
CLOCK
SCIETPR
EXTENDED TRANSMITTER PRESCALER REGISTER
SCIERPR
EXTENDED RECEIVER PRESCALER REGISTER
RECEIVER
CLOCK
EXTENDED PRESCALER RECEIVER RATE CONTROL
EXTENDED PRESCALER
fCPU
TRANSMITTER RATE
CONTROL
/16
/PR
SCIBRR
SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1SCR0
RECEIVER RATE
CONTROL
CONVENTIONAL BAUD RATE GENERATOR
Doc ID 12321 Rev 6
137/247
On-chip peripherals
ST72344xx, ST2345xx
Conventional baud rate generation
The baud rates for the receiver and transmitter (Rx and Tx) are set independently and
calculated as follows:
:
Tx =
fCPU
(16*PR)*TR
Rx =
fCPU
(16*PR)*RR
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If fCPU is 8 MHz (normal mode) and if PR = 13 and TR = RR = 1, the transmit and
receive baud rates are 38400 baud.
Note:
The baud rate registers MUST NOT be changed while the transmitter or the receiver is
enabled.
Extended baud rate generation
The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value
prescaler, whereas the conventional Baud Rate Generator retains industry standard
software compatibility.
The extended baud rate generator block diagram is shown in Figure 65.
The output clock rate sent to the transmitter or to the receiver is the output from the 16
divider divided by a factor ranging from 1 to 255 set in the SCIERPR or the SCIETPR
register.
Note:
The extended prescaler is activated by setting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as follows:
fCPU
fCPU
Rx =
Tx =
16*ERPR*(PR*RR)
16*ETPR*(PR*TR)
with:
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
Receiver muting and wakeup feature
In multiprocessor configurations, it is often desirable that only the intended message
recipient should actively receive the full message contents, thus reducing redundant SCI
service overhead for all non addressed receivers.
The non-addressed devices may be placed in sleep mode by means of the muting function.
138/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Setting the RWU bit by software puts the SCI in sleep mode:
●
None of the reception status bits can be set.
●
All the receive interrupts are inhibited.
A muted receiver can be woken up in one of the following two ways:
●
by Idle Line detection if the WAKE bit is reset,
●
by Address Mark detection if the WAKE bit is set.
A receiver wakes-up by Idle Line detection when the Receive line has recognized an Idle
Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.
A receiver wakes up by Address Mark detection when it received a “1” as the most
significant bit of a word, thus indicating that the message is an address. The reception of
this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which
allows the receiver to receive this word normally and to use it as an address word.
Parity control
Parity control (generation of parity bit in transmission and parity checking in reception) can
be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length
defined by the M bit, the possible SCI frame formats are as listed in Table 56.
Table 56.
Frame formats
M bit
0
SCI frame(1)
PCE bit
0
| SB | 8 bit data | STB |
1
| SB | 7-bit data | PB | STB |
0
| SB | 9-bit data | STB |
1
| SB | 8-bit data PB | STB |
1
1. SB: Start Bit, STB: Stop Bit, PB: Parity Bit.
Note:
In case of wakeup by an address mark, the MSB bit of the data is taken into account and not
the parity bit
Even parity: The parity bit is calculated to obtain an even number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).
Odd parity: The parity bit is calculated to obtain an odd number of “1s” inside the frame
made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.
Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).
Transmission mode: If the PCE bit is set, then the MSB bit of the data written in the data
register is not transmitted but is changed by the parity bit.
Reception mode: If the PCE bit is set, then the interface checks if the received data byte
has an even number of “1s” if even parity is selected (PS = 0) or an odd number of “1s” if
odd parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR
register and an interrupt is generated if PIE is set in the SCICR1 register.
Doc ID 12321 Rev 6
139/247
On-chip peripherals
ST72344xx, ST2345xx
SCI clock tolerance
During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th
samples is considered as the bit value. For a valid bit detection, all the three samples should
have the same value otherwise the noise flag (NF) is set. For example: if the 8th, 9th and
10th samples are 0, 1 and 1 respectively, then the bit value is “1”, but the Noise Flag bit is
set because the three samples values are not the same.
Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples
have the desired bit value. This means the clock frequency should not vary more than 6/16
(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when
receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed
3.75%.
Note:
The internal sampling clock of the microcontroller samples the pin value on every falling
edge. Therefore, the internal sampling clock and the time the application expects the
sampling to take place may be out of sync. For example: If the baud rate is 15.625 kbaud (bit
length is 64 µs), then the 8th, 9th and 10th samples will be at 28 µs, 32 µs and 36 µs
respectively (the first sample starting ideally at 0 µs). But if the falling edge of the internal
clock occurs just before the pin value changes, the samples would then be out of sync by
~4 µs. This means the entire bit length must be at least 40 µs (36 µs for the 10th sample
+ 4 µs for synchronization with the internal sampling clock).
Clock deviation causes
The causes which contribute to the total deviation are:
●
DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or the
transmitter is transmitting at a different baud rate).
●
DQUANT: Error due to the baud rate quantization of the receiver.
●
DREC: Deviation of the local oscillator of the receiver: This deviation can occur during
the reception of one complete SCI message assuming that the deviation has been
compensated at the beginning of the message.
●
DTCL: Deviation due to the transmission line (generally due to the transceivers)
All the deviations of the system should be added and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
Noise error causes
See also description of noise error in Receiver.
●
Start bit: the noise flag (NF) is set during start bit reception if one of the following
conditions occurs:
–
140/247
A valid falling edge is not detected. A falling edge is considered to be valid if the
three consecutive samples before the falling edge occurs are detected as '1' and,
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
after the falling edge occurs, during the sampling of the 16 samples, if one of the
samples numbered 3, 5 or 7 is detected as a “1”.
–
During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is
detected as a “1”.
●
Therefore, a valid Start bit must satisfy both the above conditions to prevent the Noise
Flag getting set.
●
Data bits: the noise flag (NF) is set during normal data bit reception if the following
condition occurs:
–
During the sampling of 16 samples, if all three samples numbered 8, 9 and 10 are
not the same. The majority of the 8th, 9th and 10th samples is considered as the
bit value.
Therefore, a valid Data bit must have samples 8, 9 and 10 at the same value to prevent the
Noise Flag getting set.
Figure 66. Bit sampling in reception mode
RDI LINE
sampled values
Sample
clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6/16
7/16
7/16
One bit time
11.5.5
Low-power modes
Table 57.
Mode description
Mode
Description
Wait
No effect on SCI.
SCI interrupts cause the device to exit from Wait mode.
Halt
SCI registers are frozen.
In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.
Doc ID 12321 Rev 6
141/247
On-chip peripherals
11.5.6
ST72344xx, ST2345xx
Interrupts
Table 58.
Interrupt events
Interrupt event
Enable control
bit
Event flag
Transmit data register empty
TDRE
TIE
Transmission complete
TC
TCIE
Received data ready to be read
RDRF
Overrun error detected
OR
Idle line detected
IDLE
ILIE
Parity error
PE
PIE
RIE
Exit from
Wait
Yes
Exit from
Halt
No
The SCI interrupt events are connected to the same interrupt vector.
These events generate an interrupt if the corresponding Enable Control Bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
11.5.7
Register description
Status register (SCISR)
Reset value: 1100 0000 (C0h)
7
TDRE
0
TC
RDRF
IDLE
OR
NF
FE
PE
Read-only
Bit 7 = TDRE Transmit data register empty.
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE bit = 1 in the SCICR2 register.
It is cleared by a software sequence (an access to the SCISR register followed by a
write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Note:
Data is not transferred to the shift register until the TDRE bit is cleared.
Bit 6 = TC Transmission complete.
This bit is set by hardware when transmission of a frame containing Data is complete.
An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note:
TC is not set after the transmission of a Preamble or a Break.
Bit 5 = RDRF Received data ready flag.
This bit is set by hardware when the content of the RDR register has been transferred
to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is
142/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
cleared by a software sequence (an access to the SCISR register followed by a read to
the SCIDR register).
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE Idle line detect.
This bit is set by hardware when an Idle Line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to
the SCISR register followed by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note:
The IDLE bit is not set again until the RDRF bit has been set itself (that is, a new idle line
occurs).
Bit 3 = OR Overrun error.
This bit is set by hardware when the word currently being received in the shift register is
ready to be transferred into the RDR register while RDRF = 1. An interrupt is generated
if RIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to
the SCISR register followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error is detected
Note:
When this bit is set, the RDR register content is not lost but the shift register is overwritten.
Bit 2 = NF Noise flag.
This bit is set by hardware when noise is detected on a received frame. It is cleared by
a software sequence (an access to the SCISR register followed by a read to the SCIDR
register).
0: No noise is detected
1: Noise is detected
Note:
This bit does not generate interrupt as it appears at the same time as the RDRF bit which
itself generates an interrupt.
Bit 1 = FE Framing error.
This bit is set by hardware when a desynchronization, excessive noise or a break
character is detected. It is cleared by a software sequence (an access to the SCISR
register followed by a read to the SCIDR register).
0: No Framing error is detected
1: Framing error or break character is detected
Note:
This bit does not generate an interrupt as it appears at the same time as the RDRF bit which
itself generates an interrupt. If the word currently being transferred causes both frame error
and overrun error, it is transferred and only the OR bit is set.
Bit 0 = PE Parity error.
This bit is set by hardware when a parity error occurs in receiver mode. It is cleared by
a software sequence (a read to the status register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1 in the SCICR1 register.
0: No parity error
1: Parity error
Doc ID 12321 Rev 6
143/247
On-chip peripherals
ST72344xx, ST2345xx
Control register 1 (SCICR1)
Reset value: x000 0000 (x0h)
7
R8
0
T8
SCID
M
WAKE
PCE
PS
PIE
Read/Write
Bit 7 = R8 Receive data bit 8.
This bit is used to store the 9th bit of the received word when M = 1.
Bit 6 = T8 Transmit data bit 8.
This bit is used to store the 9th bit of the transmitted word when M = 1.
Bit 5 = SCID Disabled for low power consumption
When this bit is set the SCI prescalers and outputs are stopped and the end of the
current byte transfer in order to reduce power consumption.This bit is set and cleared
by software.
0: SCI enabled
1: SCI prescaler and outputs disabled
Bit 4 = M Word length.
This bit determines the word length. It is set or cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit
Note:
The M bit must not be modified during a data transfer (both transmission and reception).
Bit 3 = WAKE Wakeup method.
This bit determines the SCI Wake-Up method, it is set or cleared by software.
0: Idle Line
1: Address Mark
Bit 2 = PCE Parity control enable.
This bit selects the hardware parity control (generation and detection). When the parity
control is enabled, the computed parity is inserted at the MSB position (9th bit if M = 1;
8th bit if M = 0) and parity is checked on the received data. This bit is set and cleared
by software. Once it is set, PCE is active after the current byte (in reception and in
transmission).
0: Parity control disabled
1: Parity control enabled
Bit 1 = PS Parity selection.
This bit selects the odd or even parity when the parity generation/detection is enabled
(PCE bit set). It is set and cleared by software. The parity is selected after the current
byte.
0: Even parity
1: Odd parity
144/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Bit 0 = PIE Parity interrupt enable.
This bit enables the interrupt capability of the hardware parity control when a parity
error is detected (PE bit set). It is set and cleared by software.
0: Parity error interrupt disabled
1: Parity error interrupt enabled
Control register 2 (SCICR2)
Reset value: 0000 0000 (00h)
7
TIE
0
TCIE
RIE
ILIE
TE
RE
RWU
SBK
Read/Write
Bit 7 = TIE Transmitter interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TDRE = 1 in the SCISR register
Bit 6 = TCIE Transmission complete interrupt enable
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever TC = 1 in the SCISR register
Bit 5 = RIE Receiver interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever OR = 1 or RDRF = 1 in the SCISR register
Bit 4 = ILIE Idle line interrupt enable.
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE = 1 in the SCISR register.
Bit 3 = TE Transmitter enable.
This bit enables the transmitter. It is set and cleared by software.
0: Transmitter is disabled
1: Transmitter is enabled
Note:
During transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble (idle
line) after the current word.
When TE is set there is a 1 bit-time delay before the transmission starts.
Bit 2 = RE Receiver enable.
This bit enables the receiver. It is set and cleared by software.
0: Receiver is disabled
1: Receiver is enabled and begins searching for a start bit
Doc ID 12321 Rev 6
145/247
On-chip peripherals
ST72344xx, ST2345xx
Bit 1 = RWU Receiver wake-up.
This bit determines if the SCI is in mute mode or not. It is set and cleared by software
and can be cleared by hardware when a wake-up sequence is recognized.
0: Receiver in active mode
1: Receiver in mute mode
Note:
Before selecting Mute mode (by setting the RWU bit), the SCI must first receive a data byte;
otherwise, it cannot function in Mute mode with wake-up by Idle line detection.
In Address Mark Detection Wake-Up configuration (WAKE bit = 1), the RWU bit cannot be
modified by software while the RDRF bit is set.
Bit 0 = SBK Send break.
This bit set is used to send break characters. It is set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted
Note:
If the SBK bit is set to “1” and then to “0”, the transmitter sends a BREAK word at the end of
the current word.
Data register (SCIDR)
Reset value: Undefined
Contains the Received or Transmitted data character, depending on whether it is read from
or written to.
7
DR7
0
DR6
DR5
DR4
DR3
DR2
DR1
DR0
Read/Write
The Data register performs a double function (read and write) since it is composed of two
registers, one for transmission (TDR) and one for reception (RDR).
The TDR register provides the parallel interface between the internal bus and the output
shift register (see Figure 63).
The RDR register provides the parallel interface between the input shift register and the
internal bus (see Figure 63).
Baud rate register (SCIBRR)
Reset value: 0000 0000 (00h)
7
SCP1
0
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
Read/Write
Bits 7:6 = SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard clock division ranges as shown in Figure 59.
146/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Table 59.
On-chip peripherals
SCP[1:0] configuration
PR prescaling factor
SCP1
SCP0
1
0
0
3
1
4
0
1
13
1
Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division
applied to the bus clock to yield the transmit rate clock in conventional baud rate
Generator mode.
Table 60.
SCT[2:0] configuration
TR dividing factor
SCT2
SCT1
1
SCT0
0
0
2
1
0
4
0
1
8
1
0
16
0
32
1
1
64
0
1
128
Note:
1
This TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR
is replaced by the (TR*ETPR) dividing factor.
Bits 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 and SCP0 bits, define the total division
applied to the bus clock to yield the receive rate clock in conventional Baud Rate
Generator mode.
Table 61.
SCR[2:0] configuration
RR dividing factor
SCR2
SCR1
1
SCR0
0
0
2
1
0
4
0
1
8
1
0
16
0
32
1
1
64
0
1
128
1
Doc ID 12321 Rev 6
147/247
On-chip peripherals
Note:
ST72344xx, ST2345xx
This RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR
is replaced by the (RR*ERPR) dividing factor.
Extended receive prescaler division register (SCIERPR)
Reset value: 0000 0000 (00h)
7
ERPR7
0
ERPR6
ERPR5
ERPR4
ERPR3
ERPR2
ERPR1
ERPR0
Read/Write
Bits 7:0 = ERPR[7:0] 8-bit Extended Receive Prescaler Register.
The extended Baud Rate Generator is activated when a value other than 00h is stored
in this register. The clock frequency from the 16 divider (see Figure 65) is divided by the
binary factor set in the SCIERPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
Extended transmit prescaler division register (SCIETPR)
Reset value:0000 0000 (00h)
7
ETPR7
ETPR6
0
ETPR5
ETPR4
ETPR3
ETPR2
ETPR1
ETPR0
Read/Write
Bits 7:0 = ETPR[7:0] 8-bit extended transmit prescaler register.
The extended Baud Rate Generator is activated when a value other than 00h is stored
in this register. The clock frequency from the 16 divider (see Figure 65) is divided by the
binary factor set in the SCIETPR register (in the range 1 to 255).
The extended baud rate generator is not active after a reset.
Table 62.
Baud rate selection
Conditions
Symbol
Parameter
fCPU
fTx
fRx
Communication
frequency
Accuracy
vs.
Standard
Prescaler
~0.16%
Conventional Mode
TR (or RR) = 128,
PR = 13
TR (or RR) = 32, PR = 13
TR (or RR) = 16, PR =13
TR (or RR) = 8, PR = 13
TR (or RR) = 4, PR = 13
TR (or RR) = 16, PR = 3
TR (or RR) = 2, PR = 13
TR (or RR) = 1, PR = 13
8 MHz
~0.79%
148/247
Extended Mode
ETPR (or ERPR) = 35,
TR (or RR) = 1, PR = 1
Doc ID 12321 Rev 6
Standard
Baud
Rate
300
1200
2400
4800
9600
10400
19200
38400
~300.48
~1201.92
~2403.84
~4807.69
~9615.38
~10416.67
~19230.77
~38461.54
14400
~14285.71
Unit
Hz
ST72344xx, ST2345xx
Table 63.
Address
(Hex.)
On-chip peripherals
SCI register map and reset values
Register
Label
7
6
5
4
3
2
1
0
0050h
SCISR
Reset value
TDRE
1
TC
1
RDRF
0
IDLE
0
OR
0
NF
0
FE
0
PE
0
0051h
SCIDR
Reset value
MSB
x
x
x
x
x
x
x
LSB
x
0052h
SCIBRR
Reset value
SCP1
0
SCP0
0
SCT2
0
SCT1
0
SCT0
0
SCR2
0
SCR1
0
SCR0
0
0053h
SCICR1
Reset value
R8
x
T8
0
SCID
0
M
0
WAKE
0
PCE
0
PS
0
PIE
0
0054h
SCICR2
Reset value
TIE
0
TCIE
0
RIE
0
ILIE
0
TE
0
RE
0
RWU
0
SBK
0
0056h
SCIERPR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
0057h
SCIPETPR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
Doc ID 12321 Rev 6
149/247
On-chip peripherals
ST72344xx, ST2345xx
11.6
I2C bus interface (I2C)
11.6.1
Introduction
The I2C bus interface serves as an interface between the microcontroller and the serial I2C
bus. It provides both multimaster and slave functions, and controls all I2C bus-specific
sequencing, protocol, arbitration and timing. It supports fast I2C mode (400 kHz).
11.6.2
Main features
●
Parallel-bus/I2C protocol converter
●
Multi-master capability
●
7-bit/10-bit Addressing
●
Transmitter/Receiver flag
●
End-of-byte transmission flag
●
Transfer problem detection
I2C master features
●
Clock generation
●
I2C bus busy flag
●
Arbitration lost flag
●
End of byte transmission flag
●
Transmitter/receiver flag
●
Start bit detection flag
●
Start and Stop generation
I2C slave features
11.6.3
●
Stop bit detection
●
I2C bus busy flag
●
Detection of misplaced start or stop condition
●
Programmable I2C address detection
●
Transfer problem detection
●
End-of-byte transmission flag
●
Transmitter/receiver flag
General description
In addition to receiving and transmitting data, this interface converts it from serial to parallel
format and vice versa, using either an interrupt or polled handshake. The interrupts are
enabled or disabled by software. The interface is connected to the I2C bus by a data pin
(SDAI) and by a clock pin (SCLI). It can be connected both with a standard I2C bus and a
Fast I2C bus. This selection is made by software.
150/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Mode selection
The interface can operate in the four following modes:
●
Slave transmitter/receiver
●
Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to master after it generates a START
condition, and from master to slave in case of an arbitration loss or a STOP generation,
allowing then Multi-Master capability.
Communication flow
In Master mode, it initiates a data transfer and generates the clock signal. A serial data
transfer always begins with a start condition and ends with a stop condition. Both start and
stop conditions are generated in master mode by software.
In Slave mode, the interface is capable of recognizing its own address (7 or 10-bit), and the
General Call address. The General Call address detection may be enabled or disabled by
software.
Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the
start condition contain the address (one in 7-bit mode, two in 10-bit mode). The address is
always transmitted in Master mode.
A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must
send an acknowledge bit to the transmitter. Refer to Figure 67.
Figure 67. I2C bus protocol
SDA
ACK
MSB
SCL
1
2
8
9
Stop
Condition
Start
Condition
Acknowledge may be enabled and disabled by software.
The I2C interface address and/or general call address can be selected by software.
The speed of the I2C interface may be selected between Standard (up to 100 kHz) and Fast
I2C (up to 400 kHz).
SDA/SCL line control
●
Transmitter mode: the interface holds the clock line low before transmission to wait for
the microcontroller to write the byte in the Data Register.
●
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data Register.
The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on
the I2C bus mode.
Doc ID 12321 Rev 6
151/247
On-chip peripherals
ST72344xx, ST2345xx
When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 68.
I2C interface block diagram
Data register (DR)
SDA or SDAI
Data control
Data shift register
Comparator
Own address register 1 (OAR1)
Own address register 2 (OAR2)
SCL or SCLI
Clock control
Clock control register (CCR)
Control register (CR)
Status register 1 (SR1)
Control logic
Status register 2 (SR2)
Interrupt
11.6.4
Functional description
Refer to the CR, SR1 and SR2 registers in Section 11.6.7. for the bit definitions.
By default the I2C interface operates in Slave mode (M/SL bit is cleared) except when it
initiates a transmit or receive sequence.
First the interface frequency must be configured using the FRi bits in the OAR2 register.
Slave mode
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register; then it is compared with the address of the interface or the General Call
address (if selected by software).
Note:
In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and
the two most significant bits of the address.
Header matched (10-bit mode only): the interface generates an acknowledge pulse if the
ACK bit is set.
152/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Address not matched: the interface ignores it and waits for another Start condition.
Address matched: the interface generates in sequence:
●
Acknowledge pulse if the ACK bit is set.
●
EVF and ADSL bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register, holding the SCL line low (see
Figure 69 Transfer sequencing EV1).
Next, in 7-bit mode read the DR register to determine from the least significant bit (Data
Direction Bit) if the slave must enter Receiver or Transmitter mode.
In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It
will enter transmit mode on receiving a repeated Start condition followed by the header
sequence with matching address bits and the least significant bit set (11110xx1).
Slave receiver
Following the address reception and after SR1 register has been read, the slave receives
bytes from the SDA line into the DR register via the internal shift register. After each byte the
interface generates in sequence:
●
Acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 69 Transfer sequencing EV2).
Slave transmitter
Following the address reception and after SR1 register has been read, the slave sends
bytes from the DR register to the SDA line via the internal shift register.
The slave waits for a read of the SR1 register followed by a write in the DR register, holding
the SCL line low (see Figure 69 Transfer sequencing EV3).
When the acknowledge pulse is received:
●
The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Closing slave communication
After the last data byte is transferred a Stop Condition is generated by the master. The
interface detects this condition and sets:
●
EVF and STOPF bits with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR2 register (see Figure 69 Transfer sequencing
EV4).
Error cases
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and the BERR bits are set with an interrupt if the ITE bit is set.
If it is a Stop, then the interface discards the data, released the lines and waits for
another Start condition.
If it is a Start, then the interface discards the data and waits for the next slave address
on the bus.
●
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with
an interrupt if the ITE bit is set.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
Doc ID 12321 Rev 6
153/247
On-chip peripherals
ST72344xx, ST2345xx
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
Note:
In both cases, SCL line is not held low; however, the SDA line can remain low if the last bits
transmitted are all 0. It is then necessary to release both lines by software. The SCL line is
not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
How to release the SDA / SCL lines
Set and subsequently clear the STOP bit while BTF is set. The SDA/SCL lines are released
after the transfer of the current byte.
SMBus compatibility
ST7 I2C is compatible with SMBus V1.1 protocol. It supports all SMBus addressing modes,
SMBus bus protocols and CRC-8 packet error checking. Refer to AN1713: SMBus Slave
Driver For ST7 I2C Peripheral.
Master mode
To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent:
●
The EVF and SB bits are set by hardware with an interrupt if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see Figure 69 Transfer sequencing
EV5).
Slave address transmission
Then the slave address is sent to the SDA line via the internal shift register.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence causes the
following event:
●
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 69 Transfer sequencing EV9).
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set):
●
The EVF bit is set by hardware with interrupt generation if the ITE bit is set.
Then the master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see Figure 69 Transfer sequencing
EV6).
Next the master must enter Receiver or Transmitter mode.
154/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Note:
On-chip peripherals
In 10-bit addressing mode, to switch the master to Receiver mode, the software must
generate a repeated Start condition and resend the header sequence with the least
significant bit set (11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
●
Acknowledge pulse if the ACK bit is set
●
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see Figure 69 Transfer sequencing EV7).
To close the communication: before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
Note:
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after SR1 register has been read, the master sends
bytes from the DR register to the SDA line via the internal shift register.
The master waits for a read of the SR1 register followed by a write in the DR register,
holding the SCL line low (see Figure 69 Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets:
●
EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: after writing the last byte to the DR register, set the STOP bit to
generate the Stop condition. The interface goes automatically back to slave mode (M/SL bit
cleared).
Error cases
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
Note that BERR will not be set if an error is detected during the first pulse of each 9-bit
transaction:
Single Master Mode
If a Start or Stop is issued during the first pulse of a 9-bit transaction, the BERR flag will
not be set and transfer will continue however the BUSY flag will be reset. To work
around this, slave devices should issue a NACK when they receive a misplaced Start or
Stop. The reception of a NACK or BUSY by the master in the middle of communication
gives the possibility to re-initiate transmission.
Multimaster Mode
Normally the BERR bit would be set whenever unauthorized transmission takes place
while transfer is already in progress. However, an issue will arise if an external master
generates an unauthorized Start or Stop while the I2C master is on the first pulse of a
9-bit transaction. It is possible to work around this by polling the BUSY bit during I2C
Doc ID 12321 Rev 6
155/247
On-chip peripherals
ST72344xx, ST2345xx
master mode transmission. The resetting of the BUSY bit can then be handled in a
similar manner as the BERR flag being set.
Note:
156/247
●
AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the Start or Stop bit.
The AF bit is cleared by reading the I2CSR2 register. However, if read before the
completion of the transmission, the AF flag will be set again, thus possibly generating a
new interrupt. Software must ensure either that the SCL line is back at 0 before reading
the SR2 register, or be able to correctly handle a second interrupt during the 9th pulse
of a transmitted byte.
●
ARLO: Detection of an arbitration lost condition.
In this case the ARLO bit is set by hardware (with an interrupt if the ITE bit is set and
the interface goes automatically back to slave mode (the M/SL bit is cleared).
In all these cases, the SCL line is not held low; however, the SDA line can remain low if the
last bits transmitted are all 0. It is then necessary to release both lines by software. The SCL
line is not held low while AF=1 but by other flags (SB or BTF) that are set at the same time.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 69. Transfer sequencing
7-bit Slave receiver:
S Address A
Data1 A
EV1
Data2 A
EV2
.....
EV2
DataN A
P
EV2
EV4
7-bit Slave transmitter:
S Address A
Data1 A
EV1 EV3
Data2 A
EV3
EV3
DataN NA
.....
P
EV3-1
EV4
7-bit Master receiver:
S
Address A
EV5
Data1 A
EV6
Data2 A
EV7
EV7
DataN NA
.....
P
EV7
7-bit Master transmitter:
S
Address A
EV5
Data1 A
EV6 EV8
Data2 A
EV8
EV8
DataN A
.....
P
EV8
10-bit Slave receiver:
S Header A Address A
Data1 A
EV1
DataN A
.....
EV2
P
EV2
EV4
10-bit Slave transmitter:
Sr Header A
Data1 A
EV1 EV3
EV3
.....
DataN A
P
EV3-1
EV4
10-bit Master transmitter
S
Header A
EV5
Address A
EV9
Data1 A
EV6 EV8
EV8
.....
DataN A
P
EV8
10-bit Master receiver:
Header A
Sr
EV5
Data1
A
EV6
EV7
.....
DataN A
P
EV7
Legend: S = Start, Sr = Repeated Start, P = Stop, A = Acknowledge, NA = Nonacknowledge, EVx = Event (with interrupt if ITE=1)
EV1: EVF=1, ADSL=1, cleared by reading SR1 register.
EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register. BTF is cleared by
releasing the lines (STOP=1, STOP=0) or by writing DR register (DR=FFh).
Note:
If lines are released by STOP=1, STOP=0, the subsequent EV4 is not seen.
EV4: EVF=1, STOPF=1, cleared by reading SR2 register.
EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register.
Doc ID 12321 Rev 6
157/247
On-chip peripherals
ST72344xx, ST2345xx
EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example
PE=1).
EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register.
EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register.
EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register.
11.6.5
Low-power modes
Table 64.
Mode description
Mode
11.6.6
Description
Wait
No effect on I2C interface.
I2C interrupts cause the device to exit from Wait mode.
Halt
I2C registers are frozen.
In HALT mode, the I2C interface is inactive and does not acknowledge data on the bus.
The I2C interface resumes operation when the MCU is woken up by an interrupt with “exit
from HALT mode” capability.
Interrupts
Figure 70. Event flags and interrupt generation
ADD10
BTF
ADSL
SB
AF
STOPF
ARLO
BERR
ITE
Interrupt
EVF
*
* EVF can also be set by EV6 or an error from the SR2 register.
Table 65.
Interrupt events (1)
Interrupt event
Event flag
10-bit address sent event (Master mode)
Enable
Exit from Exit from
control bit
Wait
Halt
ADD10
Yes
No
BTF
Yes
No
ADSL
Yes
No
Yes
No
AF
Yes
No
Stop detection event (Slave mode)
STOPF
Yes
No
Arbitration lost event (Multimaster configuration)
ARLO
Yes
No
Bus error event
BERR
Yes
No
End of byte transfer event
Address matched event (Slave mode)
Start bit generation event (Master mode)
SB
ITE
Acknowledge failure event
158/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
1. The I2C interrupt events are connected to the same interrupt vector (see Section 8: Interrupts). They
generate an interrupt if the corresponding Enable Control Bit is set and the I-bit in the CC register is reset
(RIM instruction).
11.6.7
Register description
I2C control register (CR)
Reset value: 0000 0000 (00h)
7
0
0
0
PE
ENGC
START
ACK
STOP
ITE
Read / Write
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral enable.
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
Note:
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the I2C interface, write the CR register TWICE with PE=1 as the first write only
activates the interface (only PE is set).
Bit 4 = ENGC Enable General Call.
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
Note:
In accordance with the I2C standard, when GCAL addressing is enabled, an I2C slave can
only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition.
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0) or when the Start condition is sent (with interrupt generation if
ITE=1).
●
In master mode:
0: No start generation
1: Repeated start generation
●
In slave mode:
0: No start generation
1: Start generation when the bus is free
Doc ID 12321 Rev 6
159/247
On-chip peripherals
ST72344xx, ST2345xx
Bit 2 = ACK Acknowledge enable.
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
Bit 1 = STOP Generation of a Stop condition.
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note:
This bit is not cleared when the interface is disabled (PE=0).
●
In master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition is
sent. The STOP bit is cleared by hardware when the Stop condition is sent.
●
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode
the STOP bit has to be cleared by software.
Bit 0 = ITE Interrupt enable.
This bit is set and cleared by software and cleared by hardware when the interface is
disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to Figure 70 for the relationship between the events and the interrupt.
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
Figure 69) is detected.
I2C status register 1 (SR1)
Reset value: 0000 0000 (00h)
7
EVF
0
ADD10
TRA
BUSY
BTF
Read Only
160/247
Doc ID 12321 Rev 6
ADSL
M/SL
SB
ST72344xx, ST2345xx
On-chip peripherals
Bit 7 = EVF Event flag.
This bit is set by hardware as soon as an event occurs. It is cleared by software reading
SR2 register in case of error event or as described in Figure 69. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No event
1: One of the following events has occurred:
●
BTF=1 (Byte received or transmitted)
●
ADSL=1 (Address matched in Slave mode while ACK=1)
●
SB=1 (Start condition generated in Master mode)
●
AF=1 (No acknowledge received after byte transmission)
●
STOPF=1 (Stop condition detected in Slave mode)
●
ARLO=1 (Arbitration lost in Master mode)
●
BERR=1 (Bus error, misplaced Start or Stop condition detected)
●
ADD10=1 (Master has sent header byte)
●
Address byte successfully transmitted in Master mode.
Bit 6 = ADD10 10-bit addressing in Master mode.
This bit is set by hardware when the master has sent the first byte in 10-bit address
mode. It is cleared by software reading SR2 register followed by a write in the DR
register of the second address byte. It is also cleared by hardware when the peripheral
is disabled (PE=0).
0: No ADD10 event occurred.
1: Master has sent first address byte (header)
Bit 5 = TRA Transmitter/Receiver.
When BTF is set, TRA=1 if a data byte has been transmitted. It is cleared automatically
when BTF is cleared. It is also cleared by hardware after detection of Stop condition
(STOPF=1), loss of bus arbitration (ARLO=1) or when the interface is disabled (PE=0).
0: Data byte received (if BTF=1)
1: Data byte transmitted
Bit 4 = BUSY Bus busy.
This bit is set by hardware on detection of a Start condition and cleared by hardware on
detection of a Stop condition. It indicates a communication in progress on the bus. The
BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs.
0: No communication on the bus
1: Communication ongoing on the bus
Bit 3 = BTF Byte transfer finished.
This bit is set by hardware as soon as a byte is correctly received or transmitted with
interrupt generation if ITE=1. It is cleared by software reading SR1 register followed by
a read or write of DR register. It is also cleared by hardware when the interface is
disabled (PE=0).
●
Following a byte transmission, this bit is set after reception of the acknowledge clock
pulse. In case an address byte is sent, this bit is set only after the EV6 event (See
Doc ID 12321 Rev 6
161/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 69). BTF is cleared by reading SR1 register followed by writing the next byte in
DR register.
●
Following a byte reception, this bit is set after transmission of the acknowledge clock
pulse if ACK=1. BTF is cleared by reading SR1 register followed by reading the byte
from DR register.
The SCL line is held low while BTF=1.
0: Byte transfer not done
1: Byte transfer succeeded
Bit 2 = ADSL Address matched (Slave mode).
This bit is set by hardware as soon as the received slave address matched with the
OAR register content or a general call is recognized. An interrupt is generated if ITE=1.
It is cleared by software reading SR1 register or by hardware when the interface is
disabled (PE=0).
The SCL line is held low while ADSL=1.
0: Address mismatched or not received
1: Received address matched
Bit 1 = M/SL Master/Slave.
This bit is set by hardware as soon as the interface is in Master mode (writing
START=1). It is cleared by hardware after detecting a Stop condition on the bus or a
loss of arbitration (ARLO=1). It is also cleared when the interface is disabled (PE=0).
0: Slave mode
1: Master mode
Bit 0 = SB Start bit (Master mode).
This bit is set by hardware as soon as the Start condition is generated (following a write
START=1). An interrupt is generated if ITE=1. It is cleared by software reading SR1
register followed by writing the address byte in DR register. It is also cleared by
hardware when the interface is disabled (PE=0).
0: No Start condition
1: Start condition generated
I2C status register 2 (SR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
AF
STOPF
Read Only
Bit 7:5 = Reserved.
Forced to 0 by hardware.
162/247
Doc ID 12321 Rev 6
ARLO
BERR
GCAL
ST72344xx, ST2345xx
On-chip peripherals
Bit 4 = AF Acknowledge failure.
This bit is set by hardware when no acknowledge is returned. An interrupt is generated
if ITE=1. It is cleared by software reading SR2 register or by hardware when the
interface is disabled (PE=0).
The SCL line is not held low while AF=1 but by other flags (SB or BTF) that are set at
the same time.
0: No acknowledge failure
1: Acknowledge failure
Bit 3 = STOPF Stop detection (Slave mode).
This bit is set by hardware when a Stop condition is detected on the bus after an
acknowledge (if ACK=1). An interrupt is generated if ITE=1. It is cleared by software
reading SR2 register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while STOPF=1.
0: No Stop condition detected
1: Stop condition detected
Bit 2 = ARLO Arbitration lost.
This bit is set by hardware when the interface loses the arbitration of the bus to another
master. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
After an ARLO event the interface switches back automatically to Slave mode
(M/SL=0).
The SCL line is not held low while ARLO=1.
0: No arbitration lost detected
1: Arbitration lost detected
Note:
In a Multimaster environment, when the interface is configured in Master Receive mode it
does not perform arbitration during the reception of the Acknowledge Bit. A mishandling of
the ARLO bit from the I2CSR2 register may occur when a second master simultaneously
requests the same data from the same slave, and the I2C master does not acknowledge the
data. The ARLO bit is then left at 0 instead of being set.
Bit 1 = BERR Bus error.
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. An interrupt is generated if ITE=1. It is cleared by software reading SR2
register or by hardware when the interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Note:
If a Bus Error occurs, a Stop or a repeated Start condition should be generated by the
Master to re-synchronize communication, get the transmission acknowledged and the bus
released for further communication
Bit 0 = GCAL General Call (Slave mode).
This bit is set by hardware when a general call address is detected on the bus while
ENGC=1. It is cleared by hardware detecting a Stop condition (STOPF=1) or when the
interface is disabled (PE=0).
0: No general call address detected on the bus
1: General call address detected on the bus
Doc ID 12321 Rev 6
163/247
On-chip peripherals
ST72344xx, ST2345xx
I2C clock control register (CCR)
Reset value: 0000 0000 (00h)
7
FM/SM
0
CC6
CC5
CC4
CC3
CC2
CC1
CC0
Read / Write
Bit 7 = FM/SM Fast/Standard I2C mode.
This bit is set and cleared by software. It is not cleared when the interface is disabled
(PE=0).
0: Standard I2C mode
1: Fast I2C mode
Bit 6:0 = CC[6:0] 7-bit clock divider.
These bits select the speed of the bus (FSCL) depending on the I2C mode. They are not
cleared when the interface is disabled (PE=0).
Refer to Section 13: Electrical characteristics for the table of values.
Note:
164/247
The programmed fSCL assumes no load on SCL and SDA lines.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
I2C data register (DR)
Reset value: 0000 0000 (00h)
7
D7
0
D6
D5
D4
D3
D2
D1
D0
Read / Write
Bits 7:0 = D[7:0] 8-bit Data Register.
These bits contain the byte to be received or transmitted on the bus.
●
Transmitter mode: byte transmission start automatically when the software writes in the
DR register.
●
Receiver mode: the first data byte is received automatically in the DR register using the
least significant bit of the address.
Then, the following data bytes are received one by one after reading the DR register.
I2C own address register (OAR1)
Reset value: 0000 0000 (00h)
7
ADD7
0
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
Read / Write
7-bit addressing mode
Bits 7:1 = ADD[7:1] Interface address.
These bits define the I2C bus address of the interface. They are not cleared when the
interface is disabled (PE=0).
Bit 0 = ADD0 Address direction bit.
This bit is don’t care, the interface acknowledges either 0 or 1. It is not cleared when
the interface is disabled (PE=0).
Note:
Address 01h is always ignored.
10-bit addressing mode
Bit 7:0 = ADD[7:0] Interface address.
These are the least significant bits of the I2C bus address of the interface. They are not
cleared when the interface is disabled (PE=0).
Doc ID 12321 Rev 6
165/247
On-chip peripherals
ST72344xx, ST2345xx
I2C own address register (OAR2)
Reset value: 0100 0000 (40h)
7
FR1
0
FR0
0
0
0
ADD9
ADD8
0
Read / Write
Bit 7:6 = FR[1:0] Frequency bits.
These bits are set by software only when the interface is disabled (PE=0). To configure
the interface to I2C specified delays select the value corresponding to the
microcontroller frequency fCPU.
Table 66.
FR[1:0] configuration
fCPU
FR1
FR0
< 6 MHz
0
0
6 to 8 MHz
0
1
Bits 5:3 = Reserved
Bits 2:1 = ADD[9:8] Interface address.
These are the most significant bits of the I2C bus address of the interface (10-bit mode
only). They are not cleared when the interface is disabled (PE=0).
Bit 0 = Reserved.
Table 67.
I2C register map and reset values
Address
(Hex.)
Register
label
0058h
7
6
5
4
3
2
1
0
I2CCR
Reset value
0
0
PE
0
ENGC
0
START
0
ACK
0
STOP
0
ITE
0
0059h
I2CSR1
Reset value
EVF
0
ADD10
0
TRA
0
BUSY
0
BTF
0
ADSL
0
M/SL
0
SB
0
005Ah
I2CSR2
Reset value
0
0
0
AF
0
STOPF
0
ARLO
0
BERR
0
GCAL
0
005Bh
I2CCCR
Reset value
FM/SM
0
CC6
0
CC5
0
CC4
0
CC3
0
CC2
0
CC1
0
CC0
0
005Ch
I2COAR1
Reset value
ADD7
0
ADD6
0
ADD5
0
ADD4
0
ADD3
0
ADD2
0
ADD1
0
ADD0
0
005Dh
I2COAR2
Reset value
FR1
0
FR0
1
0
0
0
ADD9
0
ADD8
0
0
005Eh
I2CDR
Reset value
MSB
0
0
0
0
0
0
0
LSB
0
166/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
11.7
I2C triple slave interface with DMA (I2C3S)
11.7.1
Introduction
The I2C3S interface provides three I2C slave functions, supporting both standard (up to
100 kHz) and fast I2C mode (100 to 400 kHz). Special features are provided for:
11.7.2
●
Full-speed emulation of standard I2C E2PROMs
●
Receiving commands to perform user-defined operations such as IAP
Main features
●
Three user configurable independent slave addresses can be individually enabled
●
2x 256 bytes and 1x 128 bytes buffers with fixed addresses in RAM
●
7-bit addressing
●
DMA transfer to/from I2C bus and RAM
●
Standard (transfers 256 bytes at up to 100 kHz)
●
Fast mode (transfers 256 bytes at up to 400 kHz)
●
Transfer error detection and handling
●
3 interrupt flags per address for maximum flexibility
●
Two interrupt request lines (one for Slaves 1 and 2, the other for Slave 3)
●
Full emulation of standard I2C EEPROMs:
●
–
Supports 5 read/write commands and combined format
–
No I2C clock stretching
–
Programmable page size (8/16 bytes) or full buffer
–
Configurable write protection
Data integrity and byte-pair coherency when reading 16-bit words from I2C bus
Doc ID 12321 Rev 6
167/247
On-chip peripherals
Figure 71.
ST72344xx, ST2345xx
I2C3S interface block diagram
I2C SLAVE ADDRESS 1
DATA E2PROM
256 BYTES
I2C SLAVE ADDRESS 3
RAM
SLAVE 1 BUFFER
256 BYTES
COMPARATOR
8-BIT
SHIFT REGISTER
SDA or SDAI
DATA/ADDRESS BUS
I2C SLAVE ADDRESS 2
SLAVE 2 BUFFER
256 BYTES
SCL or SCLI
DMA
SLAVE 3 BUFFER
128 BYTES
SHADOW
REGISTER
CONTROL LOGIC
Slave 1 or 2 Interrupt
Slave 3 Interrupt
11.7.3
CPU
General description
In addition to receiving and transmitting data, I2C3S converts it from serial to parallel format
and vice versa. The interrupts are enabled or disabled by software. The I2C3S is connected
to the I2C bus by a data pin (SDA) and by a clock pin (SCL). It can be connected both with a
standard I2C bus and a Fast I2C bus. The interface operates only in Slave mode as
transmitter/receiver.
In order to fully emulate standard I2C EEPROM devices with highest transfer speed, the
peripheral prevents I2C clock signal stretching and performs data transfer between the shift
register and the RAM buffers using DMA.
Communication flow
A serial data transfer normally begins with a start condition and ends with a stop condition.
Both start and stop conditions are generated by an external master. Refer to Figure 67 for
the standard protocol. The I2C3S is not a master and is not capable of generating a
start/stop condition on the SDA line. The I2C3S is capable of recognizing 3 slave addresses
which are user programmable. The three I2C slave addresses can be individually
enabled/disabled by software.
Since the I2C3S interface always acts as a slave, it does not generate a clock. Data and
addresses are transferred as 8-bit bytes, MSB first. The first byte following the start
condition contains the slave address. A 9th clock pulse follows the 8 clock cycles of a byte
transfer, during which the receiver must send an acknowledge bit to the transmitter.
168/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
SDA/SCL line control
●
When the I2C3S interface is enabled, the SDA and SCL ports must be configured as
floating inputs. In this case, the value of the external pull-up resistor used depends on
the application.
●
When the I2C3S interface is disabled, the SDA and SCL ports revert to being standard
I/O port pins.
Figure 72. I2C bus protocol
SDA
ACK
MSB
SCL
1
2
Start
condition
11.7.4
8
9
Stop
condition
Functional description
The three slave addresses 1, 2 and 3 can be used as general purpose I2C slaves. They also
support all features of standard I2C EEPROMs like the ST M24Cxx family and are able to
fully emulate them.
Slaves 1 and 2 are mapped on the same interrupt vector. Slave 3 has a separate interrupt
vector with higher priority.
The three slave addresses are defined by writing the 7 MSBs of the address in the
I2C3SSAR1, I2C3SSAR2 and I2C3SSAR3 registers. The slaves are enabled by setting the
enable bits in the same registers.
Each slave has its own RAM buffer at a fixed location in the ST7 RAM area.
●
Slaves 1 and 2 have 256-byte buffers which can be individually protected from I2C
master write accesses.
●
Slave 3 has a 128-byte RAM buffer without write protection feature.
All three slaves have individual read flags (RF) and write flags (WF) with maskable
interrupts. These flags are set when the I2C master has completed a read or write operation.
Paged operation
To allow emulation of Standard I2C EEPROM devices, pages can be defined in the RAM
buffer. The pages are configured using the PL[1:0] bits in the I2C3SCR1 register. 8/16-Byte
page length has to be selected depending on the EEPROM device to emulate. The Full
Page option is to be used when no paging of the RAM buffer is required. The configuration is
common to the 3 slave addresses. The Full Page configuration corresponds to 256 bytes for
address 1 and 2 and to 128 bytes for address 3.
Paging affects the handling of rollover when write operations are performed. In case the
bottom of the page is reached, the write continues from the first address of the same page.
Page length does not affect read operations: rollover is done on the whole RAM buffer
whatever the configured page length.
Doc ID 12321 Rev 6
169/247
On-chip peripherals
ST72344xx, ST2345xx
The Byte count register is reset when it reaches 256 bytes, whatever the page length, for all
slave addresses, including slave 3.
DMA
The I2C slaves use a DMA controller to write/read data to/from their RAM buffer.
A DMA request is issued to the DMA controller on reception of a byte or just before
transmission of a byte.
When a byte is written by DMA in RAM, the CPU is stalled for max. 2 cycles. When several
bytes are transferred from the I2C bus to RAM, the DMA releases between each byte and
the CPU resumes processing until the DMA writes the next byte.
RAM buffer write protection
By setting the WP1/WP2 bits in the I2C3SCR2 register, it is possible to protect the RAM
buffer of Slaves 1/2 respectively against write access from the master.
If a write operation is attempted, the slave address is acknowledged, the current address
register is overwritten, data is also acknowledged but it is not written to the RAM. Both the
current address and byte count registers are incremented as in normal operation.
In case of write access to a write protected address, no interrupt is generated and the
BusyW bit in the I2C3SCR2 register is not set.
Only write operations are disabled/enabled. Read operations are not affected.
Byte-pair coherency for I2C read operations
Byte-pair coherency allows the I2C master to read a 16-bit word and ensures that it is not
corrupted by a simultaneous CPU update. Two mechanisms are implemented, covering the
two possible cases:
170/247
1.
CPU updates a word in RAM after the first byte has been transferred to the I2C shift
register from RAM. In this case, the first byte read from RAM would be the MSB of the
old word and 2nd byte would be the LSB of the new word.
To prevent this corruption, the I2C3S uses DMA to systematically read a 2-byte word
when it receives a read command from the I2C master. The MSB of the word should be
at address 2n. Using DMA, the MSB is moved from RAM address 2n to the I2C shift
register and the LSB from RAM address 2n+1 moved to a shadow register in the I2C3S
peripheral. The CPU is stalled for a maximum of 2 cycles during word transfer.
In case only one byte is read, the unused content of the shadow register will be
automatically overwritten when a new read operation is performed.
In case a second byte is read in the same I2C message (no Stop or Restart condition),
the content of the shadow register is transferred to the shift register and transmitted to
the master.
This process continues until a Stop or Restart condition occurs.
2.
I2C3S attempts to read a word while the CPU is updating the RAM buffer. To prevent
data corruption, the CPU must switch operation to Word mode prior to updating a word
in the RAM buffer. Word mode is enabled by software using the B/W bit in the
I2C3SCR2 register. In Word mode, when the CPU writes the MSB of a word to address
2n, it is stored in a shadow register rather than being actually written in RAM. When the
CPU writes the second byte (the LSB) at address 2n+1, it is directly written in RAM.
The next cycle after the write to address 2n+1, the MSB is automatically written from
the shadow register to RAM address 2n. DMA is disabled for a 1 cycle while the CPU is
writing a word.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Word mode is disabled by hardware after the word update is performed. It must be
enabled before each word update by CPU.
Use the following procedure when the ST7 writes a word in RAM:
Note:
1.
Disable interrupts
2.
Enable Word mode by setting the B/W and BusyW bits in the I2C3SCR2 register.
BusyW bit is set to 1 when modifying any bits in Control Register 2. Writing a 1 to this
bit does not actually modify BusyW but prevents accidental clearing of the bit.
3.
Write Byte 1 in an even address in RAM. The byte is not actually written in RAM but in
a shadow register. This address must be within the I2C RAM buffer of slave addresses
1, 2 or 3.
4.
Write Byte 2 in the next higher address in RAM. This byte is actually written in RAM.
During the next cycle, the shadow register content is written in the lower address. The
DMA request is disabled during this cycle.
5.
Byte mode resumes automatically after writing byte 2 and DMA is re-enabled.
6.
Enable interrupts
Word mode does not guarantee byte-pair coherency of words WRITTEN by the I2C master
in RAM and read by the ST7. In this case, byte pair coherency must be handled by software.
Figure 73. 16-bit word write operation flowchart
HOST
ST7 I2C3SNS
ST7 CPU
Sends address
and write bit
Decodes I2C3SNS address
decodes R/W bit
sets write flag
Sends write address
Updates current addressregister
Normal execution
Issues DMA request
Word mode?
Y
Repeat
Delays while CPU
completes word write
Sends 1 byte of data
STOP condition
Writes one byte to RAM
Halts execution
N
1 Cycle
max
Resumes execution
Sets BUSYW in control register + I2C3S disabled
issues interrupt
Services I2C3SNS interrupt
Resets I2C3SNS write flag
Reads I2C3SNS status register
Enables I2C3SNS
Updates control register
1 Cycle
max
Byte-Pair Coherency ensured by setting Word Mode
RAM start address depends on slave address
Doc ID 12321 Rev 6
171/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 74. 16-bit word read operation flowchart
Host
Sends address
and read bit
Sends read address
ST7 I2C3SNS
ST7 CPU
Decodes I2C3SNS address
Decodes R/W bit
Sets read flag
Normal execution
Updates current addressregister
Issues DMA request
Word mode?
Halts execution
N
Y
Delays while CPU
completes word write
Repeat
Receives byte 1
Reads 1 word from RAM
Byte 1 => Shift reg
Byte 2 => Shadow reg
Releases DMA
STOP?
Resumes execution
3 cycles
max
Y
N
Receives byte 2
Stop condition
Shadow reg => Shift reg
Updates status + DMA CNTL
Services I2C3SNS interrupt
Resets read flag
Reads I2C3SNS status register
Byte-Pair Coherency ensured by setting Word Mode + DMA on Words
RAM start address depends on slave address
Application note
Taking full advantage of its higher interrupt priority Slave 3 can be used to allow the
addressing master to send data bytes as commands to the ST7. These commands can be
decoded by the ST7 software to perform various operations such as programming the Data
E2PROM via IAP (In-Application Programming).
Slave 3 writes the command byte and other data in the RAM and generates an interrupt.
The ST7 then decodes the command and processes the data as decoded from the
command byte. The ST7 also writes a status byte in the RAM which the addressing master
can poll.
11.7.5
Address handling
As soon as a start condition is detected, the address is received from the SDA line and sent
to the shift register. Then it is compared with the three addresses of the interface to decode
which slave of the interface is being addressed.
Address not matched: the interface ignores it and waits for another Start condition.
172/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Address matched: the interface generates in sequence the following:
Note:
●
An Acknowledge pulse
●
Depending on the LSB of the slave address sent by the master, slaves enter transmitter
or receiver mode.
●
Send an interrupt to the CPU after completion of the read/write operation after
detecting the Stop/ Restart condition on the SDA line.
The Status Register has to be read to clear the event flag associated with the interrupt.
An interrupt will be generated only if the interrupt enable bit is set in the Control Register.
Slaves 1 and 2 have a common interrupt and the Slave 3 has a separate interrupt.
At the end of write operation, I2C3S is temporarily disabled by hardware by setting BusyW
bit in CR2. The byte count register, status register and current address register should be
saved before resetting BusyW bit.
Slave reception (write operations)
Byte Write: The Slave address is followed by an 8-bit byte address. Upon receipt of this
address, an acknowledge is generated, the address is moved into the current address
register and the 8-bit data is clocked in. Once the data is shifted in, a DMA request is
generated and the data is written in the RAM. The addressing device will terminate the write
sequence with a stop condition. Refer to Figure 76.
Page Write: A page write is initiated in a similar way to a byte write, but the addressing
device does not send a stop condition after the first data byte. The page length is
programmed using bits 7:6 (PL[1:0]) in the Control Register1.
The current address register value is incremented by one every time a byte is written. When
this address reaches the page boundary, the next byte will be written at the beginning of the
same page. Refer to Figure 77.
Slave transmission (Read operations)
Current address read: The current address register maintains the last address accessed
during the last read or write operation incremented by one.
During this operation the I2C slave reads the data pointed by the current address register.
Refer to Figure 78.
Random read: Random read requires a dummy byte write sequence to load in the byte
address. The addressing device then generates restart condition and resends the device
address similar to current address read with the read/write bit high. Refer to Figure 79.
Some types of I2C masters perform a dummy write with a stop condition and then a current
address read.
In either case, the slave generates a DMA request, sends an acknowledge and serially
clocks out the data.
When the memory address limit is reached, the current address will roll over and the
random read will continue till the addressing master sends a stop condition.
Sequential read: Sequential reads are initiated by either a current address read or a
random address read. After the addressing master receives the data byte, it responds with
an acknowledge. As long as the slave receives an acknowledge, it continues to increment
the current address register and clock out sequential data bytes.
Doc ID 12321 Rev 6
173/247
On-chip peripherals
ST72344xx, ST2345xx
When the memory address limit is reached the current address will roll over and the
sequential read will continue till the addressing master sends a stop condition. Refer to
Figure 81.
Combined format
If a master wants to continue communication either with another slave or by changing the
direction of transfer then the master would generate a restart and provide a different slave
address or the same slave address with the R/W bit reversed. Refer to Figure 82.
Rollover handling
The RAM buffer of each slave is divided into pages whose length is defined according to
PL1:0 bits in I2C3SCR1. Rollover takes place in these pages as described below.
In the case of Page Write, if the number of data bytes transmitted is more than the page
length, the current address will roll over to the first byte of the current page and the previous
data will be overwritten. This page size is configured using PL[1:0] bit in the I2C3SCR1
register.
In case of Sequential Read, if the current address register value reaches the memory
address limit the address will roll over to the first address of the reserved area for the
respective slave.
There is no status flag to indicate the roll over.
Note:
The reserved areas for slaves 1 and 2 have a limit of 256 bytes. The area for slave 3 is 128
bytes. The MSB of the address is hardwired, the addressing master therefore needs to send
only an 8 bit address.
The page boundaries are defined based on the page size configuration using PL[1:0] bit in
the I2C3SCR1 register. If an 8-byte page size is selected, the upper 5 bits of the RAM
address are fixed and the lower 3 bits are incremented. For example, if the page write starts
at register address 0x0C, the write will follow the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x08,
0x09, 0x0A, 0x0B. If a 16-byte page size is selected, the upper 4 bits of the RAM address
are fixed and the lower 4 bits are incremented. For example, if the page write starts at
register address 0x0C, the write will follow the sequence 0x0C, 0x0D, 0x0E, 0x0F, 0x00,
0x01, etc.
Error conditions
174/247
●
BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
BERR bit is set by hardware with an interrupt if ITER is set. During a stop condition, the
interface discards the data, releases the lines and waits for another Start condition.
However, a BERR on a Start condition will result in the interface discarding the data
and waiting for the next slave address on the bus.
●
NACK: Detection of a non-acknowledge bit not followed by a Stop condition. In this
case, NACK bit is set by hardware with an interrupt if ITER is set.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Figure 75. Transfer sequencing
7-bit Slave receiver:
S Address A
Data1
A
Data2
A
.....
WF
DataN A P
BusyW
7-bit Slave transmitter:
S Address A
Data1
A
Data2
A
.....
RF
DataN NA P
Legend: S = Start, P = Stop, A = Acknowledge, NA = Non-acknowledge,
WF = WF event, WFx bit is set (with interrupt if ITWEx=1, after Stop or Restart conditions),
cleared by reading the I2C3SSR register while no communication is ongoing.
RF = RF event, RFx is set (with interrupt if ITREx=1, after Stop or Restart conditions),
cleared by reading the I2C3SSR register while no communication is ongoing.
BusyW = BusyW flag in the I2C3CR2 register set, cleared by software writing 0.
Note:
The I2C3S supports a repeated start (Sr) in place of a stop condition (P).
Figure 76. Byte write
Start
SA
W
Ack
BA
Ack
Data
Ack
Stop
Figure 77. Page write
Start
SA
W
Ack
BA
Ack
Data
Ack
Data
Ack
Stop
Figure 78. Current address read
Start
SA
R
Ack
Data
Nack
Stop
Figure 79. Random read (dummy write + restart + current address read)
Start
SA
W Ack
BA
Ack Start
SA
Doc ID 12321 Rev 6
R Ack
Data
Nack
Stop
175/247
On-chip peripherals
ST72344xx, ST2345xx
Figure 80. Random read (dummy write + stop + start + current address read)
Start
SA
W Ack
BA
Ack
Stop Start
SA
R Ack
Data
Nack
Stop
Figure 81. Sequential read
Start
R
SA
Data
Ack
Ack
Data
Ack
Data Nack
Stop
Figure 82. Combined format for read
Start
SA
R
Ack
Data
Nack
Restart
SA
R
Ack
Data
Nack
Stop
Legend: SA - Slave Address, BA - Byte Address, W: Write, R: Read
11.7.6
Low-power modes
Table 68.
Mode
176/247
Mode description
Description
Wait
No effect on I2C interface.
I2C interrupts causes the device to exit from Wait mode.
Halt
I2C registers are frozen.
In Halt mode, the I2C interface is inactive and does not acknowledge data on the bus.
The I2C interface resumes operation when the MCU is woken up by an interrupt with
“exit from Halt mode” capability.
Active-halt
I2C registers are frozen.
In Active halt mode, the I2C interface is inactive and does not acknowledge data on the
bus. The I2C interface resumes operation when the MCU is woken up by an interrupt
with “exit from Active-halt mode” capability.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
11.7.7
On-chip peripherals
Interrupt generation
Figure 83. Event flags and interrupt generation
Restart
Stop
Data Status Flag
Dummy Write
Write Protect
Restart: Restart condition on SDA
Stop: Stop condition on SDA
Dummy Write: True if no data is written in RAM
Write Protect: True for Write operation and if slaves
are write protected (since this is applicable for
slaves 1 and 2. For slave 3 and for Read operation
write protect will always be 0)
Data Status Flag: Actual Interrupt is produced when
this condition is true
Restart:
Restart condition on SDA
Data Status Flag
RF1
RF2
ITRE1/2
NACK
INTERRUPT 1
(Slave address 1/2)
ITER
BERR
WF1
WF2
ITWE1/2
Data Status Flag
Data Status Flag
WF3
ITWE3
BERR
INTERRUPT 2
ITER
NACK
(Slave address 3)
RF3
ITRE3
Data Status Flag
Note:
Read/Write interrupts are generated only after stop or restart conditions. Figure 83 shows
the conditions for the generation of the two interrupts.
Table 69.
Interrupt events
Flag
Enable
control
bit
Exit
from
wait
Exit
from
halt
Interrupt on write to Slave 1
WF1
ITWE1
Yes
No
Interrupt on write to Slave 2
WF2
ITWE1
Yes
No
Interrupt on write to Slave 3
WF3
ITWE2
Yes
No
RF1- RF3
ITREx
Yes
No
BERR, NACK
ITER
Yes
No
Interrupt event
Interrupt on Read from Slave 1, Slave 2 or Slave 3.
Errors
Doc ID 12321 Rev 6
177/247
On-chip peripherals
11.7.8
ST72344xx, ST2345xx
Register description
I2C 3S control register 1 (I2C3SCR1)
Reset value: 0000 0000 (00h)
7
PL1
PL0
0
0
ITER
ITRE3
ITRE1/2
ITWE3
ITWE
1/2
Read / Write
Bits 7:6 = PL1:0 Page length configuration
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
Table 70.
PL configuration
PL1
PL0
Page length
0
0
8
0
1
16
1
0
Full Page (256 bytes for slave 1 & 2, 128 bytes for slave 3)
1
1
NA
Bit 5 = Reserved, must be kept at 0.
Bit 4 = ITER BERR / NACK Interrupt enable
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: BERR / NACK interrupt disabled
1: BERR / NACK interrupt enabled
Note:
In case of error, if ITER is enabled either interrupt 1 or 2 is generated depending on which
slave flags the error (see Figure 83).
Bit 3= ITRE3 Interrupt enable on read from Slave 3
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE =0).
0: Interrupt on Read from Slave 3 disabled
1: Interrupt on Read from Slave 3 enabled
Bit 2 = ITRE1/2 Interrupt enable on read from Slave 1 or 2
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled.
(PE =0)
0: Interrupt on Read from Slave 1 or 2 disabled
1: Interrupt on Read from Slave 1 or 2 enabled
178/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Bit 1= ITWE3 Interrupt enable on write to Slave 3
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled.
0: Interrupt after write to Slave 3 disabled
1: Interrupt after write to Slave 3 enabled
Bit 0 = ITWE1/2 Interrupt enable on write to Slave 1 or 2
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled software. It is also cleared by hardware when the interface is disabled.
0: Interrupt after write to Slave 1 or 2 disabled
1: Interrupt after write to Slave 1 or 2 enabled
I2C control register 2 (I2C3SCR2)
Reset value: 0000 0000 (00h)
7
0
0
0
0
WP2
WP1
PE
BusyW
B/W
Read / Write
Bits 7:5 = Reserved, must be kept at 0.
Bit 4 = WP2 Write Protect enable for Slave 2
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0)
0: Write access to Slave 2 RAM buffer enabled
1: Write access to Slave 2 RAM buffer disabled
Bit 3 = WP1 Write Protect enable for Slave 1
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: Write access to Slave 1 RAM buffer enabled
1: Write access to Slave 1 RAM buffer disabled
Note:
(Applicable for both WP2/ WP1)
Only write operations are disabled/enabled. Read operations are not affected.
If a write operation is attempted, the slave address is acknowledged, the current address
register is overwritten, data is also acknowledged but it is not written to the RAM.
Both the current address and byte count registers are incremented as in normal operation.
No interrupt generated if slave is write protected
BusyW will not be set if slave is write protected
Bit 2 = PE Peripheral enable
This bit is set and cleared by software.
0: Peripheral disabled
1: Slave capability enabled
Note:
To enable the I2C interface, write the CR register TWICE with PE=1, as the first write only
activates the interface (only PE is set).
Doc ID 12321 Rev 6
179/247
On-chip peripherals
ST72344xx, ST2345xx
Bit 1 = BusyW Busy on Write to RAM Buffer
This bit is set by hardware when a Stop/ Restart is detected after a write operation. The
I2C3S peripheral is temporarily disabled till this bit is reset. This bit is cleared by
software. If this bit is not cleared before the next slave address reception, further
communication will be non-acknowledged. This bit is set to 1 when modifying any bits
in Control Register 2. Writing a 1 to this bit does not actually modify BusyW but
prevents accidentally clearing of the bit.
0: No BusyW event occurred
1: A Stop/ Restart is detected after a write operation
Bit 0 = B/W Byte / Word Mode
This control bit must be set by software before a word is updated in the RAM buffer and
cleared by hardware after completion of the word update. In Word mode the CPU
cannot be interrupted when it is modifying the LSB byte and MSB byte of the word. This
mode is to ensure the coherency of data stored as words.
0: Byte mode
1: Word mode
Note:
When the word mode is enabled, all interrupts should be masked while the word is being
written in RAM.
I2C3S status register (I2C3SSR)
Reset value: 0000 0000 (00h)
7
NACK
0
BERR
WF3
WF2
WF1
RF3
RF2
RF1
Read Only
Bit 7= NACK Non Acknowledge not followed by Stop
This bit is set by hardware when a non acknowledge returned by the master is not
followed by a Stop or Restart condition. It is cleared by software reading the SR register
or by hardware when the interface is disabled (PE=0).
0: No NACK error occurred
1: Non Acknowledge not followed by Stop
Bit 6 = BERR Bus error
This bit is set by hardware when the interface detects a misplaced Start or Stop
condition. It is cleared by software reading SR register or by hardware when the
interface is disabled (PE=0).
The SCL line is not held low while BERR=1.
0: No misplaced Start or Stop condition
1: Misplaced Start or Stop condition
Bit 5 = WF3 Write operation to Slave 3
This bit is set by hardware on reception of the direction bit in the I2C address byte for
Slave 3. This bit is cleared when the status register is read and there is no
communication ongoing or when the peripheral is disabled (PE = 0)
0: No write operation to Slave 3
1: Write operation performed to Slave 3
180/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Bit 4 = WF2 Write operation to Slave 2
This bit is set by hardware on reception of the direction bit in the I2C address byte for
Slave 2. This bit is cleared when the status register is read and there is no
communication ongoing, or when the peripheral is disabled (PE = 0)
0: No write operation to Slave 2
1: Write operation performed to Slave 2
Bit 3 = WF1 Write operation to Slave 1
This bit is set by hardware on reception of the direction bit in the I2C address byte for
Slave 1. This bit is cleared by software when the status register is read and there is no
communication ongoing, or by hardware when the peripheral is disabled (PE = 0).
0: No write operation to Slave 1
1: Write operation performed to Slave 1
Bit 2 = RF3 Read operation from Slave 3
This bit is set by hardware on reception of the direction bit in the I2C address byte for
Slave 3. It is cleared by software reading the SR register when there is no
communication ongoing. It is also cleared by hardware when the interface is disabled
(PE=0).
0: No read operation from Slave 3
1: Read operation performed from Slave 3
Bit 1= RF2 Read operation from Slave 2
This bit is set by hardware on reception of the direction bit in the I2C address byte for
Slave 2. It is cleared by software reading the SR register when there is no
communication ongoing. It is also cleared by hardware when the interface is disabled
(PE=0).
0: No read operation from Slave 2
1: Read operation performed from Slave 2
Bit 0= RF1 Read operation from Slave 1
This bit is set by hardware on reception of the direction bit in the I2C address byte for
Slave 1. It is cleared by software reading SR register when there is no communication
ongoing. It is also cleared by hardware when the interface is disabled (PE=0).
0: No read operation from Slave 1
1: Read operation performed from Slave 1
I2C byte count register (I2C3SBCR)
Reset value: 0000 0000 (00h)
7
NB7
0
NB6
NB5
NB4
NB3
NB2
NB1
NB0
Read only
Bits 7:0 = NB [7:0] Byte Count Register
This register keeps a count of the number of bytes received or transmitted through any
of the three addresses. This byte count is reset after reception by a slave address of a
new transfer and is incremented after each byte is transferred. This register is not
limited by the full page length. It is also cleared by hardware when the interface is
disabled (PE =0).
Doc ID 12321 Rev 6
181/247
On-chip peripherals
ST72344xx, ST2345xx
I2C slave 1 address register (I2C3SSAR1)
Reset value: 0000 0000 (00h)
7
ADDR7
0
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
EN1
Read / Write
Bits 7:1 = ADDR[7:1] Address of Slave 1
This register contains the first 7 bits of Slave 1 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when the interface is disabled (PE =0).
Bit 0= EN1 Enable bit for Slave Address 1
This bit is used to enable/disable Slave Address 1. It is also cleared by hardware when
the interface is disabled (PE =0).
0: Slave Address 1 disabled
1: Slave Address 1 enabled
I2C slave 2 address register (I2C3SSAR2)
Reset value: 0000 0000 (00h)
7
ADDR7
0
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
EN2
Read / Write
Bits 7:1 = ADDR[7:1] Address of Slave 2.
This register contains the first 7 bits of Slave 2 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when the interface is disabled (PE =0).
Bit 0= EN2 Enable bit for Slave Address 2
This bit is used to enable/disable Slave Address 2. It is also cleared by hardware when
the interface is disabled (PE =0).
0: Slave Address 2 disabled
1: Slave Address 2 enabled
I2C slave 3 address register (I2C3SSAR3)
Reset value: 0000 0000 (00h)
7
ADDR7
ADDR6
0
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
EN3
Read / Write
Bit 7:1 = ADDR[7:1] Address of Slave 3
This register contains the first 7 bits of Slave 3 address (excluding the LSB) and is user
programmable. It is also cleared by hardware when the interface is disabled (PE =0).
Bit 0= EN3 Enable bit for Slave Address 3
This bit is used to enable/disable Slave Address 3. It is also cleared by hardware when
the interface is disabled (PE =0).
0: Slave Address 3 disabled
1: Slave Address 3 enabled
182/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
I2C slave 1 memory current address register (I2C3SCAR1)
Reset value: 0000 0000 (00h)
7
CA7
0
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Read only
Bit 7:0 = CA[7:0] Current address of Slave 1 buffer
This register contains the 8 bit offset of Slave Address 1 reserved area in RAM. It is
also cleared by hardware when the interface is disabled (PE =0).
I2C slave 2 memory current address register (I2C3SCAR2)
Reset value: 0000 0000 (00h)
7
CA7
0
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Read only
Bit 7:0 = CA[7:0] Current address of Slave 2 buffer
This register contains the 8-bit offset of Slave Address 2 reserved area in RAM. It is
also cleared by hardware when the interface is disabled (PE =0).
I2C slave 3 memory current address register (I2C3SCAR3)
Reset value: 0000 0000 (00h)
7
CA7
0
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Read only
Bit 6:0 = CA[6:0] Current address of Slave 3 buffer
This register contains the 8-bit offset of slave address 3 reserved area in RAM. It is also
cleared by hardware when the interface is disabled (PE =0).
Note:
Slave address 3 can store only 128 bytes. For slave address 3, CA7 bit will remain 0. i.e. if
the Byte Address sent is 0x80, then the Current Address register will hold the 0x00 value
due to an overflow.
Table 71.
I2C3S register map
Address
(Hex.)
Register
name
7
6
5
4
0060h
I2C3SCR1
PL1
PL0
0
ITER
0061h
I2C3SCR2
0
0
0
WP2
WP1
PE
BusyW
B/W
0062h
I2C3SSR
NACK
BERR
WF3
WF2
WF1
RF3
RF2
RF1
0063h
I2C3SBCR
NB7
NB6
NB5
NB4
NB3
NB2
NB1
NB1
0064h
I2C3SSAR1 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1
0065h
I2C3SCAR1
3
2
1
0
ITRE3 ITRE1/2 ITWE3 ITWE1/2
EN1
CA 7 .. CA0
Doc ID 12321 Rev 6
183/247
On-chip peripherals
Table 71.
Address
(Hex.)
184/247
ST72344xx, ST2345xx
I2C3S register map (continued)
Register
name
7
6
5
4
3
2
1
0066h
I2C3SSAR2 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1
0067h
I2C3SCAR2
0068h
I2C3SSAR3 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1
0069h
I2C3SCAR3
0
EN2
CA 7 .. CA0
CA 7 .. CA0
Doc ID 12321 Rev 6
EN3
ST72344xx, ST2345xx
On-chip peripherals
11.8
10-bit A/D converter (ADC)
11.8.1
Introduction
The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive
approximation converter with internal sample and hold circuitry. This peripheral has up to 16
multiplexed analog input channels (refer to device pinout description) that allow the
peripheral to convert the analog voltage levels from up to 16 different sources.
The result of the conversion is stored in a 10-bit Data Register. The A/D converter is
controlled through a Control/Status Register.
Note:
Whenever you change the channel or write in the ADCCSR register, the ADC conversion
starts again.
11.8.2
Main features
●
10-bit conversion
●
Up to 16 channels with multiplexed input
●
Linear successive approximation
●
Data register (DR) which contains the results
●
Conversion complete status flag
●
ON/OFF bit (to reduce consumption)
The block diagram is shown in Figure 84.
Figure 84. ADC block diagram
fCPU
DIV 4
0
DIV 2
fADC
1
EOC SPEED ADON
0
CH3
CH2
CH1
CH0
ADCCSR
4
AIN0
AIN1
ANALOG TO DIGITAL
ANALOG
MUX
CONVERTER
AINx
ADCDRH
D9
D8
ADCDRL
Doc ID 12321 Rev 6
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
185/247
On-chip peripherals
11.8.3
ST72344xx, ST2345xx
Functional description
The conversion is monotonic, meaning that the result never decreases if the analog input
does not, and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VAREF (high-level voltage reference), then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference), then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in Section 13:
Electrical characteristics.
RAIN is the maximum recommended impedance for an analog input signal. If the impedance
is too high, this will result in a loss of accuracy due to leakage and sampling not being
completed in the allotted time.
A/D converter configuration
The analog input ports must be configured as input, no pull-up, no interrupt. Refer to the
«I/O ports» chapter. Using these pins as analog inputs does not affect the ability of the port
to be read as a logic input.
In the ADCCSR register:
–
Select the CS[3:0] bits to assign the analog channel to convert.
Starting the conversion
In the ADCCSR register:
●
Set the ADON bit to enable the A/D converter and to start the conversion. From this
time on, the ADC performs a continuous conversion of the selected channel.
When a conversion is complete:
●
The EOC bit is set by hardware.
●
The result is in the ADCDR registers.
A read to the ADCDRH resets the EOC bit.
To read the 10 bits, perform the following steps:
Note:
1.
Poll the EOC bit
2.
Read the ADCDRL register
3.
Read the ADCDRH register. This clears EOC automatically.
The data is not latched, so both the low and the high data register must be read before the
next conversion is complete, so it is recommended to disable interrupts while reading the
conversion result.
To read only 8 bits, perform the following steps:
186/247
1.
Poll the EOC bit
2.
Read the ADCDRH register. This clears EOC automatically.
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
On-chip peripherals
Changing the conversion channel
The application can change channels during conversion. When software modifies the
CH[3:0] bits in the ADCCSR register, the current conversion is stopped, the EOC bit is
cleared, and the A/D converter starts converting the newly selected channel.
11.8.4
Low-power modes
Note:
The A/D converter may be disabled by resetting the ADON bit. This feature allows reduced
power consumption when no conversion is needed.
Table 72.
Mode description
Mode
11.8.5
Description
Wait
No effect on A/D Converter
Halt
A/D Converter disabled.
After wakeup from Halt mode, the A/D Converter requires a stabilization time
tSTAB (see Electrical characteristics) before accurate conversions can be
performed.
Interrupts
None.
11.8.6
Register description
Control/status register (ADCCSR)
Reset value: 0000 0000 (00h)
7
EOC
0
SPEED
ADON
0
CH3
CH2
CH1
CH0
Read/Write (Except bit 7 read only)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hardware when software reads the ADCDRH
register or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software.
0: fADC = fCPU/4
1: fADC = fCPU/2
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: Disable ADC and stop conversion
1: Enable ADC and start conversion
Bit 4 = Reserved. Must be kept cleared.
Doc ID 12321 Rev 6
187/247
On-chip peripherals
ST72344xx, ST2345xx
Bits 3:0 = CH[3:0] Channel Selection
These bits are set and cleared by software. They select the analog input to convert.
Table 73.
Channel selection
Channel pin(1)
CH3
CH2
CH1
CH0
AIN0
0
0
0
0
AIN1
0
0
0
1
AIN2
0
0
1
0
AIN3
0
0
1
1
AIN4
0
1
0
0
AIN5
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
AIN8
1
0
0
0
Reserved
1
0
0
1
AIN10
1
0
1
0
Reserved
1
0
1
1
AIN12
1
1
0
0
AIN13
1
1
0
1
AIN14
1
1
1
0
AIN15
1
1
1
1
1. The number of channels is device dependent. Refer to the device pinout description.
Data register (ADCDRH)
Reset value: 0000 0000 (00h)
7
D9
0
D8
D7
D6
D5
D4
D3
D2
Read Only
Bits 7:0 = D[9:2] MSB of Converted Analog Value
Data register (ADCDRL)
Reset value: 0000 0000 (00h)
7
0
0
0
0
0
0
Read Only
Bits7:2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Converted Analog Value
188/247
Doc ID 12321 Rev 6
0
D1
D0
ST72344xx, ST2345xx
Table 74.
On-chip peripherals
ADC register map and reset values
Address
(Hex.)
Register
label
7
6
5
4
3
2
1
0
0070h
ADCCSR
Reset value
EOC
0
SPEED
0
ADON
0
0
CH3
0
CH2
0
CH1
0
CH0
0
0071h
ADCDRH
Reset value
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
0072h
ADCDRL
Reset value
0
0
0
0
0
0
D1
0
D0
0
Doc ID 12321 Rev 6
189/247
Instruction set
ST72344xx, ST2345xx
12
Instruction set
12.1
ST7 addressing modes
The ST7 Core features 17 different addressing modes which can be classified in seven main
groups:
Table 75.
Addressing mode groups
Addressing mode
Example
Inherent
nop
Immediate
ld A,#$55
Direct
ld A,$55
Indexed
ld A,($55,X)
Indirect
ld A,([$55],X)
Relative
jrne loop
Bit operation
bset
byte,#5
The ST7 Instruction set is designed to minimize the number of bytes required per
instruction: To do so, most of the addressing modes may be subdivided in two submodes
called long and short:
●
Long addressing mode is more powerful because it can use the full 64-Kbyte address
space; however, it uses more bytes and more CPU cycles.
●
Short addressing mode is less powerful because it can generally only access page
zero (0000h - 00FFh range), but the instruction size is more compact, and faster. All
memory-to-memory instructions use short addressing modes only (CLR, CPL, NEG,
BSET, BRES, BTJT, BTJF, INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
The ST7 Assembler optimizes the use of long and short addressing modes.
Table 76.
ST7 addressing mode overview
Mode
Syntax
Destination/
source
Pointer
Pointer
address size (hex.)
Length
(bytes)
Inherent
nop
+0
Immedi
ate
ld A,#$55
+1
Short
Direct
ld A,$10
00..FF
+1
Long
Direct
ld A,$1000
0000..FFFF
+2
No
Offset
Direct
Indexed ld A,(X)
00..FF
+ 0 (with X register)
+ 1 (with Y register)
Short
Direct
Indexed ld A,($10,X)
00..1FE
+1
Long
Direct
Indexed ld A,($1000,X)
0000..FFFF
+2
Short
Indirect
ld A,[$10]
00..FF
00..FF
byte
+2
Long
Indirect
ld A,[$10.w]
0000..FFFF
00..FF
word
+2
190/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Table 76.
Instruction set
ST7 addressing mode overview (continued)
Mode
Syntax
Destination/
source
Pointer
Pointer
address size (hex.)
Length
(bytes)
Short
Indirect Indexed ld A,([$10],X)
00..1FE
00..FF
byte
+2
Long
Indirect Indexed ld A,([$10.w],X)
0000..FFFF
00..FF
word
+2
Relative Direct
jrne loop
PC-128/PC+127(1)
(1)
Relative Indirect
jrne [$10]
PC-128/PC+127
Bit
Direct
bset $10,#7
00..FF
Bit
Indirect
bset [$10],#7
00..FF
Bit
Direct
Bit
Indirect Relative btjt [$10],#7,skip
Relative btjt $10,#7,skip
+1
00..FF
byte
+2
+1
00..FF
byte
00..FF
+2
+2
00..FF
00..FF
byte
+3
1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.
12.1.1
Inherent
All Inherent instructions consist of a single byte. The opcode fully specifies all the required
information for the CPU to process the operation.
Table 77.
Inherent instructions
Inherent instruction
Function
NOP
No operation
TRAP
S/W Interrupt
WFI
Wait for interrupt (low-power mode)
HALT
Halt oscillator (lowest power mode)
RET
Subroutine return
IRET
Interrupt subroutine return
SIM
Set interrupt mask
RIM
Reset interrupt mask
SCF
Set carry flag
RCF
Reset carry flag
RSP
Reset stack pointer
LD
Load
CLR
Clear
PUSH/POP
Push/Pop to/from the stack
INC/DEC
Increment/Decrement
TNZ
Test negative or zero
CPL, NEG
1 or 2 complement
MUL
Byte Multiplication
Doc ID 12321 Rev 6
191/247
Instruction set
Table 77.
ST72344xx, ST2345xx
Inherent instructions (continued)
Inherent instruction
12.1.2
Function
SLL, SRL, SRA, RLC, RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
Immediate
Immediate instructions have 2 bytes; the first byte contains the opcode, the second byte
contains the operand value.
Table 78.
Immediate instructions
Immediate instruction
12.1.3
Function
LD
Load
CP
Compare
BCP
Bit Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Operations
Direct
In Direct instructions, the operands are referenced by their memory address.
The direct addressing mode consists of two submodes:
Direct (Short)
The address is a byte, thus requires only 1 byte after the opcode, but only allows 00 - FF
addressing space.
Direct (Long)
The address is a word, thus allowing 64-Kbyte addressing space, but requires 2 bytes after
the opcode.
12.1.4
Indexed (No Offset, Short, Long)
In this mode, the operand is referenced by its memory address, which is defined by the
unsigned addition of an index register (X or Y) with an offset.
The indirect addressing mode consists of three submodes:
192/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
Instruction set
Indexed (No offset)
There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space.
●
Indexed (Short)
The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE
addressing space.
●
Indexed (Long)
The offset is a word, thus allowing 64-Kbyte addressing space and requires 2 bytes
after the opcode.
12.1.5
Indirect (Short, Long)
The required data byte to do the operation is found by its memory address, located in
memory (pointer).
The pointer address follows the opcode. The indirect addressing mode consists of two
submodes:
Indirect (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing
space, and requires 1 byte after the opcode.
Indirect (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64-Kbyte addressing
space, and requires 1 byte after the opcode.
12.1.6
Indirect Indexed (Short, Long)
This is a combination of indirect and short indexed addressing modes. The operand is
referenced by its memory address, which is defined by the unsigned addition of an index
register value (X or Y) with a pointer value located in memory. The pointer address follows
the opcode.
The indirect indexed addressing mode consists of two submodes:
Indirect Indexed (Short)
The pointer address is a byte, the pointer size is a byte, thus allowing 00 - 1FE addressing
space, and requires 1 byte after the opcode.
Indirect Indexed (Long)
The pointer address is a byte, the pointer size is a word, thus allowing 64-Kbyte addressing
space, and requires 1 byte after the opcode.
Doc ID 12321 Rev 6
193/247
Instruction set
ST72344xx, ST2345xx
Table 79.
Instructions supporting direct, indexed, indirect and indirect indexed
addressing modes
Long and short instructions
LD
Load
CP
Compare
AND, OR, XOR
Logical Operations
ADC, ADD, SUB, SBC
Arithmetic Addition/subtraction operations
BCP
Bit Compare
Table 80.
12.1.7
Function
Short instructions
Short instructions only
Function
CLR
Clear
INC, DEC
Increment/Decrement
TNZ
Test Negative or Zero
CPL, NEG
1 or 2 Complement
BSET, BRES
Bit Operations
BTJT, BTJF
Bit Test and Jump Operations
SLL, SRL, SRA, RLC, RRC
Shift and Rotate Operations
SWAP
Swap Nibbles
CALL, JP
Call or Jump subroutine
Relative Mode (direct, indirect)
This addressing mode is used to modify the PC register value by adding an 8-bit signed
offset to it.
Table 81.
Relative direct/indirect instructions
Available relative direct/indirect instructions
Function
JRxx
Conditional Jump
CALLR
Call Relative
The relative addressing mode consists of two submodes:
Relative (Direct)
The offset follows the opcode.
Relative (Indirect)
The offset is defined in memory, of which the address follows the opcode.
194/247
Doc ID 12321 Rev 6
ST72344xx, ST2345xx
12.2
Instruction set
Instruction groups
The ST7 family devices use an instruction set consisting of 63 instructions. The instructions
may be subdivided into 13 main groups as illustrated in the following table:
Table 82.
Main instruction groups
Load and Transfer
LD
CLR
Stack operation
PUSH
POP
Increment/Decrement
INC
DEC
Compare and Tests
CP
TNZ
BCP
Logical operations
AND
OR
XOR
CPL
NEG
Bit Operation
BSET
BRES
Conditional Bit Test and Branch
BTJT
BTJF
Arithmetic operations
ADC
ADD
SUB
SBC
MUL
Shift and Rotates
SLL
SRL
SRA
RLC
RRC
SWAP
SLA
Unconditional Jump or Call
JRA
JRT
JRF
JP
CALL
CALLR
NOP
Conditional Branch
JRxx
Interruption management
TRAP
WFI
HALT
IRET
Condition Code Flag modification
SIM
RIM
SCF
RCF
RSP
RET
Using a prebyte
The instructions are described with 1 to 4 bytes.
In order to extend the number of available opcodes for an 8-bit CPU (256 opcodes), three
different prebyte opcodes are defined. These prebytes modify the meaning of the instruction
they precede.
The whole instruction becomes:
●
PC-2
End of previous instruction
●
PC-1
Prebyte
●
PC
Opcode
●
PC+1
Additional word (0 to 2) according to the number of bytes required to
compute the effective address
These prebytes enable instruction in Y as well as indirect addressing modes to be
implemented. They precede the opcode of the instruction in X or the instruction using direct
addressing mode. The prebytes are:
PDY 90
Replace an X-based instruction using immediate, direct, indexed, or inherent
addressing mode by a Y one.
PIX 92
Replace an instruction using direct, direct bit or direct relative addressing mode
to an instruction using the corresponding indirect addressing mode.
It also changes an instruction using X indexed addressing mode to an
instruction using indirect X indexed addressing mode.
PIY 91
Replace an instruction using X indirect indexed addressing mode by a Y one.
Doc ID 12321 Rev 6
195/247
Instruction set
12.2.1
ST72344xx, ST2345xx
Illegal opcode reset
In order to provide enhanced robustness to the device against unexpected behavior, a
system of illegal opcode detection is implemented. If a code to be executed does not
correspond to any opcode or prebyte value, a reset is generated. This, combined with the
Watchdog, allows the detection and recovery from an unexpected fault or interference.
Note:
A valid prebyte associated with a valid opcode forming an unauthorized combination does
not generate a reset.
Table 83.
Mnemo
196/247
Illegal opcode detection
Description
Function/Example
Dst
Src
H
I
N
Z
C
ADC
Add with Carry
A=A+M+C
A
M
H
N
Z
C
ADD
Addition
A=A+M
A
M
H
N
Z
C
AND
Logical And
A=A.M
A
M
N
Z
BCP
Bit compare A,
Memory
tst (A . M)
A
M
N
Z
BRES
Bit Reset
bres Byte, #3
M
BSET
Bit Set
bset Byte, #3
M
BTJF
Jump if bit is false (0) btjf Byte, #3, Jmp1
M
C
BTJT
Jump if bit is true (1)
M
C
CALL
Call subroutine
CALLR
Call subroutine
relative
CLR
Clear
CP
Arithmetic Compare
tst(Reg - M)
reg
CPL
One Complement
A = FFH-A
DEC
Decrement
dec Y
HALT
Halt
IRET
Interrupt routine
return
Pop CC, A, X, PC
INC
Increment
inc X
JP
Absolute Jump
jp [TBL.w]
JRA
Jump relative always
JRT
Jump relative
JRF
Never jump
JRIH
Jump if ext. interrupt
=1
JRIL
Jump if ext. interrupt
=0
JRH
Jump if H = 1
H=1?
JRNH
Jump if H = 0
H=0?
btjt Byte, #3, Jmp1
reg, M
0
1
N
Z
C
reg, M
N
Z
1
reg, M
N
Z
N
Z
N
Z
M
0
jrf *
Doc ID 12321 Rev 6
H
reg, M
I
C
ST72344xx, ST2345xx
Table 83.
Mnemo
Instruction set
Illegal opcode detection (continued)
Description
Function/Example
JRM
Jump if I = 1
I=1?
JRNM
Jump if I = 0
I=0?
JRMI
Jump if N = 1 (minus) N = 1 ?
JRPL
Jump if N = 0 (plus)
N=0?
JREQ
Jump if Z = 1 (equal)
Z=1?
JRNE
Jump if Z = 0 (not
equal)
Z=0?
JRC
Jump if C = 1
C=1?
JRNC
Jump if C = 0
C=0?
JRULT
Jump if C = 1
Unsigned <
Dst
Src
JRUGE Jump if C = 0
Jmp if unsigned >=
JRUGT Jump if (C + Z = 0)
Unsigned >
JRULE
Jump if (C + Z = 1)
Unsigned
工商网监
湘ICP备2023018690号
