STA501013TR

STA501 40V 3.5A DOUBLE POWER HALF BRIDGE MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION ■ ■ 200mΩ RdsON COMPLEMENTARY DMOS OUTPUT STAGE ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ THERMAL WARNING OUTPUT ■ UNDER VOLTAGE PROTECTION MULTIPOWER BCD TECHNOLOGY PowerSO36 ) s t( ORDERING NUMBER: STA501 c u d DESCRIPTION STA501 is a monolithic dual half bridge stage in Multipower BCD Technology. The device is particularly designed to make the output stage of a mono All-Digital High Efficiency e t le AUDIO APPLICATION CIRCUIT +3.3V PWRDN R57 10K R59 10K 24 PWRDN 25 FAULT 27 C53 100nF TH_WAR 28 VDD 21 VDD 22 VSS 33 VSS 34 o r P e t e l o C60 100nF O CONFIG TRI-STATE TH_WAR bs 23 26 C58 100nF C58 100nF IBIAS INA VCCSIGN VCCSIGN INA GND-Reg GND-Clean ) s ( ct du GNDSUB 14 12 13 29 30 REGULATORS M15 31 20 19 M16 10 N.C. 11 GND GND N.C. N.C. 7 VCCA C32 1µF 6 GNDA 4 VCCB C110 100nF C109 330pF R103 6 C33 1µF 3 OUTB OUTB M14 L113 22µH OUTA OUTA 1 N.C. C31 1µF GND 17 2 32 C55 1000µF GND VCCB 16 9 36 C30 1µF 8 35 +VCC VCC M17 INB INB o s b O 15 PROTECTIONS & LOGIC o r P (DDX™) amplifier capable to deliver 50W @ THD = 10% at Vcc 30V output power on 8Ω load. The input pins have threshold proportional to Ibias pin voltage. 5 R104 20 R102 6 C107 100nF C108 470nF C106 100nF C111 100nF L112 22µH GNDB D02AU1447 December 2003 1/8 STA501 PIN FUNCTION N° Pin 1 GND-SUB 35 ; 36 Vcc Sign 15 Vcc Positive Supply 12 Vcc Positive Supply 7 Vcc Positive Supply 4 Vcc Positive Supply 14 GND Negative Supply 13 GND Negative Supply 6 GND Negative Supply 5 GND Negative Supply 16 ; 17 N.C. 10 ; 11 N.C. 8;9 OUTA Output half bridge 2;3 OUTB Output half bridge 29 GND 30 GND 31 INA Input of half bridge 32 INB Input of half bridge 21 ; 22 Vdd 5V Regulator referred to ground 33 ; 34 Vss 5V Regulator referred to +Vcc 25 PWRDN 26 TRI-STATE 27 FAULT 28 s b O 19 2/8 Substrate ground Signal Positive Supply ) s ( ct c u d u d o Stand-by pin Hi-Z pin Fault pin advisor GND TH-WAR GND-clean 23 IBIAS 18 NC 20 GND-Reg Thermal warning advisor Logical ground High logical state setting voltage Not connected Ground for regulator Vdd e t le o s b O - r P e t e l o 24 Description o r P ) s t( STA501 FUNCTIONAL PIN STATUS PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT * 1 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorpion PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130C THWAR* 1 Normal operation * : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. PIN CONNECTION c u d VCCSign 36 1 GND-SUB 35 2 OUTB VSS 34 3 33 4 VCC INB 32 so OUTB VSS 5 GND INA 31 6 GND GND 30 7 VCC GND 29 8 OUTA 28 9 OUTA 27 10 N.C 26 11 N.C. PWRDN 25 12 VCC GND 24 13 GND IBIAS 23 14 GND VDD 22 15 VCC VDD 21 16 N.C. GND-Reg 20 17 N.C. GND-Clean 19 18 N.C. FAULT r P e (s) b O - ct u d o TRI-STATE s b O o r P VCCSign TH_WAR t e l o e t le ) s t( D02AU1449 3/8 STA501 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit VCE DC Supply Voltage (Pin 4,7,12,15) 40 V Vmax Maximum Voltage on pins 23 to 32 5.5 V 0 to 70 °C -40 to 150 °C Top Operating Temperature Range Tstg, Tj Storage and Junction Temperature THERMAL DATA Symbol Tj-case Parameter Min. Typ. Thermal Resistance Junction to Case (thermal pad) TjSD Thermal shut-down junction temperature 150 Twarn Thermal warning temperature 130 thSD Thermal shut-down hysteresis 25 Max. Unit 2.5 °C/W °C ) s t( °C c u d °C ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; Vcc = 30V; Tamb = 25°C unless otherwise specified) Symbol Parameter Test conditions RdsON Power Pchannel/Nchannel MOSFET RdsON Id=1A Idss Power Pchannel/Nchannel leakage Idss Vcc=35V gN Power Pchannel RdsON Matching Id=1A gP Power Nchannel RdsON Matching t c u Dt_s Low current Dead Time (static) Dt_d td ON tr tf b O - Unit 200 270 mΩ 50 µA 95 % 95 % High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8 Ω Id=3.5A; see fig. 3 50 ns Turn-on delay time Resistive load 100 ns Turn-off delay time Resistive load 100 ns Rise time Resistive load 25 ns Fall time Resistive load; as fig. 1 25 ns 36 V Ibias/2 +300mV V r P e VCC Supply voltage operating voltage VIN-H High level input voltage VIN-L Low level input voltage IIN-H Hi level Input current 4/8 so Max. ns t e l o s b O e t le Typ. 20 od td OFF (s) Id=1A o r P Min. see test circuit no.1; see fig. 1 10 10 Ibias/2 -300mV Pin voltage = Ibias V 1 µA STA501 ELECTRICAL CHARACTERISTCS (continued) Symbol IIN-L Parameter Test conditions Low level input current Min. Pin voltage = 0.3V Typ. IPWRDN-H Hi level PWRDN pin input current Ibias = 3.3V Max. Unit 1 µA 35 µA VL Low logical state voltage VL (pin PWRDN, TRISTATE) (note 1) Ibias = 3.3V VH High logical state voltage VH (pin PWRDN, TRISTATE) (note 1) Ibias = 3.3V 1.7 V IVCCPWRDN Supply Current from Vcc in Power Down PWRDN = 0 3 mA IFAULT Output Current pins FAULT -TH-WARN when FAULT CONDITIONS IVCC-hiz 0.8 Vpin = 3.3V V 1 Supply current from Vcc in Tristate Vcc=30V; Tri-state=0 22 IVCC Supply current from Vcc in operation (both channel switching) Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 50 Iout-sh Overcurrent protection threshold (short circuit current limit) VUV 3.5 P e let tpw-min Output minimum pulse width so No Load ) s t( mA uc d o r 6 Undervoltage protection threshold mA mA 8 A 7 70 V 150 ns b O - Notes: 1. The following table explains the VL, VH variation with Ibias Ibias VLmin VHmax 2.7 0.7 1.5 3.3 0.8 5 r P e u d o 0.85 t e l o ) s ( ct 1.7 1.85 Unit V V V LOGIC TRUTH TABLE (see fig. 2) TRI-STATE INA INB Q1 Q2 Q3 Q4 OUTPUT MODE 0 x x OFF OFF OFF OFF Hi-Z 1 0 0 OFF OFF ON ON DUMP 1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used s b O 5/8 STA501 Figure 1. Test Circuit. OUTY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t DTr Duty cycle = 50% DTf M58 OUTY INY R 8Ω M57 V67 = vdc = Vcc/2 + - gnd Figure 2. Q1 o s b O Q2 OUTA ) s ( ct OUTB Q3 o r P e Figure 3. t e l o s b O du o r P e t le +VCC INA INB Q4 GND D02AU1450 High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B DTout(A) M58 DTin(A) Q2 Q1 Iout=3.5A M57 Q3 DTout(B) Rload=8Ω OUTA INA L67 22µ C69 470nF L68 22µ C71 470nF C70 470nF M64 DTin(B) OUTB INB Iout=3.5A Q4 Duty cycle A and B: Fixed to have DC output current of 3.5A in the direction shown in figure 6/8 c u d D02AU1448 ) s t( M63 D02AU1451 STA501 DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e MIN. 3.25 mm TYP. 0.8 MAX. 3.5 3.3 1 MIN. 0.128 0.075 0.38 0.32 16 9.8 0 0.008 0.009 0.622 0.37 14.5 11.1 2.9 6.2 3.2 0.547 0.429 inch TYP. 0.031 0.2 0 0.22 0.23 15.8 9.4 5.8 2.9 0.003 0.015 0.012 0.630 0.38 0.039 0.57 0.437 0.114 0.244 1.259 0.228 0.114 0.65 11.05 e3 G H h L N s 0 15.5 0.026 0.435 0.075 0 15.9 0.61 1.1 1.1 0.031 10˚ (max) 8˚ (max) 0.8 OUTLINE AND MECHANICAL DATA 0.008 1 13.9 10.9 MAX. 0.138 0.13 0.039 0.003 0.625 0.043 0.043 (1) “D and E1” do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006”) (2) No intrusion allowed inwards the leads. ) s ( ct c u d ) s t( o r P (SLUG UP) PowerSO36 e t e l o s b O - u d o r P e t e l o s b O 7183931 7/8 STA501 c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. s b O The ST logo is a registered trademark of STMicroelectronics. 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