STA5630ATR

STA5630 Low power GPS RF front-end Data brief  production data Features ■ Integrated LNA ■ Low power consumption (< 25 mW) ■ 1.8 V supply voltage ■ GPS and Galileo compliant ■ Minimum external components ■ Serial interface ■ 3 bits A/D converter ■ CMOS 65 nm technology ■ Standard QFN-32 package ■ Ambient temperature range: -40 °C to +85 °C '!0'03 VFQFPN32 Description The STA5630 is a fully integrated RF front-end able to down-convert either the GPS L1 signal from 1575.42 MHz to 4.092 MHz. The STA5630 embeds high performance LNA minimizing external component count. The chip uses state of the art CMOS 65 nm technology. A 3-bit ADC converts the IF signal to Sign (SIGN) and Magnitude (MAG0 and MAG1). The magnitude bits are internally integrated in order to control the variable gain amplifiers. The VGA gain can be also set by the SPI interface. Table 1. The STA5630 accepts a range of reference clocks (10 to 52 MHz) and generates a 16.368 MHz sampling clock (GPS_CLK) for the baseband. The STA5630 embeds LDO to supply the internal core of the device facilitating requirements to external power supply. High performance, low power, and cost effective device, the STA5630 is the ideal solution for automotive, cellular and consumer battery powered applications. Device summary Order code Marking Package Packing STA5630TR STA5630 VFQFPN32 Tape and reel STA5630ATR (1) STA5630A VFQFPN32 Tape and reel 1. Automotive Grade. September 2013 Doc ID 16055 Rev 4 This is information on a product in full production. For further information contact your local STMicroelectronics sales office. 1/8 www.st.com 8 Contents STA5630 Contents 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2/8 Doc ID 16055 Rev 4 STA5630 1 Applications Applications Three main applications cases are considered and described hereafter. The first uses a passive antenna and only a single RF SAW in front of the internal LNA. It targets low cost and medium performance applications. In this case LNA is ON and RFA could be set at minimum gain if heavy blocker signals are present. The second uses a passive antenna and two RF SAWs. It maximizes the performances in presence of severe blockers. In this case LNA is ON and RFA is set at maximum gain. The third case uses an active antenna. This solution targets applications where the GPS antenna is far from the RF front-end. In this case the signal can be fed into either LNA or RFA input depending on the application conditions. STA5630 is suitable for baseband requiring 16.368/4.092 clock/RF interface and one, two or three bits samples. It accepts reference clocks (TCXO) in the range of 10-52 MHz and delivers a TCXO buffered copy to the baseband. The STA5630 has two default modes selectable by an external pin (MODE): ● MODE 0: the chip is configured to use 16.368 MHz as reference frequency, ● MODE 1: the chip is configured to use 26 MHz as reference frequency. Other modes are programmed through the serial interface 1.1 Block diagram Figure 1. Block diagram ,.!?/54 40?)&?0 2&!?). 40?)&?. )MAGE 2EJECTION -IXER &?)&-(Z ,.!?%. #OMPLEX)& FILTER 2&! 3)'. 6'! !'# ,.!?). ,.! "UFFER 6?). 3ELECTABLE"7 '03"7-(Z '!,),%/"7-(Z -!'  BITS -!' -!' $IGITAL )NTEGRATOR 0&$ #0  !$# '03?#,+ 6?/54 ,$/ &?,/-(Z 2 ž  6?2&/54 . ž   OR  30)?.#3 30)?#,+ CHIP CONFIG  30)?$) 30)?$/ 4#8/?#,+ $IGITAL )NTERFACE 6?)/ $EFAULT-ODE3ELECTOR -/$%4#8/ -(Z -/$%4#8/-(Z #()0?%. -/$% 4#8/ '!0'03 Doc ID 16055 Rev 4 3/8 Pin description STA5630 2 Pin description Table 2. Pin list description Pin # Pin name Description Type 1 TP_IF_P RF/IF receiver chain test positive output Analog output 2 V12_RFA RF amplifier (RFA) power supply (1.2V) Supply pin 3 RFA_IN RFA input, DC coupled 4 V12_IF IF section power supply (1.2V) 5 V12_OUT 6 V12_RF_OUT 7 V18_IN 8 Analog input Supply pin LDO IF/DIG output. Power supply (1.2V) delivered for IF/ADC/DIG_TCXO/VCO/VDD_IO VCC Output LDO RF output: Power supply (1.2V) delivered for LNA/RFA/MIXER VCC Output LDOs power supply (1.8V) Supply pin V12_LNA Low noise amplifier (LNA) power supply (1.2V) Supply pin LNA output 9 LNA_OUT 10 GND 11 LNA_IN 12 GND 13 CHIP_EN 14 Analog output Ground Ground LNA input, DC coupled Ground Analog input Ground Chip Enable Digital input MODE Power-On Default Configuration Selector Digital input 15 V18_IO I/Os power supply (1.8V) Supply pin 16 GPS_CLK GPS clock (16.368MHz) Digital output 17 MAG0 Mag0 data (Last significant bit) Digital output 18 MAG1 Mag1 data Digital output 19 SIGN Sign data (most significant bit) Digital output 20 SPI_CLK Serial Parallel Interface Clock Digital input 21 SPI_NCS Serial Parallel Interface Chip Select (Active Low - 1.8V domain) Digital input 22 SPI_DI Serial Parallel Interface Data Input Digital input 23 SPI_DO Serial Parallel Interface Data Output Digital output 24 TCXO_CLK TCXO Buffered Output Digital output 25 V12_IO Power supply for I/Os digital section (1.2V) 26 GND_IO I/Os Ground 27 TCXO_IN TCXO Input, DC coupled 28 V12_DIG Digital section and TCXO buffer input power supply (1.2V) Supply pin 29 V12_VCO VCO power supply (1.2V) Supply pin 30 V12_ADC ADC section power supply (1.2V) Supply pin 31 V12_MIX Mixer power supply (1.2V) Supply pin 32 TP_IF_N RF/IF receiver chain test negative output EP GND 4/8 Supply pin Ground Ground Analog input Analog output Ground Doc ID 16055 Rev 4 STA5630 Pin description ,.!?/54 '.$ ,.!?). '.$ #()0?%. -/$% 6?)/ '03?#,+ Pin connection diagram (bottom view)         -!' 6?2&?/54   3)'. 6?/54   30)?#,+ 6?)&   30)?.#3 2&!?).   30)?$) 6?2&!   30)?$/ 40?)&?0   4#8/?#,+         6?)/  '.$?)/  4#8/?). 6?). 6?$)' -!' 6?6#/  6?!$#  6?-)8 6?,.! 40?)&?. Figure 2. '!0'03 Doc ID 16055 Rev 4 5/8 Package information 3 STA5630 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 3. VFQFPN32 (5x5x1.0 mm) mechanical data and package dimensions MM INCH /54,).%!.$ -%#(!.)#!,$!4! $)- -). 490 -!8       !   !  ! -). 490 -!8    B       $       $       %       %       E , DDD           6&1&0.XXMM 6ERY&INE1UAD&LAT0ACKAGE.OLEAD ) '!0'03 6/8 Doc ID 16055 Rev 4 STA5630 4 Revision history Revision history Table 3. Document revision history Date Revision Changes 22-Jul-2009 1 Initial release. 03-Mar-2010 2 Updated: Features on page 1; Updated: Figure 1: Block diagram on page 3; Updated: Section 2: Pin description on page 4. 27-Jun-2012 3 Updated: Features on page 1 and Table 1: Device summary on page 1. 17-Sep-2013 4 Updated Disclaimer Doc ID 16055 Rev 4 7/8 STA5630 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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