STDVE003ABTR

STDVE003A Adaptive 3.4 Gbps 3:1 TMDS/HDMI signal equalizer Features ■ Compatible with the high-definition multimedia interface (HDMI) v1.3 digital interface ■ Conforms to the transition minimized differential signaling (TMDS) voltage standard on input and output channels ■ 340 MHz maximum clock speed operation supports all video formats with deep color at maximum refresh rates ■ 3.4 Gbps data rate per channel ■ Fully automatic adaptive equalizer ■ Single supply VCC: 3.135 to 3.465 V ■ ESD: > ± 5 KV HBM for all TMDS I/Os ■ Integrated open-drain I2C buffer for display data channel (DDC) ■ 5.3 V tolerant DDC and HPD I/Os ■ Lock-up free operation of I2C bus ■ 0 to 400 kHz clock frequency for I2C bus ■ Low capacitance of all the channels ■ Equalizer regenerates the incoming attenuated TMDS signal ■ Buffer drives the TMDS outputs over long PCB track lengths u d o TQFP80 r P e t e l o Description ) (s t c u d o r P e t e l o s b O ■ Low output skew and jitter ■ Tight input thresholds reduce bit error rates ■ On-chip selectable 50 Ω input termination ■ Low ground bounce ■ Data and control inputs provide undershoot clamp diode ■ -40°C to 85°C operating temperature range ■ Evaluation kit is available Table 1. ) s ( ct s b O The STDVE003A integrates a 4-channel 3.4 Gbps TMDS equalizer and a 3:1 switch to select one of the three HDMI ports. The 3-input HDMI ports can be either external ports or internal sources. Highspeed data paths and flow-through pinout minimize the internal device jitter and simplify the board layout. The equalizer overcomes the intersymbol interference (ISI) jitter effects from lossy cables. The buffer/driver on the output can drive the TMDS output signals over long distances. In addition to this, STDVE003A integrates the 50 Ω termination resistor on all the input channels to improve performance and reduce board space. The device can be placed in a low-power mode by disabling the output current drivers. The STDVE003A is ideal for advanced TV and STB applications supporting HDMI/DVI standard. The differential signal from the HDMI/DVI ports can be routed through the STDVE003A to guarantee good signal quality at the HDMI receiver. Designed for very low skew, jitter and low I/O capacitance, the switch preserves the signal integrity to pass the stringent HDMI compliance requirements. Device summary Order code Operating temperature Package Packaging STDEV003ABTR -40°C to 85°C TQFP80 Tape and reel December 2008 Rev 4 1/42 www.st.com 42 Contents STDVE003A Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Adaptive equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2.1 4 ) s ( ct 3.1 u d o SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.5 I2C DDC line repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.6 Power-down condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7 Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 Timing between HPD and DDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 r P e t e l o ) (s s b O Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 t c u 4.1 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 DC electrical characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 t e l o Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 Dynamic switching characteristics (I2C repeater) . . . . . . . . . . . . . . . . . . 26 5.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.2 Power supply requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 d o r P e s b O 5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.3.1 I2C lines application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2/42 STDVE003A List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Gain frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 OE_N operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SEL operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bias parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC specifications for TMDS differential inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC specifications for TMDS differential ouputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC specifications for OE_N, EQ_BOOST, SEL (S1, S2, S3) inputs . . . . . . . . . . . . . . . . . 19 Input termination resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 External reference resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DDC I/O pins (switch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Status pins (Y_HPD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Status pins (A_HPD, B_HPD, C_HPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input/output SDA, SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Clock and data rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Equalizer gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Differential output timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DDC I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Status pins (Y_HPD, A_HPD, B_HPD, C_HPD, SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I2C repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 TQFP80 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reel mechanical data (dimensions in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 3/42 List of figures STDVE003A List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. STDVE003A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Equalizer functional diagram (one signal pair) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DDC I2C bus repeater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STDVE003A in a digital TV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration (TQFP80 package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STDVE003A gain vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 TMDS output driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Test circuit for HDMI receiver and driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Test circuit for turn off and turn off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Test circuit for short circuit output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Propagation delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Turn-on and turn-off times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 TSK(O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TSK(P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 TSK(D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 AC waveform 1 (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Test circuit for AC measurements (I2C lines) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 I2C bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical application of I2C bus system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TQFP80 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 TQFP80 tape information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Reel information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 4/42 s b O STDVE003A 1 Block diagram Block diagram Figure 1. STDVE003A block diagram HDMI input port A 3:1 HDMI input select switch HDMI input port B Input stage Output driver/ transmitter Equalizer HDMI output port Y HDMI input port C 2 2 DDC port A DDC switch 2 DDC port B ) s ( ct IC repeater 2 DDC port Y 2 DDC port C S1,S2,S3 HPD port A HPD analog switch HPD port B HPD port C u d o HPD port Y r P e t e l o Figure 2. CS00061 s b O Equalizer functional diagram (one signal pair) ) (s S1, S2, S3 ct Data+ du 50 Ω termination selectable Switch (3:1) Pre-amp Data+ Equalizer ro Data- P e s b O t e l o Quantizer Output I driver Data- OE_N Current control REXT AM00715V1 5/42 Block diagram STDVE003A Figure 3. DDC I2C bus repeater 2 I C bus repeater Y_DDC_SDA A_DDC_SDA B_DDC_SDA C_DDC_SDA Switch A_DDC_SCL B_DDC_SCL Y_DDC_SCL C_DDC_SCL ) s ( ct S1, S2, S3 1.1 u d o r P e Application diagrams Figure 4. t c u od e t e ol t e l o STDVE003A in a digital TV ) (s Pr CS00062 s b O Game console DVD-R STB Digital TV STDVE003A HDMI receiver s b O CS00063 6/42 STDVE003A Pin configuration HPD2 VCC 62 61 63 GND SCL2 SDA2 65 2 58 A34 3 57 B34 GND 4 56 VCC B11 5 55 A33 A11 6 54 B33 VCC 7 53 B12 8 52 GND A32 o s b 43 42 35 36 37 38 39 40 Z1 GND SCL_SINK SDA_SINK HPD_SINK u d o VCC OE_N 41 GND Y4 SDA3 HPD3 44 34 24 25 GND SCL3 Y1 23 S3 46 45 32 22 -O B31 GND 33 21 S1 S2 20 VCC A31 48 VCC 19 31 17 18 B32 47 Z2 VCC REXT Y2 16 GND GND e t e l 30 15 29 14 A14 Z3 B14 Y3 13 28 VCC Pr 49 26 11 12 50 27 B13 A13 ) s ( ct u d o 51 STDVE003A Z4 9 10 VCC A12 GND ) s ( ct s b O DDC_2_PWR GND SCL1 DDC_Y_PWR t e l o 60 59 SDA1 EQ_BOOST r P e 64 67 1 DDC_1_PWR Table 2. 66 A21 B21 GND 68 VCC B22 70 69 GND A22 71 72 A23 74 B23 75 73 A24 B24 VCC 77 76 VCC GND 80 78 Pin configuration (TQFP80 package) HPD1 Figure 5. 79 2 Pin configuration DDC_3_PWR CS00064 Pin description Pin number Pin name Type Function 1 DDC_1_PWR Power External power to connect the pull-up resistor on DDC A ports. Connect to GND if unused. 2, 3 SDA1, SCL1 I/O Port1 DDC bus data and clock lines 4 GND Power Ground 5, 6 B11, A11 Input,TMDS Port 1 differential inputs for channel 1 7 VCC Power Supply voltage (3.3 V ± 5%) 8, 9 B12, A12 Input,TMDS Port 1 differential inputs for channel 2 10 GND Power Ground 11, 12 B13, A13 Input,TMDS Port 1 differential inputs for channel 3 13 VCC Power Supply voltage (3.3 V ± 5%) 14, 15 B14, A14 Input, TMDS Port 1 differential inputs for channel 4 7/42 Pin configuration STDVE003A Table 2. Pin description (continued) Pin number Pin name Type 16 GND Power Ground 17 VCC Power Supply voltage (3.3 V ± 5%) 18 REXT Analog Connect to GND through a 4.7 KΩ ± 1% precision reference resistor. Sets the output current to generate the output voltage compliant with TMDS 19 EQ_BOOST Input Provides equalizer boost function. Set to L for short cables and H for long cables. 20 DDC_Y_PWR Power External power to connect the pull-up resistor on DDC Y ports. Connect to GND if unused. 21, 23 S1,S2,S3 Input Source select inputs 24 GND Power Ground 25, 26 Y4, Z4 Output, TMDS Channel 4 differential outputs 27 VCC Power Supply voltage (3.3 V ± 5%) 28, 29 Y3, Z3 Output, TMDS Channel 3 differential outputs 30 GND Power Ground 31, 32 Y2, Z2 Output, TMDS Channel 2 differential outputs 33 VCC Power Supply voltage (3.3 V ± 5%) 34, 35 Y1, Z1 Output, TMDS Channel 1 differential outputs GND Power Ground GND Power Ground SCL_SINK I/O Sink side DDC bus clock line SDA_SINK I/O Sink side DDC bus data line Pr 37 38 e t e l 39 o s b O 8/42 ct u d o 36 ) (s Function ) s ( ct u d o r P e t e l o s b O 40 HPD_SINK Input Sink side hot plug detector input High: 5 V power signal asserted from source to sink and EDID is ready. Low: No 5 V power signal is asserted from source to sink or EDID is not ready. 41 DDC_3_PWR Power External power to connect the pull-up resistor on DDC C ports. Connect to GND if unused. 42 OE_N Input Output enable, active low 43 VCC Power Supply voltage (3.3 V ± 5%) 44 HPD3 Output Port 3 hot plug detector output. Open drain output. Connect an external resistor according to the HDMI specification. 45 SDA3 I/O Port 3 DDC bus data line 46 SCL3 I/O Port 3 DDC bus clock line STDVE003A Pin configuration Table 2. Pin description (continued) Pin number Pin name Type 47 GND Power 48, 49 B31, A31 Input, TMDS 50 VCC Power 51, 52 B32, A32 Input, TMDS 53 GND Power 54, 55 B33, A33 Input, TMDS 56 VCC Power 57, 58 B34, A34 Input, TMDS 59 GND Power Ground 60 DDC_2_PWR Power External power to connect the pull-up resistor on DDC B ports. Connect to GND if unused. 61 VCC Power Supply voltage (3.3 V ± 5%) Port 2 hot plug detector output. Open drain output. Connect an external resistor according to the HDMI specification. Supply voltage (3.3 V ± 5%) Port 3 differential inputs for channel 2 Ground Port 3 differential inputs for channel 3 Supply voltage (3.3 V ± 5%) u d o r P e t e l o 63 SDA2 I/O Port 2 DDC bus data line 64 SCL2 I/O Port 2 DDC bus clock line 65 GND 66 GND 67, 68 B21, A21 s ( t c )- du s b O Power Ground Power Ground Input, TMDS Port 2 differential inputs for channel 1 VCC Power B22, A22 Input, TMDS GND Power 73, 74 B23, A23 Input, TMDS 75 VCC Power 76, 77 B24, A24 Input, TMDS 78 GND Power Ground 79 VCC Power Supply voltage (3.3 V ± 5%) 80 HPD1 ro P e ) s ( ct Port 3 differential inputs for channel 4 Output 72 O Port 3 differential inputs for channel 1 HPD2 70, 71 o s b Ground 62 69 let Function Supply voltage (3.3 V ± 5%) Port 2 differential inputs for channel 2 Ground Port 2 differential inputs for channel 3 Supply voltage (3.3 V ± 5%) Port 2 differential inputs for channel 4 Port 1 hot plug detector output. Open drain output. Connect an external resistor according to the HDMI specification. 9/42 Functional description 3 STDVE003A Functional description The STDVE003A routes physical layer signals for high bandwidth digital video and is compatible with low voltage differential signaling standard like TMDS. The device passes the differential inputs from a video source to a common display when it is in the active mode of operation. The device conforms to the TMDS standard on both inputs and outputs. The low on-resistance and low I/O capacitance of the switch in STDVE003A result in a very small propagation delay. The device integrates SPDT-type switches for 3 differential data TMDS channels and 1 differential clock channel. Additionally, it integrates the switches for DDC and HPD line switching with I2C repeater on the DDC lines. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the I2C interfaces are isolated and the HPD pins are driven to L state. ) s ( ct 3.1 u d o Adaptive equalizer r P e The equalizer dramatically reduces the intersymbol interference (ISI) jitter and attenuation from long or lossy transmission media. The inputs present high impedance when the device is not active or when VCC is absent or 0 V. In all other cases, the 50 Ω termination resistors on input channels are present. t e l o s b O This circuit helps to improve the signal eye pattern significantly. Shaping is performed by the gain stage of the equalizer to compensate the signal degradation and then the signals are driven on to the output ports. ) (s The equalizer is fully adaptive and automatic in function providing smaller gain at low frequencies and higher gain at high frequencies. The default setting of EQ_BOOST = L is recommended for optimized operation. t c u d o r Frequency Gain in dB Gain in dB (MHz) (EQ_BOOST = 0) (EQ_BOOST = 1) 225 3 6.5 325 5 8.5 410 6.5 11 825 11 16 1650 16 21.5 Table 3. Gain frequency response P e t e l o bs O 10/42 STDVE003A Functional description Figure 6. STDVE003A gain vs. frequency ) s ( ct u d o r P e The STDVE003A equalizer is fully adaptive and automatic in function. The default setting of EQ_BOOST = L is recommended for optimal operation. The equalizer’s performance is optimized for all frequencies over the cable lengths from 1 m to 25 m at EQ_BOOST = L. If cable lengths greater than 25 m are desired in application, then EQ_BOOST = H setting is recommended. t e l o Input termination ) (s s b O The STDVE003A integrates precise 50 Ω ± 5% termination resistors, pulled up to VCC, on all its differential input channels. External terminations are not required. This gives better performance and also minimizes the PCB board space. These on-chip termination resistors should match the differential characteristic impedance of the transmission line. Since the output driver consists of current steering devices, an output voltage is not generated without a termination resistor. Output voltage levels are dependent on the value of the total termination resistance. The STDVE003A produces TMDS output levels for point-to-point links that are doubly terminated (100 Ω at each end). With the typical 10 mA output current, the STDVE003A produces an output voltage of 3.3 – 0.5 V = 2.8 V when driving a termination line terminated at each end. The input terminations are selectable thus saving power for the unselected ports. t c u d o r P e s b O t e l o Output buffers Each differential output of the STDVE003A drives external 50 Ω load (pull-up resistor) and conforms to the TMDS voltage standard. The output drivers consist of 10 mA differential current-steering devices. The driver outputs are short-circuit current limited and are high-impedance to ground when OE_N = H or the device is not powered. The current steering architecture requires a resistive load to terminate the signal to complete the transmission loop from VCC to GND through the termination resistor. Because the device switches the direction of the current flow and not voltage levels, the output voltage swing is determined by VCC minus the voltage drop across the termination resistor. The output current drivers are controlled by the OE_N pin and are turned off when OE_N is a high. A stable 10 mA current is derived by accurate internal current mirrors of a stable reference current which is generated by band-gap voltage 11/42 Functional description STDVE003A across the REXT. The differential output driver provides a typical 10 mA current sink capability, which provides a typical 500 mV voltage drop across a 50 Ω termination resistor. TMDS voltage levels The TMDS interface standard is a signaling method intended for point-to-point communication over a tightly controlled impedance medium. The TMDS standard uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI emissions and system susceptibility to noise. The device is capable of detecting differential signals as low as 100 mV within the entire common mode voltage range. 3.2 ) s ( ct Operating modes Table 4. OE_N operating modes Input u d o Output OE_N IN+ (ports A1, A2 or A3) IN(ports B1, B2 or B3) L H L L L H H X X OUT+ e t e l H O ) o s b Pr Function OUTL Active mode L H Active mode Hi-Z Hi-Z Low power mode The OE_N input activates a hardware power down mode. When the power down mode is active (OE_N = H), all input and output buffers and internal bias circuitry are powered-off and disabled. s ( t c Outputs are tri-stated in power-down mode. When exiting power-down mode, there is a delay associated with turning on band-references and input/output buffer circuits. u d o r P e t e l o s b O 12/42 STDVE003A 3.2.1 Functional description SEL operating modes The active source is selected by configuring source select inputs, S1, S2 and S3. The selected TMDS inputs from each port are switched through a 3-to-1 multiplexer. The I2C interface of the selected input port is linked to the I2C interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the I2C interfaces are isolated, and the HPD pins are kept low. Table 5. SEL operating modes Control pins I/O selected S1 S2 S3 Y/Z H X X A1/B1 L H X L L L L Hot-plug detect status SCL_SINK HPD1 HPD2 SCL1 SDA1 HPD_SINK L A2/B2 SCL2 SDA2 L HPD_SINK L H A3/B3 SCL3 SDA3 u d o L L HPD_SINK L None (Z) None (Z) L L L SDA_SINK s b O t e l o r P e HPD3 ) s ( ct L H: logic high; L: logic low; X: don't care; Z: high impedance 3.3 HPD pins ) (s t c u The input pin HPD_SINK is 5 V tolerant, allowing direct connection to 5 V signals. The switch is able to pass both 0 V and 5 V signal levels. The HPD_SINK is an input pin while the A_HPD, B_HPD and C_HPD are open-drain outputs. d o r 3.4 P DDC e channels t e ol s b O The DDC channels are designed with a bidirectional NMOS gate, providing 5 V signal tolerance. The 5 V tolerance allows direct connection to a standard I2C bus, thus eliminating the need for a level shifter. There should be external pull-up resistors on either side of the device on both the SCL and SDA lines. 13/42 Functional description STDVE003A I2C DDC line repeater 3.5 The device contains two identical bidirectional open-drain, non-inverting buffer circuits that enable I2C DDC bus lines to be extended without degradation in system performance. The STDVE003A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I2C bus, while retaining all the operating modes and features of the I2C system. This enables two buses of 400 pF bus capacitance to be connected in an I2C application. These buffers are operational from a supply V of 3.0 V to 3.6 V. The I2C bus capacitance limit of 400 pF restricts the number of devices and bus length. The STDVE003A enables the system designer to isolate the two halves of a bus, accommodating more I2C devices or longer trace lengths. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other bus is required. The STDVE003A can be used to run the I2C bus at both 5 V and 3.3 V interface levels. ) s ( ct The S1, S2 and S3 (SEL) lines act as control signals for the corresponding A, B or C ports. Note that the SEL line has an internal pull-down resistor. The SEL line should not change state during an I2C operation, because disabling during bus operation hangs the bus and enabling part way through a bus cycle could confuse the I2C parts being enabled. The SEL input should change state only when the global bus and the repeater port are in idle state, to prevent system failures. u d o r P e t e l o The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lock-up condition from occurring when the input low condition is released. ) (s s b O As with the standard I2C system, pull up resistors are required to provide the logic high levels on the buffered bus. The STDVE003A has standard open collector configuration of the I2C bus. The size of the pull up resistors depends on the system, but each side of the repeater must have a pull up resistor. t c u d o r This part is designed to work with standard mode and fast mode I2C devices. Standard mode I2C devices only specify 3 mA output drive, this limits the termination current to 3 mA in a generic I2C system where standard mode devices and multiple masters are possible. Under certain conditions, higher termination currents can be used. P e 3.6 s b O t e l o Power-down condition 3.7 The OE_N is used to disable most of the internal circuitry of STDVE003A that puts the device in a low power mode of operation. Bias The bandgap reference voltage over the external REXT reference resistor sets the internal bias reference current. This current and its factors (achieved by employing highly accurate and well matched current mirror circuit topologies) are generated on-chip and used by several internal modules. The 10 mA current used by the transmitter block is also generated using this reference current. It is important to ensure that the REXT value is within the ±1% tolerance range of its typical value. 14/42 STDVE003A Functional description Table 6. Bias parameter Parameter Bandgap voltage Min Typ Max Unit - 1.2 - V The output voltage swing depends on 3 components: supply voltage (Vsupply), termination resistor (RT) and current drive (Idrive). The supply voltage can vary from 3.3 V ±5%, termination resistor can vary from 50 Ω ±10%. The voltage on the output is given by: Vsupply −Idrive x RT. ) s ( ct The variation on Idrive must be controlled to ensure that the voltage on HDMI output is within the HDMI specification under all conditions. u d o This is achieved when: r P e 400 mV ≤Idrive x RT ≤600 mV with typical value centered at 500 mV. 3.8 t e l o Timing between HPD and DDC It is important to ensure that the I2C DDC interface is ready by the time the HPD detection is complete. s b O As soon as the discovery is finished by the HPD detection, the configuration data is exchanged between a source and sink through the I2C DDC interface. The STDVE003 Afs DDC interface is ready for communication as soon as the power supply to the chip is present and stable. When the desired port is enabled and the chip is out of shutdown mode, the I2C DDC lines can be used for communication. ) (s t c u d o r Thus, as soon as the HPD detection sequence is complete, the DDC interface can be readily used. There is no delay between the HPD detection and I2C DDC interface to be ready. P e t e l o s b O 15/42 Maximum rating 4 STDVE003A Maximum rating Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7. Absolute maximum ratings Symbol Parameter VCC VI IO TSTG TL V DC input voltage (TMDS ports) 1.7 to +4.0 V SEL (S1, S2, S3), OE_N -0.5 to +4.0 du V A_DDC_SDA, A_DDC_SCL, B_DDC_SDA, B_DDC_SCL, C_DDC_SDA, C_DDC_SCL,Y_DDC_SDA, Y_DDC_SCL, Y_HPD, A_HPD, B_HPD, C_HPD e t e l DC output current Storage temperature o s b Lead temperature (10 sec) O ) Thermal data t(s Parameter ΘJA Thermal coefficient (junction-ambient) uc d o r P e 16/42 ) s ( ct -0.5 to +4.0 Symbol t e l o Unit Supply voltage to ground Table 8. s b O Value o r P -0.5 to +6.0 V 120 mA -65 to +150 °C 300 °C TQFP80 Unit 48 °C/W STDVE003A Maximum rating 4.1 Recommended operating conditions 4.2 DC electrical characteristics TA = -40 to +85 °C, VCC = 3.3 V ± 5% (a) Table 9. Power supply characteristics Value Symbol VCC ICC Parameter Test condition Supply voltage Supply current Unit Min Typ Max 3.135 3.3 3.465 All inputs/outputs are enabled. Inputs are terminated with 50 Ω to VCC. Data rate = 3.4 Gbps Symbol u d o r P e 280 VCC = 3.465 V Table 10. ) s ( ct V mA t e l o s b O DC specifications for TMDS differential inputs Parameter Test condition ) (s Min Value Unit Typ Max 0 150 VTH Differential input high threshold (peak-to-peak) VCC = 3.465 V over the entire VCMR VTL Differential input low threshold Pr VCC = 3.465 V over the entire VCMR -150 VCC = 3.465 V 150 1560 mV VCC - 0.3 VCC - 0.04 V u d o e t e ol VID s b O VCMR CIN ct Differential input voltage (peak-to-peak)(1) Common mode voltage range Input capacitance IN+ or IN- to GND F = 1 MHz 0 3.5 mV mV pF 1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) |. a. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C. 17/42 Maximum rating Table 11. STDVE003A DC specifications for TMDS differential ouputs Value Symbol Parameter Test condition Unit Min Typ Max VOH Single-ended high level output voltage VCC-10 VCC+10 mV VOL Single-ended low level output voltage VCC-600 VCC-400 mV mV Single ended output swing voltage VCC = 3.3 V RTERM = 50 Ω 400 500 600 VOD Differential output voltage (peak-to-peak)(1) VCC = 3.3 V RTERM = 50 Ω 800 1000 1200 IOL Differential output low level current 8 10 |ISC| Output driver shortcircuit current (continuous) OUT± = GND through a 50 Ω resistor. See Figure 11 Output capacitance OUT+ or OUTto GND when tristate F = 1 MHz Vswing COUT O ) bs e t e ol ) s ( ct du 12 o r P 12 5.5 1. Differential output voltage is defined as | (OUT+ - OUT-) |. Differential input voltage is defined as | (IN+ - IN-) | s ( t c u d o r P e t e l o s b O 18/42 mV mA mA pF STDVE003A Table 12. Maximum rating DC specifications for OE_N, EQ_BOOST, SEL (S1, S2, S3) inputs Value Symbol Parameter Test condition Unit Min Max VIH HIGH level input voltage High level guaranteed 2.0 VIL LOW level input voltage Low level guaranteed -0.5 VIK Clamp diode voltage VCC = 3.465 V IIN = -18 mA -1.2 IIH Input high current VCC = 3.465 V VIN = VCC -5 +5 IIL Input low current VCC = 3.465 V VIN = GND -5 +5 CIN Input capacitance Pin to GND F = 1 MHz Table 13. RTERM Table 14. Parameter t c u od Parameter r P e Resistor for TMDS compliant voltage swing range let REXT o s b Symbol ) (s s b O -0.8 V ) s ( ct u d o r P e 45 Value 50 µA µA pF Unit 55 Ω Value Test condition Unit Min Tolerance for R = ±1% Typ Max 4.7 KΩ DDC I/O pins (switch) Value Parameter Test condition Unit Min VI(DDC) V External reference resistor Symbol Table 15. IIN = -10 mA 0.8 t e l o Test condition Differential input termination resistor on IN± channels relative to VCC V 3.5 Input termination resistor Symbol O Typ Input voltage GND Typ Max 5.3 V 19/42 Maximum rating Table 15. STDVE003A DDC I/O pins (switch) Value Symbol Parameter Test condition Unit Min II(leak) Typ VCC = 3.465 V A, B, C ports = 5.3 V Y port = 0.0 V Switch is isolated 6 µA VCC = 3.465 V A, B, C ports = 3.3 V Y port = 0.0 V Switch is isolated 2 µA Input leakage current VI=0 V F = 1 MHz Switch disabled CI/O VI=0 V F = 1 MHz Switch enabled t c u d o r P e t e l o 20/42 5 Input/output capacitance ) (s s b O Max r P e 9 t e l o s b O u d o ) s ( ct pF pF STDVE003A Table 16. Maximum rating Status pins (Y_HPD) Value Symbol Parameter Test condition Unit Min Typ Max VIH High level input voltage VCC = 3.3 V High level guaranteed 2.0 5.3 V VIL Low level input voltage VCC = 3.3 V Low level guaranteed GND 0.8 V 4 µA VCC = 3.465 V Y = 5.3 V II(leak) Table 17. VCC = 3.465 V Y = 3.3 V Parameter ) (s Input/output capacitance u d o ct Output low voltage (open drain I/Os) VOL r P e VI = 0 V F = 1 MHz Switch enabled VCC = 3.3 V IOL = 8 mA r P e t e l o s b O VI = 0 V F = 1 MHz Switch disabled µA u d o Test condition Voltage CI/O 2 Status pins (A_HPD, B_HPD, C_HPD)(1) Symbol V ) s ( ct Input leakage current Min Value Unit Typ GND Max 5.3 V 5 pF 9 pF 0.4 V 1. Typical parameters are measured at VCC = 3.3 V, TA = +25 °C. t e l o s b O 21/42 Maximum rating STDVE003A DC electrical characteristics (I2C repeater) 4.3 (TA = -40 to +85 °C, VCC = 3.3 V ± 5%, GND = 0 V; unless otherwise specified) Table 18. Supplies Value Symbol Parameter Test condition VCC DC supply voltage Unit Table 19. Min Typ Max 3.135 3.3 3.465 V Input/output SDA, SCL ) s ( t Value Symbol Parameter Test condition Unit Min VIH High level input voltage 0.7 VCC VIL Low level input voltage(1) -0.5 VILc Low level input voltage contention(1) -0.5 VIK Input clamp voltage II = -18 mA IIL Input current low (SDA, SCL) Input current low (SDA, SCL) IIH Input current high (SDA, SCL) VOL IOH let so b O CI r P e Output high level leakage current Input capacitance c u d 5.3 V 0.3 VCC V 0.4 V o r P − -1.2 V − − 1 μA VI = 3.465 V (SDA, SCL) − − 10 μA VI = 5.3 V (SDA, SCL) − − 10 μA IOL = 3 mA 0.4 V IOL = 6 mA 0.65 V s ( t c u d o LOW-level output voltage e t e ol Max bs O ) − Typ VO = 3.6 V; driver disabled − − 10 μA VO = 5.3 V; driver disabled − − 10 μA VI = 3 V or 0 V − 6 7(2) pF 1. VIL specification is for the first low level seen by the SDA/SCL lines. VILc is for the second and subsequent low levels seen by the SDA/SCL lines. 2. The SCL/SDA CI is about 200 pF when VCC = 0 V. The STDVE003A should be used in applications where power is secured to the repeater but an active bus remains on either set of the SDA/SCL pins. 22/42 STDVE003A Maximum rating Dynamic switching characteristics(b) 4.4 TA = -40 to +85 °C, VCC = 3.3 V ± 5%, RTERM = 50 Ω ± 5%, CL = 5 pF). Typical values are at TA = +25 °C and VCC = 3.3 V. Table 20. Clock and data rate Value Symbol Parameter Test condition Unit Min Clock frequency (1/10th of the differential data rate) fCK Drate Table 21. Typ 25 Max 340 MHz ) s ( ct Signaling rate 3.4 u d o Equalizer gain Gbps Value Symbol Parameter Test condition Min e t e ol At all frequencies (EQ_BOOST = L) for short cables G_EQ Equalizer gain s b O At all frequencies (EQ_BOOST = H) for long cables Table 22. Parameter Differential data and clock output rise/fall times P e t e l o b. t c u d o r tr tPLH Differential low to high propagation delay tPHL Differential high to low propagation delay s b O Unit Max 15 dB 20 dB Differential output timings Symbol tf ) (s Pr Typ Value Test condition Unit Min Typ Max 20% to 80% of VOD 75 150 240 ps 80% to 20% of VOD 75 150 240 ps Alternating 1 and 0 pattern at slow and fast data rates Measure at 50% VOD between input to output 250 800 ps 250 800 ps The timing values in this section are tested during characterization and are guaranteed by design and simulation. Not tested in production. 23/42 Maximum rating Table 23. STDVE003A Skew times Value Symbol Parameter Test condition Unit Min tSK(O) Inter-pair channel-tochannel output skew tSK(P) Pulse skew tSK(D) Intra-pair differential skew | tPLH - tPHL | Output channel to channel skew tSK(CC) Table 24. Typ 25 Difference in propagation delay (tPLH or tPHL) among all output channels 50 Value Parameter Min tON tOFF r P e let o s b Table 26. TMDS output disable time Time from OE_N to OUT± change from active to tristate ) (s ps 80 ps 44 ps ) s ( t 125 ps l o s b O ct o r P Unit Typ Max 12 20 ns 6 10 ns DDC I/O pins Symbol O Time from OE_N to OUT± change from tristate to active u d o Table 25. ete Test condition TMDS output enable time 100 c u d Turn-on and turn-off times Symbol Max Parameter Value Test condition Unit Min Typ Max Refer to Section 4.5 Status pins (Y_HPD, A_HPD, B_HPD, C_HPD, SEL) Value Symbol Parameter Test condition Unit Min tPD(HPD) Propagation delay (from Y_HPD to the active port of HPD) TON/OFF Switch time (from port select to the CL = 10 pF latest valid status of HPD) 24/42 CL = 10 pF, RPU = 1 KΩ Typ Max 150 ns 50 ns STDVE003A Table 27. Maximum rating Jitter Value Symbol Parameter Test condition Unit Min PRBS pattern at 1.6 Gbps (800 MHz) Total jitter(1) tJIT Typ Max 35 ps (p-p) 1. Total jitter is measured peak-to-peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. Input differential voltage = VID = 500 mV, PRBS random pattern at 1.65 Gbps, tr=tf=50 ps (20% to 80%). Jitter parameter is not production-tested but guaranteed through characterization on a sample-to-sample basis. ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 25/42 Maximum rating STDVE003A Dynamic switching characteristics (I2C repeater) 4.5 TA = -40 to +85 °C, VCC = 3.3 V ± 5%. Typical values are at TA = +25 °C and VCC = 3.3 V. Table 28. I2C repeater(1) Value Symbol Parameter Test condition Unit Min fSCL Max Standard mode I2C clock frequency Low duration on SCL pin 100 kHz 400 kHz ) s ( ct Fast mode 100 KHz See Figure 19 Voltage on line = 5V Cmax=400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions. tLOW Typ 4.7 r P e u d o μs t e l o 400 KHz See Figure 19 Voltage on line = 5V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions. s b O 1.3 μs 100 KHz See Figure 19 Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions. 4.7 μs 400 KHz See Figure 19 Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions. 1.3 μs ) (s t c u d o r t e l o P e tLOW s b O 26/42 Low duration on SCL pin STDVE003A Table 28. Maximum rating I2C repeater(1) (continued) Value Symbol Parameter Test condition Unit Min 100 KHz See Figure 19 Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions tHIGH Max μs 4.0 High duration on SCL pin 400 KHz See Figure 19 Voltage on line = 5 V Cmax = 400 pF, Rmax=2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions bs High duration on SCL pin r P e t e l o du μs o r P 4.0 μs 0.6 μs O ) s ( t c u d o ) s ( ct 0.6 e t e ol 100 KHz Refer section 14.12, Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions tHIGH Typ 400 KHz See Figure 19 Voltage on line = 3.3 V, Cmax=400 pF, Rmax = 2 K Depends on input signal rise time. Includes the 20% time intervals on both transitions s b O 27/42 Maximum rating Table 28. STDVE003A I2C repeater(1) (continued) Value Symbol Parameter Test condition Unit Min 250 μs 400 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 300 μs ) s ( ct ns 450 ns 250 ns 100 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 300 ns 100 KHz Waveform 1 (Figure 17) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K 250 ns 100 KHz Waveform 1 (Figure 17) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K 450 ns 400 KHz Waveform 1 (Figure 17)(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K 300 ns 400 KHz Waveform 1(2) Voltage on line = 3.3 V Cmax = 400pF, Rmax = 2 K 300 ns 100 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K O ) s ( t c e t e ol s b O tf 28/42 e t e l o s b Propagation delay Pr du 250 400 KHz Waveform 1 (Figure 17) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K u d o Max 400 KHz Waveform 1 (Figure 17) Voltage on line = 5 V, Cmax = 400 pF, Rmax = 2 K 400 KHz Waveform 1 (Figure 17) Voltage on line = 3.3 V, Cmax = 400 pF, Rmax = 2 K tPHL Typ o r P Output fall time STDVE003A Table 28. Maximum rating I2C repeater(1) (continued) Value Symbol Parameter Test condition Unit Min Typ Max 100 KHz Waveform 1 (Figure 17) (2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K 300 ns 100 KHz Waveform 1 (Figure 17)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K 300 ns Output fall time tf ) s ( ct 400 KHz Waveform 1 (Figure 17)(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K tr du 300 ns 300 ns 100 KHz Waveform 1(2) Voltage on line = 5 V Cmax = 400 pF, Rmax = 2 K 1000 ns 100 KHz Waveform 1 (Figure 17)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K 1000 ns Output rise time 400 KHz Waveform 1 (Figure 17)(2) Voltage on line = 3.3 V Cmax = 400 pF, Rmax = 2 K e t e l o r P o s b tr ) s ( ct Output rise time du o r P -O 1. All the timing values are tested during characterization and are guaranteed by design and simulation. Not tested in production. e t e ol 2. The tr transition time is specified with maximum load of 2 kΩ pull-up resistance and 400 pF load capacitance. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times. Refer to Figure 9. s b O Table 29. Symbol ESD performance Parameter Test conditions Min Typ Max Unit TMDS I/Os Human body model ±5 kV Other I/Os Human body model ±2 kV ESD 29/42 Maximum rating Figure 7. STDVE003A Test circuit for electrical characteristics VCC CL VOUT+ VIN+ Pulse generator VINRT STDVE003A 100 Ω VOUT- RT CL ) s ( ct u d o r P e CS00065 t e l o 1. CL = load capacitance: include jig and probe capacitance. 2. RT = termination resistance; should be equal to ZOUT of the pulse generator. Figure 8. TMDS output driver ) (s t c u od r P e t e l o TMDS driver s b O VCC RT RT ZO = RT ZO = RT TMDS receiver s b O CS00069 1. ZO = characteristic impedance of the cable. 2. RT = termination resistance: should be equal to ZO of the cable. Both are equal to 50W. 30/42 STDVE003A Maximum rating Figure 9. Test circuit for HDMI receiver and driver VCC RT RT A VA RT Y VID TMDS receiver CL = 0.5pF TMDS driver VCC VY B Z VID = VA - VB VB VSwing = VY - VZ ) s ( ct RT VZ u d o r P e t e l o 1. RT = 50 Ω. ) (s CS00071 s b O t c u d o r P e t e l o s b O 31/42 Maximum rating STDVE003A Figure 10. Test circuit for turn off and turn off times 10µF 0.1 µF 0.01µF CL 1.15 V VCC VIN+ 1.0 V 50 Ω ) s ( ct 1.2 V 50 Ω STDVE003A 1.15 V u d o VIN1.0 V r P e SHDN_N CL REXT Pulse generator 4.7 KΩ±1% 50 Ω ) (s s b O ct u d o 1. CL = 5 pF t e l o GND CS00072 Figure 11. Test circuit for short circuit output current r P e t e l o bs O 32/42 50 Ω ISC TMDS driver 50 Ω 0V or 3.465 V STDVE003A Maximum rating Figure 12. Propagation delays VCC VA VCM VID VCM VB VCC – 0.4 0.4V VID VID VID(p-p) 0V ) s ( ct -0.4V u d o tpHL VOD(O) tpLH 100% 80% 80% VOD(p-p) 20% ete Output l o s tr Pr 0V Differential 20% 0% VOD(U) tf b O Figure 13. Turn-on and turn-off times SHDN_N ) (s t c u od let r P e O o s b 3.0 V 1.50 V 1.50 V 0V tOFF tON VOH VOUT+ when VID= +150mV VOUT- when VID= -150mV 50% 50% 1.2 V tON tOFF 1.2 V VOUT+ when VID= -150mV VOUT- when VID= +150mV 50% 50% VOL 33/42 Maximum rating STDVE003A Figure 14. TSK(O) 3.5V 2.5V Data In 1.5V tpLHX tpHLX VOH 2.5V 2.5V Data Out at Port 0 VOL ) s ( ct tSK(o) VOH du Data Out at Port 1 tpLHY e t e ol tSK(o) = | tpLHy – tpLHx | or | tpHLy – tpHLx | Figure 15. TSK(P) ) (s t c u d o r P e t e l o s b O 34/42 Figure 16. TSK(D) s b O o r P tpHLY 2.5V VOL STDVE003A Maximum rating Figure 17. AC waveform 1 (I2C lines) Figure 18. Test circuit for AC measurements (I2C lines) ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e s b O t e l o Figure 19. I2C bus timing 35/42 Application information STDVE003A 5 Application information 5.1 Power supply sequencing Proper power-supply sequencing is advised for all CMOS devices. It is recommended to always apply VCC before applying any signals to the input/output or control pins. 5.2 Power supply requirements Bypass each of the VCC pins with 0.1 μF and 1 nF capacitors in parallel as close to the device as possible, with the smaller-valued capacitor as close to the VCC pin of the device as possible. ) s ( ct All VCC pins can be tied to a single 3.3 V power source. A 0.01 μF capacitor is connected from each VCC pin directly to ground to filter supply noise. The maximum power supply variation can only be ±5% as per the HDMI specifications. u d o r P e The maximum tolerable noise ripple on 3.3 V supply must be within a specified limit. 5.3 t e l o Differential traces s b O The high-speed TMDS inputs are the most critical parts for the device. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device. ) (s (a) Maintain 100-Ω differential transmission line impedance into and out of the STDVE003A. t c u (b) Keep an uninterrupted ground plane below the high-speed I/Os. (c) Keep the ground-path vias to the device as close as possible to allow the shortest return current path. d o r (d) Layout of the TMDS differential inputs should be with the shortest stubs from the connectors. P e t e l o s b O 36/42 Output trace characteristics affect the performance of the STDVE003A. Use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor. Run the differential traces close together to minimize the effects of the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to further prevent impedance discontinuities. STDVE003A Application information I2C lines application information 5.3.1 A typical application is shown in the figure below. In the example, the system master is running on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz. Master devices can be placed on either bus. Figure 20. Typical application of I2C bus system ) s ( ct u d o r P e t e l o s b O The STDVE003A DDC lines are 5 V tolerant; so it does not require any extra circuitry to translate between the different bus voltages. ) (s t c u d o r P e t e l o s b O 37/42 Package mechanical data 6 STDVE003A Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 21. TQFP80 package outline ) s ( ct u d o r P e t e l o ) (s t c u d o r P e t e l o s b O 38/42 s b O STDVE003A Package mechanical data Table 30. TQFP80 mechanical data Millimeters Symbol Min Typ Max A 1.200 A1 0.050 0.150 A2 0.950 1.000 1.050 b 0.170 0.220 0.270 c 0.090 0.200 D 14.000 D1 12.000 D2 9.500 e 0.500 E 14.000 E1 12.000 L 0.450 o s b L1 0° O ) k ccc u d o r P e let E2 ) s ( ct 9.500 0.600 0.750 1.000 7° 0.080 s ( t c Figure 22. TQFP80 tape information u d o r P e t e l o s b O 39/42 Package mechanical data STDVE003A Figure 23. Reel information ) s ( ct u d o r P e t e l o ) (s s b O t c u Table 31. P e d o r t e l o s b O 40/42 0084694_J Reel mechanical data (dimensions in mm) A C N T 330.2 13 ±0.25 178 24.4 STDVE003A 7 Revision history Revision history Table 32. Document revision history Date Revision 23-Apr-2008 1 Initial release. 26-May-2008 2 Minor updates: Table 4,Table 7, Table 23 and Table 29. 3 Added: Fully automatic adaptive equalizer feature Modified: title, features Chapter 3.1 and Figure 2 Removed: Table 21.: Equalizer gain 4 Updated ESD information in the Features section and Table 29: ESD performance on page 29. Modified Section 3.6: Power-down condition on page 14 and Table 7: Absolute maximum ratings on page 16. 21-Jul-2008 01-Dec-2008 Changes ) s ( ct u d o r P e t e l o ) (s s b O t c u d o r P e t e l o s b O 41/42 STDVE003A ) s ( ct Please Read Carefully: u d o Information in this document is provided solely in connection with ST products. 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