STEVAL-FKI868V1
Sub-1 GHz transceiver development kit based on S2-LP
Data brief
USB interface
RoHS compliant
Description
The STEVAL-FKI868V1 evaluation board is
based on the S2-LP sub-1 GHz ultra-low power
low data-rate transceiver, suitable for ISM bands
and Wireless M-Bus.
The main board is the NUCLEO-L152RE
development board, equipped with a low power
microcontroller STM32L to control the S2-LP and
the ST-LINK/V2-1 debugger and programmer for
firmware updating.
Features
S2-LP narrow band ultra-low power sub-1
GHz transceiver in a standalone RF Module
tuned for 860 - 940 MHz frequency bands
STM32 Nucleo development board with
STM32L152RE MCU
Suitable for Wireless M-Bus systems
Associated S2-LP development kit including,
documentation, firmware for STM32L and
GUI
Programmable RF output power up to +16
dBm
Modulation schemes: 2-FSK, 2-GFSK, 4FSK, 4-GFSK, OOK, and ASK
Air data rate from 0.3 to 500 kbps
Ultra-low power consumption:
6.7 mA RX
10 mA TX at +10 dBm
Excellent performance of receiver sensitivity
(up to -130 dBm)
Low duty cycle RX / TX operation mode
Automatic acknowledgement,
retransmission, and timeout protocol engine
SPI interface for microcontroller
November 2016
DocID029972 Rev 1
For further information contact your local STMicroelectronics sales
office
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www.st.com
DocID029972 Rev 1
CON 6
CN 4
CON 8
CN 3
CON 8
CN 2
CON1 0
CN 1
1
2
3
4
5
6
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
C1
C_4 .7U_060 3
10
9
8
7
6
5
4
3
2
1
0
R7
0
0
0
0
0
R1 4
R1 5
R1 6
3V 3
1
GP IO3
0
2
C3
VD D
NM
VSMPS 2
R2 0
XTA L
Y1
L_TBD_040 2
C1 9
R2 1
0 ohm
L1
C5
VD D
VDDSMP S
SMPS 1
SMPS 2
XOU T
XIN
SD N
R1 8 NM
C3 0
C_470 n_040 2
VSMPS 2
C_470p_040 2
C2 5
VDDANAS YNT H
S2 -LP
1
2
3
4
5
6
U2
C_100p_040 2 C1 1
L6
L_TBD_040 2
C_12p_040 2
C2 0
SD N
C6
C_100p_040 2
VDDANAS YNT H
C_470 n_040 2 C1 0
VDDSMP S
L_10U_080 5
L2
C_470 n_040 2
C1 2
C_1 u_060 3
C4
C_100p_040 2
VDDVCOT X
C_12p_040 2
C3 2
C_150 n_040 2
C_470 n_040 2
Vsmps_e xt
GP IO0
CS N
VD D
R1 3 0
R1 2
JP 1
2
Jumpe r2
SCL K
NM
CS N
SCL K
SD O
C3 3
C_100p_040 2
NM
R9
SD I
SD N
nS
0
GP IO1
GP IO2
1
R1 1 0
R1 0
R5
R4
R6
C_150 n_040 2
C2
VDDSMP S
VD D
R1 9 NM
C3 1
C_100p_040 2
VRS YNT H
C1 7
C_TBD_040 2
C2 6
C_150 n_040 2
C3 4
VSMPS 2
C2 7
L_TBD_040 2
L8
C1 8
C2 8
C1 6
C2 4
C_TBD_040 2
L_TBD_040 2
L1 0
C2 9
C_TBD_040 2
C_TBD_040 2
C_TBD_040 2
C2 1
J1
RF_ IN/OU T
C9
C_100 n_040 2
R3
R_100k_040 2
3V 3
C_TBD_040 2
C_TBD_040 2
L_TBD_040 2
C_TBD_040 2
SCL K
SD I
L_TBD_040 2
L4
L_TBD_040 2
L3
L_TBD_040 2
L9
8
7
6
5
C_TBD_040 2
M9564 0
VD D
L5
C3 5
C_100p_040 2
NM
R2 2
C_TBD_040 2
C1 5
U1
R2
R_100k_040 2
nS
Vc c
Q
nHOL D
nW
C
Vs s
D
C1 3
1
2
3
4
C_TBD_040 2
nS
SD O
C_TBD_040 2
C1 4
R1 7 NM
C2 3
C_100p_040 2
18 SCL K
17
SD I
16
SD O
15 VDDR XDIG
14
13
L_TBD_060 3
L7
C2 2
C_150 n_040 2
R1
R_100k_040 2
C8
C_100p_040 2
VDDR XDIG
SCL K
SD I
SD O
VDDR XDIG
RXP
RXN
VSMPS 2
C_470 n_040 2
C7
GP IO3
GP IO2
GP IO1
GP IO0
CS N
24
23
22
21
20
19
VRD IG
GP IO3
GP IO2
GP IO1
GP IO0
CS N
VDDANASYNT H
VRSYNT H
VREFVC O
VDDVCOT X
TX
VRR F
7
8
VRSYNT H
9
VDDVCOT X 10
11
12
2/4
GN D
1
25
VD D
Schematic diagram
STEVAL-FKI868V1
Schematic diagram
Figure 1: STEVAL-FKI868V1 circuit schematic
GSPG04 11161000SG
STEVAL-FKI868V1
2
Revision history
Revision history
Table 1: Document revision history
Date
Version
10-Nov-2016
1
Changes
Initial release.
DocID029972 Rev 1
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STEVAL-FKI868V1
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